[PATCH 1/3] drm/i915/psr: Kill psr.source_ok flag.

[PATCH 1/3] drm/i915/psr: Kill psr.source_ok flag.

[Dhinakaran Pandiyan]

This flag has become redundant since
commit 4d90f2d507ab ("drm/i915: Start tracking PSR state in crtc state")
It is set at the same place as psr.enabled, which is also exposed via
debugfs.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 1 -
 drivers/gpu/drm/i915/i915_drv.h     | 1 -
 drivers/gpu/drm/i915/intel_psr.c    | 2 --
 3 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bb63073d73f..6890340387b7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2529,7 +2529,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 	mutex_lock(&dev_priv->psr.lock);
 	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
-	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
 	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
 	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
 	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caebd5825279..cb1b69e7f439 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -754,7 +754,6 @@ struct i915_drrs {
 struct i915_psr {
 	struct mutex lock;
 	bool sink_support;
-	bool source_ok;
 	struct intel_dp *enabled;
 	bool active;
 	struct delayed_work work;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e32615eeada..17636dce1cb0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -522,8 +522,6 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 	}
 
 	dev_priv->psr.psr2_support = crtc_state->has_psr2;
-	dev_priv->psr.source_ok = true;
-
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
-- 
2.11.0

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[PATCH 2/3] drm/i915/psr: CAN_PSR() macro to check for PSR source and sink support.

[Dhinakaran Pandiyan]

The global variable dev_priv->psr.sink_support is set if an eDP sink
supports PSR. Use this instead of redoing the check with is_edp_psr().
Combine source and sink support checks into a macro that can be used to
return early from psr_{invalidate, single_frame_update, flush}.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 19 ++++---------------
 2 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f89d64..48676e99316e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1760,6 +1760,7 @@ static inline void intel_backlight_device_unregister(struct intel_connector *con
 
 
 /* intel_psr.c */
+#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
 void intel_psr_enable(struct intel_dp *intel_dp,
 		      const struct intel_crtc_state *crtc_state);
 void intel_psr_disable(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 17636dce1cb0..df9b1d7baefb 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,14 +56,6 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
-	if (!intel_dp_is_edp(intel_dp))
-		return false;
-
-	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
-}
-
 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -358,10 +350,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		&crtc_state->base.adjusted_mode;
 	int psr_setup_time;
 
-	if (!HAS_PSR(dev_priv))
-		return;
-
-	if (!is_edp_psr(intel_dp))
+	if (!CAN_PSR(dev_priv))
 		return;
 
 	if (!i915_modparams.enable_psr) {
@@ -794,7 +783,7 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 	u32 val;
 
-	if (!HAS_PSR(dev_priv))
+	if (!CAN_PSR(dev_priv))
 		return;
 
 	/*
@@ -843,7 +832,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 	struct drm_crtc *crtc;
 	enum pipe pipe;
 
-	if (!HAS_PSR(dev_priv))
+	if (!CAN_PSR(dev_priv))
 		return;
 
 	mutex_lock(&dev_priv->psr.lock);
@@ -883,7 +872,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 	struct drm_crtc *crtc;
 	enum pipe pipe;
 
-	if (!HAS_PSR(dev_priv))
+	if (!CAN_PSR(dev_priv))
 		return;
 
 	mutex_lock(&dev_priv->psr.lock);
-- 
2.11.0

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[PATCH 3/3] drm/i915/psr: Avoid initializing PSR if there is no sink support.

[Dhinakaran Pandiyan]

DPCD read for the eDP is complete by the time intel_psr_init() is
called, which means we can avoid initializing PSR structures and state
if there is no sink support.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++++-
 drivers/gpu/drm/i915/intel_psr.c    | 9 +++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6890340387b7..cc659b4b2a45 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2521,14 +2521,19 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	u32 stat[3];
 	enum pipe pipe;
 	bool enabled = false;
+	bool sink_support;
 
 	if (!HAS_PSR(dev_priv))
 		return -ENODEV;
 
+	sink_support = dev_priv->psr.sink_support;
+	seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
+	if (!sink_support)
+		return 0;
+
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->psr.lock);
-	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
 	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
 	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
 	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index df9b1d7baefb..863650366425 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -503,6 +503,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
+	if (WARN_ON(!CAN_PSR(dev_priv)))
+		return;
+
 	WARN_ON(dev_priv->drrs.dp);
 	mutex_lock(&dev_priv->psr.lock);
 	if (dev_priv->psr.enabled) {
@@ -633,6 +636,9 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 	if (!old_crtc_state->has_psr)
 		return;
 
+	if (WARN_ON(!CAN_PSR(dev_priv)))
+		return;
+
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
 		mutex_unlock(&dev_priv->psr.lock);
@@ -913,6 +919,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 
+	if (!dev_priv->psr.sink_support)
+		return;
+
 	/* Per platform default: all disabled. */
 	if (i915_modparams.enable_psr == -1)
 		i915_modparams.enable_psr = 0;
-- 
2.11.0

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✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/psr: Kill psr.source_ok flag.

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/psr: Kill psr.source_ok flag.
URL   : https://patchwork.freedesktop.org/series/35965/
State : success

== Summary ==

Series 35965v1 series starting with [1/3] drm/i915/psr: Kill psr.source_ok flag.
https://patchwork.freedesktop.org/api/1.0/series/35965/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-fail -> PASS       (fi-elk-e7500) fdo#103989 +1
Test gem_exec_reloc:
        Subgroup basic-write-cpu:
                incomplete -> PASS       (fi-byt-j1900)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                pass       -> DMESG-WARN (fi-skl-6700hq) fdo#101144

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:439s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:438s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:381s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:494s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:275s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:492s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:493s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:476s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:465s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:525s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:405s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:414s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:425s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:460s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:428s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:479s
fi-kbl-7560u     total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  time:510s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:469s
fi-kbl-r         total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:515s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:577s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:443s
fi-skl-6600u     total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:520s
fi-skl-6700hq    total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:539s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:507s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:511s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:447s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:544s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:417s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:571s
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:485s

d26e7804b83cf7d3754323d02afa5ff04326d33d drm-tip: 2018y-01m-03d-17h-48m-30s UTC integration manifest
2920bf42bbad drm/i915/psr: Avoid initializing PSR if there is no sink support.
f10a2c213555 drm/i915/psr: CAN_PSR() macro to check for PSR source and sink support.
97f18fc1b7cb drm/i915/psr: Kill psr.source_ok flag.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7603/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/psr: Kill psr.source_ok flag.

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/psr: Kill psr.source_ok flag.
URL   : https://patchwork.freedesktop.org/series/35965/
State : success

== Summary ==

Warning: bzip CI_DRM_3595/shard-glkb2/results3.json.bz2 wasn't in correct JSON format
Test gem_eio:
        Subgroup in-flight:
                pass       -> DMESG-WARN (shard-snb) fdo#104058
Test kms_flip:
        Subgroup wf_vblank-vs-dpms:
                pass       -> DMESG-WARN (shard-hsw) fdo#102614
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
                pass       -> FAIL       (shard-snb) fdo#101623
Test drv_suspend:
        Subgroup debugfs-reader-hibernate:
                skip       -> FAIL       (shard-hsw) fdo#103375

fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hsw        total:2713 pass:1537 dwarn:2   dfail:0   fail:10  skip:1164 time:9391s
shard-snb        total:2713 pass:1309 dwarn:2   dfail:0   fail:10  skip:1392 time:8076s
Blacklisted hosts:
shard-apl        total:2713 pass:1686 dwarn:1   dfail:0   fail:25  skip:1001 time:13674s
shard-kbl        total:2636 pass:1759 dwarn:1   dfail:0   fail:22  skip:853 time:10365s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7603/shards.html
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Re: [PATCH 3/3] drm/i915/psr: Avoid initializing PSR if there is no sink support.

[Rodrigo Vivi]

On Wed, Jan 03, 2018 at 09:38:24PM +0000, Dhinakaran Pandiyan wrote:
> DPCD read for the eDP is complete by the time intel_psr_init() is
> called, which means we can avoid initializing PSR structures and state
> if there is no sink support.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

sorry for the delay on this. you had responded to my questions on previous
thread and after reading your response again and applying the code it made sense
why to use sink_support instead of CAN_PSR on init.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++++-
>  drivers/gpu/drm/i915/intel_psr.c    | 9 +++++++++
>  2 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6890340387b7..cc659b4b2a45 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2521,14 +2521,19 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  	u32 stat[3];
>  	enum pipe pipe;
>  	bool enabled = false;
> +	bool sink_support;
>  
>  	if (!HAS_PSR(dev_priv))
>  		return -ENODEV;
>  
> +	sink_support = dev_priv->psr.sink_support;
> +	seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
> +	if (!sink_support)
> +		return 0;
> +
>  	intel_runtime_pm_get(dev_priv);
>  
>  	mutex_lock(&dev_priv->psr.lock);
> -	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
>  	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
>  	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
>  	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index df9b1d7baefb..863650366425 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -503,6 +503,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  	if (!crtc_state->has_psr)
>  		return;
>  
> +	if (WARN_ON(!CAN_PSR(dev_priv)))
> +		return;
> +
>  	WARN_ON(dev_priv->drrs.dp);
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (dev_priv->psr.enabled) {
> @@ -633,6 +636,9 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>  	if (!old_crtc_state->has_psr)
>  		return;
>  
> +	if (WARN_ON(!CAN_PSR(dev_priv)))
> +		return;
> +
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (!dev_priv->psr.enabled) {
>  		mutex_unlock(&dev_priv->psr.lock);
> @@ -913,6 +919,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>  	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
>  		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
>  
> +	if (!dev_priv->psr.sink_support)
> +		return;
> +
>  	/* Per platform default: all disabled. */
>  	if (i915_modparams.enable_psr == -1)
>  		i915_modparams.enable_psr = 0;
> -- 
> 2.11.0
> 
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Re: [PATCH 3/3] drm/i915/psr: Avoid initializing PSR if there is no sink support.

[Rodrigo Vivi]

On Fri, Jan 12, 2018 at 11:33:08PM +0000, Rodrigo Vivi wrote:
> On Wed, Jan 03, 2018 at 09:38:24PM +0000, Dhinakaran Pandiyan wrote:
> > DPCD read for the eDP is complete by the time intel_psr_init() is
> > called, which means we can avoid initializing PSR structures and state
> > if there is no sink support.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> sorry for the delay on this. you had responded to my questions on previous
> thread and after reading your response again and applying the code it made sense
> why to use sink_support instead of CAN_PSR on init.
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

now merged, thanks.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++++-
> >  drivers/gpu/drm/i915/intel_psr.c    | 9 +++++++++
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 6890340387b7..cc659b4b2a45 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2521,14 +2521,19 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> >  	u32 stat[3];
> >  	enum pipe pipe;
> >  	bool enabled = false;
> > +	bool sink_support;
> >  
> >  	if (!HAS_PSR(dev_priv))
> >  		return -ENODEV;
> >  
> > +	sink_support = dev_priv->psr.sink_support;
> > +	seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
> > +	if (!sink_support)
> > +		return 0;
> > +
> >  	intel_runtime_pm_get(dev_priv);
> >  
> >  	mutex_lock(&dev_priv->psr.lock);
> > -	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
> >  	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
> >  	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
> >  	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index df9b1d7baefb..863650366425 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -503,6 +503,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> >  	if (!crtc_state->has_psr)
> >  		return;
> >  
> > +	if (WARN_ON(!CAN_PSR(dev_priv)))
> > +		return;
> > +
> >  	WARN_ON(dev_priv->drrs.dp);
> >  	mutex_lock(&dev_priv->psr.lock);
> >  	if (dev_priv->psr.enabled) {
> > @@ -633,6 +636,9 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> >  	if (!old_crtc_state->has_psr)
> >  		return;
> >  
> > +	if (WARN_ON(!CAN_PSR(dev_priv)))
> > +		return;
> > +
> >  	mutex_lock(&dev_priv->psr.lock);
> >  	if (!dev_priv->psr.enabled) {
> >  		mutex_unlock(&dev_priv->psr.lock);
> > @@ -913,6 +919,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> >  	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
> >  		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
> >  
> > +	if (!dev_priv->psr.sink_support)
> > +		return;
> > +
> >  	/* Per platform default: all disabled. */
> >  	if (i915_modparams.enable_psr == -1)
> >  		i915_modparams.enable_psr = 0;
> > -- 
> > 2.11.0
> > 
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