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* [PATCH] drm/i915: Add tracking for CDCLK bypass frequency
@ 2018-01-17 17:25 Imre Deak
  2018-01-17 17:56 ` Ville Syrjälä
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Imre Deak @ 2018-01-17 17:25 UTC (permalink / raw)
  To: intel-gfx

The CDCLK bypass frequency can vary on upcoming platforms, so prepare
for that now by tracking its value in the CDCLK state.

Currently on BDW+ the bypass frequency is always the reference clock and
I didn't bother with earlier platforms since it's not all that clear
what's the bypass clock on those.

I also didn't bother adding support for changing this frequency, since
atm I don't see any need for it.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  2 +-
 drivers/gpu/drm/i915/intel_cdclk.c | 35 ++++++++++++++++++-----------------
 2 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c42015b05b47..49ccfc397feb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1791,7 +1791,7 @@ struct i915_oa_ops {
 };
 
 struct intel_cdclk_state {
-	unsigned int cdclk, vco, ref;
+	unsigned int cdclk, vco, ref, bypass;
 	u8 voltage_level;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ca36321eafac..f46a61d423a1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -858,7 +858,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 
 	skl_dpll0_update(dev_priv, cdclk_state);
 
-	cdclk_state->cdclk = cdclk_state->ref;
+	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 
 	if (cdclk_state->vco == 0)
 		goto out;
@@ -1006,7 +1006,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 	/* Choose frequency for this cdclk */
 	switch (cdclk) {
 	default:
-		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
 		WARN_ON(vco != 0);
 		/* fall through */
 	case 308571:
@@ -1085,7 +1085,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 
 	/* Is PLL enabled and locked ? */
 	if (dev_priv->cdclk.hw.vco == 0 ||
-	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
 		goto sanitize;
 
 	/* DPLL okay; verify the cdclock
@@ -1159,7 +1159,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = cdclk_state.ref;
+	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
 
@@ -1199,7 +1199,7 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
 	int ratio;
 
-	if (cdclk == dev_priv->cdclk.hw.ref)
+	if (cdclk == dev_priv->cdclk.hw.bypass)
 		return 0;
 
 	switch (cdclk) {
@@ -1224,7 +1224,7 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
 	int ratio;
 
-	if (cdclk == dev_priv->cdclk.hw.ref)
+	if (cdclk == dev_priv->cdclk.hw.bypass)
 		return 0;
 
 	switch (cdclk) {
@@ -1268,7 +1268,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 
 	bxt_de_pll_update(dev_priv, cdclk_state);
 
-	cdclk_state->cdclk = cdclk_state->ref;
+	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 
 	if (cdclk_state->vco == 0)
 		goto out;
@@ -1352,7 +1352,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	/* cdclk = vco / 2 / div{1,1.5,2,4} */
 	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
 	default:
-		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
 		WARN_ON(vco != 0);
 		/* fall through */
 	case 2:
@@ -1425,7 +1425,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
 	if (dev_priv->cdclk.hw.vco == 0 ||
-	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
 		goto sanitize;
 
 	/* DPLL okay; verify the cdclock
@@ -1514,7 +1514,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = cdclk_state.ref;
+	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
 
@@ -1574,7 +1574,7 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
 
 	cnl_cdclk_pll_update(dev_priv, cdclk_state);
 
-	cdclk_state->cdclk = cdclk_state->ref;
+	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 
 	if (cdclk_state->vco == 0)
 		goto out;
@@ -1660,7 +1660,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 	/* cdclk = vco / 2 / div{1,2} */
 	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
 	default:
-		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
 		WARN_ON(vco != 0);
 		/* fall through */
 	case 2:
@@ -1705,7 +1705,7 @@ static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
 	int ratio;
 
-	if (cdclk == dev_priv->cdclk.hw.ref)
+	if (cdclk == dev_priv->cdclk.hw.bypass)
 		return 0;
 
 	switch (cdclk) {
@@ -1732,7 +1732,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
 	if (dev_priv->cdclk.hw.vco == 0 ||
-	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
 		goto sanitize;
 
 	/* DPLL okay; verify the cdclock
@@ -1805,7 +1805,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = cdclk_state.ref;
+	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
@@ -1846,9 +1846,10 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
 			    const char *context)
 {
-	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
+	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
 			 context, cdclk_state->cdclk, cdclk_state->vco,
-			 cdclk_state->ref, cdclk_state->voltage_level);
+			 cdclk_state->ref, cdclk_state->bypass,
+			 cdclk_state->voltage_level);
 }
 
 /**
-- 
2.13.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Add tracking for CDCLK bypass frequency
  2018-01-17 17:25 [PATCH] drm/i915: Add tracking for CDCLK bypass frequency Imre Deak
@ 2018-01-17 17:56 ` Ville Syrjälä
  2018-01-18 14:21   ` Imre Deak
  2018-01-17 18:11 ` ✓ Fi.CI.BAT: success for " Patchwork
  2018-01-17 19:54 ` ✗ Fi.CI.IGT: warning " Patchwork
  2 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2018-01-17 17:56 UTC (permalink / raw)
  To: Imre Deak; +Cc: intel-gfx

On Wed, Jan 17, 2018 at 07:25:08PM +0200, Imre Deak wrote:
> The CDCLK bypass frequency can vary on upcoming platforms, so prepare
> for that now by tracking its value in the CDCLK state.
> 
> Currently on BDW+ the bypass frequency is always the reference clock and
> I didn't bother with earlier platforms since it's not all that clear
> what's the bypass clock on those.
> 
> I also didn't bother adding support for changing this frequency, since
> atm I don't see any need for it.
> 
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h    |  2 +-
>  drivers/gpu/drm/i915/intel_cdclk.c | 35 ++++++++++++++++++-----------------
>  2 files changed, 19 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c42015b05b47..49ccfc397feb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1791,7 +1791,7 @@ struct i915_oa_ops {
>  };
>  
>  struct intel_cdclk_state {
> -	unsigned int cdclk, vco, ref;
> +	unsigned int cdclk, vco, ref, bypass;
>  	u8 voltage_level;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ca36321eafac..f46a61d423a1 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -858,7 +858,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
>  
>  	skl_dpll0_update(dev_priv, cdclk_state);
>  
> -	cdclk_state->cdclk = cdclk_state->ref;
> +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;

My first instinct would have been to populate bypass in the PLL
readout function. I guess I just think of the bypass clock more
as a feature of the PLL. But I suppose it really doesn't matter
where we do this.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	if (cdclk_state->vco == 0)
>  		goto out;
> @@ -1006,7 +1006,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  	/* Choose frequency for this cdclk */
>  	switch (cdclk) {
>  	default:
> -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
>  		WARN_ON(vco != 0);
>  		/* fall through */
>  	case 308571:
> @@ -1085,7 +1085,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  
>  	/* Is PLL enabled and locked ? */
>  	if (dev_priv->cdclk.hw.vco == 0 ||
> -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
>  		goto sanitize;
>  
>  	/* DPLL okay; verify the cdclock
> @@ -1159,7 +1159,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
>  
> -	cdclk_state.cdclk = cdclk_state.ref;
> +	cdclk_state.cdclk = cdclk_state.bypass;
>  	cdclk_state.vco = 0;
>  	cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
>  
> @@ -1199,7 +1199,7 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  {
>  	int ratio;
>  
> -	if (cdclk == dev_priv->cdclk.hw.ref)
> +	if (cdclk == dev_priv->cdclk.hw.bypass)
>  		return 0;
>  
>  	switch (cdclk) {
> @@ -1224,7 +1224,7 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  {
>  	int ratio;
>  
> -	if (cdclk == dev_priv->cdclk.hw.ref)
> +	if (cdclk == dev_priv->cdclk.hw.bypass)
>  		return 0;
>  
>  	switch (cdclk) {
> @@ -1268,7 +1268,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  
>  	bxt_de_pll_update(dev_priv, cdclk_state);
>  
> -	cdclk_state->cdclk = cdclk_state->ref;
> +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
>  
>  	if (cdclk_state->vco == 0)
>  		goto out;
> @@ -1352,7 +1352,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	/* cdclk = vco / 2 / div{1,1.5,2,4} */
>  	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
>  	default:
> -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
>  		WARN_ON(vco != 0);
>  		/* fall through */
>  	case 2:
> @@ -1425,7 +1425,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
>  
>  	if (dev_priv->cdclk.hw.vco == 0 ||
> -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
>  		goto sanitize;
>  
>  	/* DPLL okay; verify the cdclock
> @@ -1514,7 +1514,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
>  
> -	cdclk_state.cdclk = cdclk_state.ref;
> +	cdclk_state.cdclk = cdclk_state.bypass;
>  	cdclk_state.vco = 0;
>  	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
>  
> @@ -1574,7 +1574,7 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
>  
>  	cnl_cdclk_pll_update(dev_priv, cdclk_state);
>  
> -	cdclk_state->cdclk = cdclk_state->ref;
> +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
>  
>  	if (cdclk_state->vco == 0)
>  		goto out;
> @@ -1660,7 +1660,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>  	/* cdclk = vco / 2 / div{1,2} */
>  	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
>  	default:
> -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
>  		WARN_ON(vco != 0);
>  		/* fall through */
>  	case 2:
> @@ -1705,7 +1705,7 @@ static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  {
>  	int ratio;
>  
> -	if (cdclk == dev_priv->cdclk.hw.ref)
> +	if (cdclk == dev_priv->cdclk.hw.bypass)
>  		return 0;
>  
>  	switch (cdclk) {
> @@ -1732,7 +1732,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
>  
>  	if (dev_priv->cdclk.hw.vco == 0 ||
> -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
>  		goto sanitize;
>  
>  	/* DPLL okay; verify the cdclock
> @@ -1805,7 +1805,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
>  
> -	cdclk_state.cdclk = cdclk_state.ref;
> +	cdclk_state.cdclk = cdclk_state.bypass;
>  	cdclk_state.vco = 0;
>  	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
>  
> @@ -1846,9 +1846,10 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
>  void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
>  			    const char *context)
>  {
> -	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
> +	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
>  			 context, cdclk_state->cdclk, cdclk_state->vco,
> -			 cdclk_state->ref, cdclk_state->voltage_level);
> +			 cdclk_state->ref, cdclk_state->bypass,
> +			 cdclk_state->voltage_level);
>  }
>  
>  /**
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Add tracking for CDCLK bypass frequency
  2018-01-17 17:25 [PATCH] drm/i915: Add tracking for CDCLK bypass frequency Imre Deak
  2018-01-17 17:56 ` Ville Syrjälä
@ 2018-01-17 18:11 ` Patchwork
  2018-01-17 19:54 ` ✗ Fi.CI.IGT: warning " Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-01-17 18:11 UTC (permalink / raw)
  To: Imre Deak; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Add tracking for CDCLK bypass frequency
URL   : https://patchwork.freedesktop.org/series/36636/
State : success

== Summary ==

Series 36636v1 drm/i915: Add tracking for CDCLK bypass frequency
https://patchwork.freedesktop.org/api/1.0/series/36636/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-warn -> FAIL       (fi-elk-e7500) fdo#103989 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:417s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:426s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:485s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:481s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:481s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:465s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:453s
fi-elk-e7500     total:224  pass:167  dwarn:10  dfail:0   fail:1   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:277s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:516s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:391s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:410s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:456s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:461s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:453s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:591s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:424s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:510s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:530s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:482s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:473s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:523s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:394s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:572s
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:473s

8c0a7186880fb43aa5a438e1b356020bcc7dcdf7 drm-tip: 2018y-01m-17d-17h-27m-05s UTC integration manifest
d002947ab410 drm/i915: Add tracking for CDCLK bypass frequency

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7701/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Add tracking for CDCLK bypass frequency
  2018-01-17 17:25 [PATCH] drm/i915: Add tracking for CDCLK bypass frequency Imre Deak
  2018-01-17 17:56 ` Ville Syrjälä
  2018-01-17 18:11 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-01-17 19:54 ` Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-01-17 19:54 UTC (permalink / raw)
  To: Imre Deak; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Add tracking for CDCLK bypass frequency
URL   : https://patchwork.freedesktop.org/series/36636/
State : warning

== Summary ==

Test kms_flip:
        Subgroup 2x-dpms-vs-vblank-race:
                pass       -> DMESG-WARN (shard-hsw)
Test gem_tiled_swapping:
        Subgroup non-threaded:
                incomplete -> PASS       (shard-snb) fdo#104218
Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                skip       -> PASS       (shard-snb) fdo#102365
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
                pass       -> FAIL       (shard-snb) fdo#101623
Test gem_eio:
        Subgroup in-flight-contexts:
                pass       -> DMESG-WARN (shard-snb) fdo#104058

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058

shard-hsw        total:2753 pass:1725 dwarn:2   dfail:0   fail:10  skip:1015 time:15369s
shard-snb        total:2753 pass:1317 dwarn:2   dfail:0   fail:11  skip:1423 time:7894s
Blacklisted hosts:
shard-apl        total:2753 pass:1717 dwarn:1   dfail:0   fail:20  skip:1015 time:13890s
shard-kbl        total:2735 pass:1824 dwarn:1   dfail:0   fail:22  skip:887 time:10282s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7701/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Add tracking for CDCLK bypass frequency
  2018-01-17 17:56 ` Ville Syrjälä
@ 2018-01-18 14:21   ` Imre Deak
  0 siblings, 0 replies; 5+ messages in thread
From: Imre Deak @ 2018-01-18 14:21 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Wed, Jan 17, 2018 at 07:56:22PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 17, 2018 at 07:25:08PM +0200, Imre Deak wrote:
> > The CDCLK bypass frequency can vary on upcoming platforms, so prepare
> > for that now by tracking its value in the CDCLK state.
> > 
> > Currently on BDW+ the bypass frequency is always the reference clock and
> > I didn't bother with earlier platforms since it's not all that clear
> > what's the bypass clock on those.
> > 
> > I also didn't bother adding support for changing this frequency, since
> > atm I don't see any need for it.
> > 
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h    |  2 +-
> >  drivers/gpu/drm/i915/intel_cdclk.c | 35 ++++++++++++++++++-----------------
> >  2 files changed, 19 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index c42015b05b47..49ccfc397feb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1791,7 +1791,7 @@ struct i915_oa_ops {
> >  };
> >  
> >  struct intel_cdclk_state {
> > -	unsigned int cdclk, vco, ref;
> > +	unsigned int cdclk, vco, ref, bypass;
> >  	u8 voltage_level;
> >  };
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index ca36321eafac..f46a61d423a1 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -858,7 +858,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
> >  
> >  	skl_dpll0_update(dev_priv, cdclk_state);
> >  
> > -	cdclk_state->cdclk = cdclk_state->ref;
> > +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> 
> My first instinct would have been to populate bypass in the PLL
> readout function. I guess I just think of the bypass clock more
> as a feature of the PLL. But I suppose it really doesn't matter
> where we do this.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

My thinking was that it's CDCLK choosing either the PLL output or the
bypass clock as a source (while refclk is connected directly both to
the PLL and the CDCLK as a source); but yes doesn't matter in practice
where it's inited, I leave it as-is for now.

Thanks for the review, pushed to drm-tip.

--Imre

> 
> >  
> >  	if (cdclk_state->vco == 0)
> >  		goto out;
> > @@ -1006,7 +1006,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> >  	/* Choose frequency for this cdclk */
> >  	switch (cdclk) {
> >  	default:
> > -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> > +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
> >  		WARN_ON(vco != 0);
> >  		/* fall through */
> >  	case 308571:
> > @@ -1085,7 +1085,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  	/* Is PLL enabled and locked ? */
> >  	if (dev_priv->cdclk.hw.vco == 0 ||
> > -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> > +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> >  		goto sanitize;
> >  
> >  	/* DPLL okay; verify the cdclock
> > @@ -1159,7 +1159,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> >  
> > -	cdclk_state.cdclk = cdclk_state.ref;
> > +	cdclk_state.cdclk = cdclk_state.bypass;
> >  	cdclk_state.vco = 0;
> >  	cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
> >  
> > @@ -1199,7 +1199,7 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> >  {
> >  	int ratio;
> >  
> > -	if (cdclk == dev_priv->cdclk.hw.ref)
> > +	if (cdclk == dev_priv->cdclk.hw.bypass)
> >  		return 0;
> >  
> >  	switch (cdclk) {
> > @@ -1224,7 +1224,7 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> >  {
> >  	int ratio;
> >  
> > -	if (cdclk == dev_priv->cdclk.hw.ref)
> > +	if (cdclk == dev_priv->cdclk.hw.bypass)
> >  		return 0;
> >  
> >  	switch (cdclk) {
> > @@ -1268,7 +1268,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> >  
> >  	bxt_de_pll_update(dev_priv, cdclk_state);
> >  
> > -	cdclk_state->cdclk = cdclk_state->ref;
> > +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> >  
> >  	if (cdclk_state->vco == 0)
> >  		goto out;
> > @@ -1352,7 +1352,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >  	/* cdclk = vco / 2 / div{1,1.5,2,4} */
> >  	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
> >  	default:
> > -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> > +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
> >  		WARN_ON(vco != 0);
> >  		/* fall through */
> >  	case 2:
> > @@ -1425,7 +1425,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> >  
> >  	if (dev_priv->cdclk.hw.vco == 0 ||
> > -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> > +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> >  		goto sanitize;
> >  
> >  	/* DPLL okay; verify the cdclock
> > @@ -1514,7 +1514,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> >  
> > -	cdclk_state.cdclk = cdclk_state.ref;
> > +	cdclk_state.cdclk = cdclk_state.bypass;
> >  	cdclk_state.vco = 0;
> >  	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
> >  
> > @@ -1574,7 +1574,7 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> >  
> >  	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> >  
> > -	cdclk_state->cdclk = cdclk_state->ref;
> > +	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> >  
> >  	if (cdclk_state->vco == 0)
> >  		goto out;
> > @@ -1660,7 +1660,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> >  	/* cdclk = vco / 2 / div{1,2} */
> >  	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
> >  	default:
> > -		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> > +		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
> >  		WARN_ON(vco != 0);
> >  		/* fall through */
> >  	case 2:
> > @@ -1705,7 +1705,7 @@ static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> >  {
> >  	int ratio;
> >  
> > -	if (cdclk == dev_priv->cdclk.hw.ref)
> > +	if (cdclk == dev_priv->cdclk.hw.bypass)
> >  		return 0;
> >  
> >  	switch (cdclk) {
> > @@ -1732,7 +1732,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> >  
> >  	if (dev_priv->cdclk.hw.vco == 0 ||
> > -	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> > +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> >  		goto sanitize;
> >  
> >  	/* DPLL okay; verify the cdclock
> > @@ -1805,7 +1805,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> >  
> > -	cdclk_state.cdclk = cdclk_state.ref;
> > +	cdclk_state.cdclk = cdclk_state.bypass;
> >  	cdclk_state.vco = 0;
> >  	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
> >  
> > @@ -1846,9 +1846,10 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
> >  void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> >  			    const char *context)
> >  {
> > -	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
> > +	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
> >  			 context, cdclk_state->cdclk, cdclk_state->vco,
> > -			 cdclk_state->ref, cdclk_state->voltage_level);
> > +			 cdclk_state->ref, cdclk_state->bypass,
> > +			 cdclk_state->voltage_level);
> >  }
> >  
> >  /**
> > -- 
> > 2.13.2
> 
> -- 
> Ville Syrjälä
> Intel OTC
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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-01-18 14:21 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-17 17:25 [PATCH] drm/i915: Add tracking for CDCLK bypass frequency Imre Deak
2018-01-17 17:56 ` Ville Syrjälä
2018-01-18 14:21   ` Imre Deak
2018-01-17 18:11 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-01-17 19:54 ` ✗ Fi.CI.IGT: warning " Patchwork

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