* [PATCH 1/4] drm/i915: Extending HDCP for HSW, BDW and BXT+
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
@ 2018-01-18 5:48 ` Ramalingam C
2018-01-18 5:48 ` [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only Ramalingam C
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2018-01-18 5:48 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, rodrigo.vivi
This patch extends the Key load process and hdcp initialization for
few more capable intel platforms i.e. HSW, BDW and BXT+.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 42 ++++++++++++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_hdmi.c | 3 +--
5 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0a4fc356145..7b54041a62f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8357,6 +8357,7 @@ enum skl_power_gate {
#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGER BIT(31)
#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
+#define HDCP_KEY_LOAD_TRIGGER BIT(8)
#define HDCP_KEY_STATUS _MMIO(0x66c04)
#define HDCP_FUSE_IN_PROGRESS BIT(7)
#define HDCP_FUSE_ERROR BIT(6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 68229f53d5b8..fb2e339405b5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6352,7 +6352,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_dp_add_properties(intel_dp, connector);
- if (INTEL_GEN(dev_priv) >= 9 && !intel_dp_is_edp(intel_dp)) {
+ if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5c8e260ca2bc..2de02f50e5fd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1848,6 +1848,7 @@ int intel_hdcp_init(struct intel_connector *connector,
int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
int intel_hdcp_check_link(struct intel_connector *connector);
+bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 827cab22f191..6ce6559897a6 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -49,13 +49,32 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
int ret;
u32 val;
- /* Initiate loading the HDCP key from fuses */
- mutex_lock(&dev_priv->pcu_lock);
- ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
- mutex_unlock(&dev_priv->pcu_lock);
- if (ret) {
- DRM_ERROR("Failed to initiate HDCP key load (%d)\n", ret);
- return ret;
+ /*
+ * On HSW and BDW HW loads the HDCP1.4 Key when Display comes
+ * out of reset. So if Key is not already loaded, its an error state.
+ */
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
+ return -ENXIO;
+
+ /*
+ * Initiate loading the HDCP key from fuses.
+ *
+ * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
+ * differ in the key load trigger process from other platforms.
+ */
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+ mutex_lock(&dev_priv->pcu_lock);
+ ret = sandybridge_pcode_write(dev_priv,
+ SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ mutex_unlock(&dev_priv->pcu_lock);
+ if (ret) {
+ DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
+ ret);
+ return ret;
+ }
+ } else {
+ I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
}
/* Wait for the keys to load (500us) */
@@ -575,6 +594,15 @@ static void intel_hdcp_prop_work(struct work_struct *work)
drm_modeset_unlock(&dev->mode_config.connection_mutex);
}
+bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
+{
+
+ /* PORT E doesn't have HDCP, and PORT F is disabled */
+ return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
+ !IS_CHERRYVIEW(dev_priv) &&
+ port < PORT_E);
+}
+
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim)
{
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 691f15b59124..5de1f966c926 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2304,8 +2304,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_hdmi_add_properties(intel_hdmi, connector);
- /* PORT E doesn't have HDCP, and PORT F is disabled */
- if (INTEL_GEN(dev_priv) >= 9 && port < PORT_E) {
+ if (is_hdcp_supported(dev_priv, port)) {
int ret = intel_hdcp_init(intel_connector,
&intel_hdmi_hdcp_shim);
if (ret)
--
2.7.4
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
2018-01-18 5:48 ` [PATCH 1/4] drm/i915: Extending HDCP for HSW, BDW and BXT+ Ramalingam C
@ 2018-01-18 5:48 ` Ramalingam C
2018-01-18 22:23 ` Sean Paul
2018-01-18 5:48 ` [PATCH 3/4] drm/i915: Start repeater auth on READY/CP_IRQ Ramalingam C
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Ramalingam C @ 2018-01-18 5:48 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, rodrigo.vivi
Second stage of HDCP authentication required only if the HDCP
sink is a repeater.
This patch imposes above condition on second stage HDCP authentication.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 6ce6559897a6..b48c72cd0906 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -493,7 +493,10 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
* on those as well.
*/
- return intel_hdcp_auth_downstream(intel_dig_port, shim);
+ if (repeater_present)
+ return intel_hdcp_auth_downstream(intel_dig_port, shim);
+
+ return 0;
}
static
--
2.7.4
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
2018-01-18 5:48 ` [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only Ramalingam C
@ 2018-01-18 22:23 ` Sean Paul
2018-01-19 3:50 ` C, Ramalingam
0 siblings, 1 reply; 11+ messages in thread
From: Sean Paul @ 2018-01-18 22:23 UTC (permalink / raw)
To: Ramalingam C; +Cc: daniel.vetter, intel-gfx, rodrigo.vivi
On Thu, Jan 18, 2018 at 11:18:06AM +0530, Ramalingam C wrote:
> Second stage of HDCP authentication required only if the HDCP
> sink is a repeater.
>
> This patch imposes above condition on second stage HDCP authentication.
Hi Ram,
This is already enforced in intel_hdcp_auth_downstream()
Thanks,
Sean
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 6ce6559897a6..b48c72cd0906 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -493,7 +493,10 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
> * on those as well.
> */
>
> - return intel_hdcp_auth_downstream(intel_dig_port, shim);
> + if (repeater_present)
> + return intel_hdcp_auth_downstream(intel_dig_port, shim);
> +
> + return 0;
> }
>
> static
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
2018-01-18 22:23 ` Sean Paul
@ 2018-01-19 3:50 ` C, Ramalingam
2018-01-19 5:39 ` Sean Paul
0 siblings, 1 reply; 11+ messages in thread
From: C, Ramalingam @ 2018-01-19 3:50 UTC (permalink / raw)
To: Sean Paul
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
Vivi, Rodrigo
> -----Original Message-----
> From: Sean Paul [mailto:seanpaul@chromium.org]
> Sent: Friday, January 19, 2018 3:54 AM
> To: C, Ramalingam <ramalingam.c@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; seanpaul@chromium.org;
> daniel.vetter@ffwll.ch; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Sharma,
> Shashank <shashank.sharma@intel.com>
> Subject: Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
>
> On Thu, Jan 18, 2018 at 11:18:06AM +0530, Ramalingam C wrote:
> > Second stage of HDCP authentication required only if the HDCP sink is
> > a repeater.
> >
> > This patch imposes above condition on second stage HDCP authentication.
>
> Hi Ram,
> This is already enforced in intel_hdcp_auth_downstream()
I am not able to locate any check for repeater capability at start of downstream auth.
I am not sure whether you are referring to number of downstream device count check.
That is valid after poll for ksv_fifo ready. We don't want to wait for 5Sec timeout in poll to detect the repeater cap.
And since the caller is handy with the flag for repeater cap, it is best to decide on the call for downstream auth itself.
Thanks
--Ram
>
> Thanks,
> Sean
>
> >
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_hdcp.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
> > b/drivers/gpu/drm/i915/intel_hdcp.c
> > index 6ce6559897a6..b48c72cd0906 100644
> > --- a/drivers/gpu/drm/i915/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> > @@ -493,7 +493,10 @@ static int intel_hdcp_auth(struct intel_digital_port
> *intel_dig_port,
> > * on those as well.
> > */
> >
> > - return intel_hdcp_auth_downstream(intel_dig_port, shim);
> > + if (repeater_present)
> > + return intel_hdcp_auth_downstream(intel_dig_port, shim);
> > +
> > + return 0;
> > }
> >
> > static
> > --
> > 2.7.4
> >
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
2018-01-19 3:50 ` C, Ramalingam
@ 2018-01-19 5:39 ` Sean Paul
0 siblings, 0 replies; 11+ messages in thread
From: Sean Paul @ 2018-01-19 5:39 UTC (permalink / raw)
To: C, Ramalingam
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
Vivi, Rodrigo
On Thu, Jan 18, 2018 at 7:50 PM, C, Ramalingam <ramalingam.c@intel.com> wrote:
>> -----Original Message-----
>> From: Sean Paul [mailto:seanpaul@chromium.org]
>> Sent: Friday, January 19, 2018 3:54 AM
>> To: C, Ramalingam <ramalingam.c@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; seanpaul@chromium.org;
>> daniel.vetter@ffwll.ch; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Sharma,
>> Shashank <shashank.sharma@intel.com>
>> Subject: Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only
>>
>> On Thu, Jan 18, 2018 at 11:18:06AM +0530, Ramalingam C wrote:
>> > Second stage of HDCP authentication required only if the HDCP sink is
>> > a repeater.
>> >
>> > This patch imposes above condition on second stage HDCP authentication.
>>
>> Hi Ram,
>> This is already enforced in intel_hdcp_auth_downstream()
>
> I am not able to locate any check for repeater capability at start of downstream auth.
>
> I am not sure whether you are referring to number of downstream device count check.
> That is valid after poll for ksv_fifo ready. We don't want to wait for 5Sec timeout in poll to detect the repeater cap.
>
> And since the caller is handy with the flag for repeater cap, it is best to decide on the call for downstream auth itself.
>
Thanks for clarifying, makes sense with the other patches in the set.
Sean
> Thanks
> --Ram
>>
>> Thanks,
>> Sean
>>
>> >
>> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_hdcp.c | 5 ++++-
>> > 1 file changed, 4 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>> > b/drivers/gpu/drm/i915/intel_hdcp.c
>> > index 6ce6559897a6..b48c72cd0906 100644
>> > --- a/drivers/gpu/drm/i915/intel_hdcp.c
>> > +++ b/drivers/gpu/drm/i915/intel_hdcp.c
>> > @@ -493,7 +493,10 @@ static int intel_hdcp_auth(struct intel_digital_port
>> *intel_dig_port,
>> > * on those as well.
>> > */
>> >
>> > - return intel_hdcp_auth_downstream(intel_dig_port, shim);
>> > + if (repeater_present)
>> > + return intel_hdcp_auth_downstream(intel_dig_port, shim);
>> > +
>> > + return 0;
>> > }
>> >
>> > static
>> > --
>> > 2.7.4
>> >
>>
>> --
>> Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/4] drm/i915: Start repeater auth on READY/CP_IRQ
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
2018-01-18 5:48 ` [PATCH 1/4] drm/i915: Extending HDCP for HSW, BDW and BXT+ Ramalingam C
2018-01-18 5:48 ` [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only Ramalingam C
@ 2018-01-18 5:48 ` Ramalingam C
2018-01-18 5:48 ` [PATCH 4/4] drm/i915: Check for downstream topology errors Ramalingam C
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2018-01-18 5:48 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, rodrigo.vivi
Second stage of HDCP authentication starts at CP_IRQ or at the
assertion of READY bit from Repeater.
Till then repeater will be authenticating with its downstream devices.
So authenticated device count, depth and ksv_list readable from
repeaters are valid only after assertion of READY/CP_IRQ.
This patch makes sure that READY is polled before reading any
topology information.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index b48c72cd0906..292c98fc8e72 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -150,6 +150,12 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
dev_priv = intel_dig_port->base.base.dev->dev_private;
+ ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
+ if (ret) {
+ DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
+ return ret;
+ }
+
ret = shim->read_bstatus(intel_dig_port, bstatus);
if (ret)
return ret;
@@ -161,12 +167,6 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
return 0;
}
- ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
- if (ret) {
- DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
- return ret;
- }
-
ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
if (!ksv_fifo)
return -ENOMEM;
--
2.7.4
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/4] drm/i915: Check for downstream topology errors
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
` (2 preceding siblings ...)
2018-01-18 5:48 ` [PATCH 3/4] drm/i915: Start repeater auth on READY/CP_IRQ Ramalingam C
@ 2018-01-18 5:48 ` Ramalingam C
2018-01-18 11:41 ` ✓ Fi.CI.BAT: success for HDCP1.4 implementation enhancement Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2018-01-18 5:48 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, rodrigo.vivi
HDCP compliant Repeaters can support max of 127 devices and max
depth of 7 for downstream topology.
If these max limits are exceeded, repeater will set the
topology error flags MAX_CASCADE_EXCEEDED and/or MAX_DEVS_EXCEEDED
in Bstatus followed by asserting READY/CP_IRQ for HDCP transmitter.
This patch check for these error flags as soon as READY bit is asserted.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 6 ++++++
include/drm/drm_hdcp.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 292c98fc8e72..6a78adc0456d 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -160,6 +160,12 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
if (ret)
return ret;
+ if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
+ DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
+ DRM_ERROR("Max Topology Limit Exceeded\n");
+ return -EPERM;
+ }
+
/* If there are no downstream devices, we're all done. */
num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
if (num_downstream == 0) {
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 43f7bd902b41..562fa7df2637 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -20,6 +20,8 @@
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
+#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
+#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
/* Slave address for the HDCP registers in the receiver */
#define DRM_HDCP_DDC_ADDR 0x3A
--
2.7.4
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^ permalink raw reply related [flat|nested] 11+ messages in thread* ✓ Fi.CI.BAT: success for HDCP1.4 implementation enhancement
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
` (3 preceding siblings ...)
2018-01-18 5:48 ` [PATCH 4/4] drm/i915: Check for downstream topology errors Ramalingam C
@ 2018-01-18 11:41 ` Patchwork
2018-01-18 13:40 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-19 5:40 ` [PATCH 0/4] " Sean Paul
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-18 11:41 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 implementation enhancement
URL : https://patchwork.freedesktop.org/series/36671/
State : success
== Summary ==
Series 36671v1 HDCP1.4 implementation enhancement
https://patchwork.freedesktop.org/api/1.0/series/36671/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
pass -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
fail -> PASS (fi-skl-6700k2) fdo#103191
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:420s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:427s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:371s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:482s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-elk-e7500 total:224 pass:168 dwarn:9 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:277s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:513s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:393s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:409s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:450s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:460s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:502s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:587s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:525s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:490s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:488s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:431s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:522s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s
fi-glk-dsi total:156 pass:142 dwarn:0 dfail:0 fail:0 skip:13
cb7287f74687f033ae8e50937b8294c16317170a drm-tip: 2018y-01m-18d-10h-31m-34s UTC integration manifest
602af39163af drm/i915: Check for downstream topology errors
0d2b0894ffa2 drm/i915: Start repeater auth on READY/CP_IRQ
f5d667f9fe35 drm/i915: II stage HDCP auth for repeater only
263fc472af0f drm/i915: Extending HDCP for HSW, BDW and BXT+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7706/issues.html
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^ permalink raw reply [flat|nested] 11+ messages in thread* ✓ Fi.CI.IGT: success for HDCP1.4 implementation enhancement
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
` (4 preceding siblings ...)
2018-01-18 11:41 ` ✓ Fi.CI.BAT: success for HDCP1.4 implementation enhancement Patchwork
@ 2018-01-18 13:40 ` Patchwork
2018-01-19 5:40 ` [PATCH 0/4] " Sean Paul
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-18 13:40 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 implementation enhancement
URL : https://patchwork.freedesktop.org/series/36671/
State : success
== Summary ==
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> DMESG-FAIL (shard-hsw) fdo#104218 +1
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass -> SKIP (shard-snb) fdo#103375 +1
Subgroup cursor-128x128-suspend:
skip -> PASS (shard-hsw) fdo#103540
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
skip -> PASS (shard-snb) fdo#101623 +1
Test kms_atomic_interruptible:
Subgroup legacy-setmode:
skip -> PASS (shard-snb)
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip -> PASS (shard-snb)
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2680 pass:1674 dwarn:1 dfail:1 fail:11 skip:991 time:14906s
shard-snb total:2675 pass:1287 dwarn:1 dfail:0 fail:10 skip:1377 time:7570s
Blacklisted hosts:
shard-apl total:2753 pass:1716 dwarn:1 dfail:0 fail:21 skip:1015 time:13811s
shard-kbl total:2735 pass:1811 dwarn:10 dfail:0 fail:23 skip:890 time:10516s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7706/shards.html
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 0/4] HDCP1.4 implementation enhancement
2018-01-18 5:48 [PATCH 0/4] HDCP1.4 implementation enhancement Ramalingam C
` (5 preceding siblings ...)
2018-01-18 13:40 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-01-19 5:40 ` Sean Paul
6 siblings, 0 replies; 11+ messages in thread
From: Sean Paul @ 2018-01-19 5:40 UTC (permalink / raw)
To: Ramalingam C; +Cc: Daniel Vetter, Intel Graphics Development, Vivi, Rodrigo
On Wed, Jan 17, 2018 at 9:48 PM, Ramalingam C <ramalingam.c@intel.com> wrote:
> This series extends the HDCP1.4 support for few more intel platforms.
> And also addresses few gaps found in the base HDCP1.4 implementation w.r.t
> HDCP1.4 specification.
>
Thanks for the patches, Ram. I've applied them with a couple of
checkpatch fixes around alignment + an extra line.
Sean
> Ramalingam C (4):
> drm/i915: Extending HDCP for HSW, BDW and BXT+
> drm/i915: II stage HDCP auth for repeater only
> drm/i915: Start repeater auth on READY/CP_IRQ
> drm/i915: Check for downstream topology errors
>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_hdcp.c | 65 ++++++++++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_hdmi.c | 3 +-
> include/drm/drm_hdcp.h | 2 ++
> 6 files changed, 57 insertions(+), 17 deletions(-)
>
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 11+ messages in thread