From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: clinton.a.taylor@intel.com
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Register definitions for DP Phy compiance
Date: Fri, 2 Mar 2018 10:10:21 -0800 [thread overview]
Message-ID: <20180302181021.GQ15113@intel.com> (raw)
In-Reply-To: <1519932972-7785-1-git-send-email-clinton.a.taylor@intel.com>
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actual use of these registers and bits?
thanks,
Rodrigo.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95a2e51..91152c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8702,6 +8702,24 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x640F0
> +#define DDI_DP_COMP_CTL_B 0x641F0
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x640f4
> +#define DDI_DP_COMP_PAT_B 0x641f4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-03-02 18:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-02 2:56 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-02 18:10 ` Rodrigo Vivi [this message]
2018-03-02 18:51 ` [PATCH] " Clint Taylor
2018-03-04 22:39 ` Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180302181021.GQ15113@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=Intel-gfx@lists.freedesktop.org \
--cc=clinton.a.taylor@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox