* [PATCH] drm/i915: Register definitions for DP Phy compiance
@ 2018-03-01 19:36 clinton.a.taylor
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: clinton.a.taylor @ 2018-03-01 19:36 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
DisplayPort Phy compliance test patterns register definitions.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51..91152c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8702,6 +8702,24 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x640F0
+#define DDI_DP_COMP_CTL_B 0x641F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x640f4
+#define DDI_DP_COMP_PAT_B 0x641f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Register definitions for DP Phy compiance
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
@ 2018-03-01 19:57 ` Patchwork
2018-03-02 2:56 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-01 19:57 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Register definitions for DP Phy compiance
URL : https://patchwork.freedesktop.org/series/39233/
State : success
== Summary ==
Series 39233v1 drm/i915: Register definitions for DP Phy compiance
https://patchwork.freedesktop.org/api/1.0/series/39233/revisions/1/mbox/
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:430s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:374s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:486s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:279s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:479s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:482s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:391s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:419s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:292s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:510s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:388s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:414s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:447s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:451s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:491s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:447s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:495s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:584s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:428s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:505s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:518s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:485s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:412s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:432s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:514s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:397s
Blacklisted hosts:
fi-cfl-u total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:499s
fi-cnl-y3 failed to collect. IGT log at Patchwork_8203/fi-cnl-y3/run0.log
7fe823aaeff7c50eeaf9b238a179b41771e08f9e drm-tip: 2018y-03m-01d-15h-58m-23s UTC integration manifest
daca9f902211 drm/i915: Register definitions for DP Phy compiance
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8203/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Register definitions for DP Phy compiance
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-03-02 2:56 ` Patchwork
2018-03-02 18:10 ` [PATCH] " Rodrigo Vivi
2018-03-04 22:39 ` Jani Nikula
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-02 2:56 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Register definitions for DP Phy compiance
URL : https://patchwork.freedesktop.org/series/39233/
State : success
== Summary ==
---- Possible new issues:
Test kms_fence_pin_leak:
incomplete -> PASS (shard-apl)
---- Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-apl) fdo#104945 +1
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-right-edge:
dmesg-warn -> PASS (shard-snb) fdo#105185 +2
fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
shard-apl total:3300 pass:1733 dwarn:1 dfail:0 fail:6 skip:1557 time:11366s
shard-hsw total:3461 pass:1768 dwarn:1 dfail:0 fail:1 skip:1690 time:11942s
shard-snb total:3461 pass:1359 dwarn:2 dfail:0 fail:1 skip:2099 time:6694s
Blacklisted hosts:
shard-kbl total:3435 pass:1932 dwarn:1 dfail:0 fail:6 skip:1495 time:9097s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8203/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Register definitions for DP Phy compiance
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-02 2:56 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-03-02 18:10 ` Rodrigo Vivi
2018-03-02 18:51 ` Clint Taylor
2018-03-04 22:39 ` Jani Nikula
3 siblings, 1 reply; 6+ messages in thread
From: Rodrigo Vivi @ 2018-03-02 18:10 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actual use of these registers and bits?
thanks,
Rodrigo.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95a2e51..91152c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8702,6 +8702,24 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x640F0
> +#define DDI_DP_COMP_CTL_B 0x641F0
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x640f4
> +#define DDI_DP_COMP_PAT_B 0x641f4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Register definitions for DP Phy compiance
2018-03-02 18:10 ` [PATCH] " Rodrigo Vivi
@ 2018-03-02 18:51 ` Clint Taylor
0 siblings, 0 replies; 6+ messages in thread
From: Clint Taylor @ 2018-03-02 18:51 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Intel-gfx
On 03/02/2018 10:10 AM, Rodrigo Vivi wrote:
> On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> DisplayPort Phy compliance test patterns register definitions.
> Hi Clint,
>
> what's the current plan to add the actual use of these registers and bits?
Supporting DP phy compliance has been mentioned by an interested
third-party. They needed the register definitions to be made available
to start development.
Clint
>
> thanks,
> Rodrigo.
>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 95a2e51..91152c9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8702,6 +8702,24 @@ enum skl_power_gate {
>> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
>> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>>
>> +/* DDI DP Compliance Control */
>> +#define DDI_DP_COMP_CTL_A 0x640F0
>> +#define DDI_DP_COMP_CTL_B 0x641F0
>> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
>> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
>> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
>> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
>> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
>> +
>> +/* DDI DP Compliance Pattern */
>> +#define DDI_DP_COMP_PAT_A 0x640f4
>> +#define DDI_DP_COMP_PAT_B 0x641f4
>> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
>> +
>> /* Sideband Interface (SBI) is programmed indirectly, via
>> * SBI_ADDR, which contains the register offset; and SBI_DATA,
>> * which contains the payload */
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Register definitions for DP Phy compiance
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
` (2 preceding siblings ...)
2018-03-02 18:10 ` [PATCH] " Rodrigo Vivi
@ 2018-03-04 22:39 ` Jani Nikula
3 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2018-03-04 22:39 UTC (permalink / raw)
To: clinton.a.taylor, Intel-gfx
On Thu, 01 Mar 2018, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DisplayPort Phy compliance test patterns register definitions.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95a2e51..91152c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8702,6 +8702,24 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x640F0
> +#define DDI_DP_COMP_CTL_B 0x641F0
Please prefix with underscores.
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x640f4
> +#define DDI_DP_COMP_PAT_B 0x641f4
Please prefix with underscores.
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-04 22:40 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-03-01 19:36 [PATCH] drm/i915: Register definitions for DP Phy compiance clinton.a.taylor
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-02 2:56 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-02 18:10 ` [PATCH] " Rodrigo Vivi
2018-03-02 18:51 ` Clint Taylor
2018-03-04 22:39 ` Jani Nikula
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox