From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written
Date: Fri, 20 Apr 2018 15:58:30 -0700 [thread overview]
Message-ID: <20180420225830.GQ1310@intel.com> (raw)
In-Reply-To: <20180420222758.6168-2-jose.souza@intel.com>
On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
>
> Bspec: 7721 and 8042
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>
> New patch in this series.
>
> drivers/gpu/drm/i915/intel_psr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0938df48107a..c907282dc82d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> I915_WRITE(EDP_PSR_DEBUG,
> EDP_PSR_DEBUG_MASK_MEMUP |
> EDP_PSR_DEBUG_MASK_HPD |
> - EDP_PSR_DEBUG_MASK_LPSP);
> + EDP_PSR_DEBUG_MASK_LPSP |
> + EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
What about only setting this bit before debugfs reads
and unseting it after that?
> }
> }
>
> --
> 2.17.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-04-20 22:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-20 22:27 [PATCH v3 1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit José Roberto de Souza
2018-04-20 22:27 ` [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written José Roberto de Souza
2018-04-20 22:57 ` Rodrigo Vivi
2018-04-24 0:42 ` Souza, Jose
2018-04-24 21:20 ` Rodrigo Vivi
2018-04-25 0:16 ` Dhinakaran Pandiyan
2018-04-25 20:37 ` Souza, Jose
2018-04-20 22:58 ` Rodrigo Vivi [this message]
2018-04-20 22:27 ` [PATCH v3 3/4] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
2018-04-25 0:18 ` Dhinakaran Pandiyan
2018-04-25 20:33 ` Souza, Jose
2018-04-20 22:27 ` [PATCH v3 4/4] drm/i915/psr/cnl: Set y-coordinate as valid in SDP José Roberto de Souza
2018-04-20 22:44 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit Patchwork
2018-04-20 23:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-20 23:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-24 23:47 ` [PATCH v3 1/4] " Dhinakaran Pandiyan
2018-04-24 23:57 ` Dhinakaran Pandiyan
2018-04-25 20:27 ` Souza, Jose
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180420225830.GQ1310@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=dhinakaran.pandiyan@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jose.souza@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox