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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written
Date: Tue, 24 Apr 2018 14:20:11 -0700	[thread overview]
Message-ID: <20180424212011.GK1994@intel.com> (raw)
In-Reply-To: <46b717278d0a8487e4a2226441eddb59a7562ed0.camel@intel.com>

On Mon, Apr 23, 2018 at 05:42:40PM -0700, Souza, Jose wrote:
> On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza
> > wrote:
> > > Any write in any display register was causing HW to exit PSR,
> > > masking it to allow more power savings. Writes to pipe related
> > > registers will still cause HW to exit PSR.
> > > This is already masked for PSR2.
> > 
> > This seems a good idea indeed with the test case on perspective.
> 
> what test cases are thinking? the current ones already do pages flips
> that will only touch the pipe related registers.
> 
> > 
> > But it needs more tests to make sure it doesn't break
> > "Display WA #0884: all"
> 
> I just tested the WA #0884 and it still causes PSR to exit. I have
> added a new debugfs that when read it writes to
> 'I915_WRITE(CURSURFLIVE(pipe), 0);' causing a PSR exit.

Interesting. Thanks a lot for checking this.
I guess we are safe then. DK?!

> 
> > 
> > Or we might need to revert that patch before moving with this idea.
> > 
> > > 
> > > Bspec: 7721 and 8042
> > > 
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > 
> > > New patch in this series.
> > > 
> > >  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 0938df48107a..c907282dc82d 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct
> > > intel_dp *intel_dp,
> > >  		I915_WRITE(EDP_PSR_DEBUG,
> > >  			   EDP_PSR_DEBUG_MASK_MEMUP |
> > >  			   EDP_PSR_DEBUG_MASK_HPD |
> > > -			   EDP_PSR_DEBUG_MASK_LPSP);
> > > +			   EDP_PSR_DEBUG_MASK_LPSP |
> > > +			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
> > >  	}
> > >  }
> > >  
> > > -- 
> > > 2.17.0
> > > 
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  reply	other threads:[~2018-04-24 21:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-20 22:27 [PATCH v3 1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit José Roberto de Souza
2018-04-20 22:27 ` [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written José Roberto de Souza
2018-04-20 22:57   ` Rodrigo Vivi
2018-04-24  0:42     ` Souza, Jose
2018-04-24 21:20       ` Rodrigo Vivi [this message]
2018-04-25  0:16         ` Dhinakaran Pandiyan
2018-04-25 20:37           ` Souza, Jose
2018-04-20 22:58   ` Rodrigo Vivi
2018-04-20 22:27 ` [PATCH v3 3/4] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
2018-04-25  0:18   ` Dhinakaran Pandiyan
2018-04-25 20:33     ` Souza, Jose
2018-04-20 22:27 ` [PATCH v3 4/4] drm/i915/psr/cnl: Set y-coordinate as valid in SDP José Roberto de Souza
2018-04-20 22:44 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit Patchwork
2018-04-20 23:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-20 23:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-24 23:47 ` [PATCH v3 1/4] " Dhinakaran Pandiyan
2018-04-24 23:57   ` Dhinakaran Pandiyan
2018-04-25 20:27   ` Souza, Jose

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