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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 2/6] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
Date: Mon,  1 Oct 2018 16:20:31 -0700	[thread overview]
Message-ID: <20181001232035.14506-2-jose.souza@intel.com> (raw)
In-Reply-To: <20181001232035.14506-1-jose.souza@intel.com>

ICL spec states that this bit is now reserved.

Bspec: 7722

v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++------
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27e650fe591b..8f436c73f184 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,7 +4195,7 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
-#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
@@ -4232,7 +4232,7 @@ enum {
 #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
 #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
-#define  PSR_EVENT_REGISTER_UPDATE		(1 << 5)
+#define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
 #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
 #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
 #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 3b5b8798c3ba..570ae1a2938a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -559,6 +559,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 mask;
 
 	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 	 * use hardcoded values PSR AUX transactions
@@ -584,12 +585,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	 * runtime_pm besides preventing  other hw tracking issues now we
 	 * can rely on frontbuffer tracking.
 	 */
-	I915_WRITE(EDP_PSR_DEBUG,
-		   EDP_PSR_DEBUG_MASK_MEMUP |
-		   EDP_PSR_DEBUG_MASK_HPD |
-		   EDP_PSR_DEBUG_MASK_LPSP |
-		   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-		   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+	mask = EDP_PSR_DEBUG_MASK_MEMUP |
+	       EDP_PSR_DEBUG_MASK_HPD |
+	       EDP_PSR_DEBUG_MASK_LPSP |
+	       EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+	if (INTEL_GEN(dev_priv) < 11)
+		mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+	I915_WRITE(EDP_PSR_DEBUG, mask);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-- 
2.19.0

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  reply	other threads:[~2018-10-01 23:20 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-01 23:20 [PATCH v3 1/6] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
2018-10-01 23:20 ` José Roberto de Souza [this message]
2018-10-01 23:20 ` [PATCH v3 3/6] drm/i915/psr: Remove PSR2 TODO error handling José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 4/6] drm/i915/psr: Use WA to force HW tracking to exit PSR2 José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 5/6] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 6/6] drm/i915/psr: Remove alpm from i915_psr José Roberto de Souza
2018-10-01 23:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/6] drm/i915/psr: Share PSR and PSR2 exit mask Patchwork
2018-10-01 23:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-02  0:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-02  5:05 ` ✓ Fi.CI.IGT: " Patchwork

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