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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH v3 5/6] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
Date: Mon,  1 Oct 2018 16:20:34 -0700	[thread overview]
Message-ID: <20181001232035.14506-5-jose.souza@intel.com> (raw)
In-Reply-To: <20181001232035.14506-1-jose.souza@intel.com>

For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
wrong value.

v3: Also update the value printed in debugfs

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ++-
 drivers/gpu/drm/i915/intel_psr.c    | 10 ++++++----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b4744a68cd88..14d58d121f2a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2723,7 +2723,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
 
 	seq_printf(m, "Main link in standby mode: %s\n",
-		   yesno(dev_priv->psr.link_standby));
+		   yesno(dev_priv->psr.link_standby &&
+		   !dev_priv->psr.psr2_enabled));
 
 	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
 
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 341af802b251..02dcc33750a8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -342,12 +342,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE);
 		dpcd_val |= DP_PSR_ENABLE_PSR2;
+	} else {
+		if (dev_priv->psr.link_standby)
+			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+
+		if (INTEL_GEN(dev_priv) >= 8)
+			dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	}
 
-	if (dev_priv->psr.link_standby)
-		dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
-	if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
-		dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
-- 
2.19.0

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  parent reply	other threads:[~2018-10-01 23:20 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-01 23:20 [PATCH v3 1/6] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 2/6] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 3/6] drm/i915/psr: Remove PSR2 TODO error handling José Roberto de Souza
2018-10-01 23:20 ` [PATCH v3 4/6] drm/i915/psr: Use WA to force HW tracking to exit PSR2 José Roberto de Souza
2018-10-01 23:20 ` José Roberto de Souza [this message]
2018-10-01 23:20 ` [PATCH v3 6/6] drm/i915/psr: Remove alpm from i915_psr José Roberto de Souza
2018-10-01 23:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/6] drm/i915/psr: Share PSR and PSR2 exit mask Patchwork
2018-10-01 23:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-02  0:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-02  5:05 ` ✓ Fi.CI.IGT: " Patchwork

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