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From: Lucas De Marchi <lucas.de.marchi@gmail.com>
To: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] drm/i915: Fix VIDEO_DIP_CTL bit shifts
Date: Thu, 4 Oct 2018 16:03:05 -0700	[thread overview]
Message-ID: <20181004230303.GA23914@ldmartin-desk.jf.intel.com> (raw)
In-Reply-To: <20181004205149.9286-1-dhinakaran.pandiyan@intel.com>

On Thu, Oct 04, 2018 at 01:51:49PM -0700, Dhinakaran Pandiyan wrote:
> The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
> definitions are unused.

If they are unused why are we fixing them instead of removing? Or better,
why did we add them?

Lucas De Marchi

> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Fixes: 7af2be6d54d4 ("drm/i915/icl: Add VIDEO_DIP registers")
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27e650fe591b..a0ad77b9212b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4584,6 +4584,15 @@ enum {
>  #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
>  #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
>  /* HSW and later: */
> +#define   DRM_DIP_ENABLE		(1 << 28)
> +#define   PSR_VSC_BIT_7_SET		(1 << 27)
> +#define   VSC_SELECT_MASK		(0x3 << 25)
> +#define   VSC_SELECT_SHIFT		25
> +#define   VSC_DIP_HW_HEA_DATA		(0 << 25)
> +#define   VSC_DIP_HW_HEA_SW_DATA	(1 << 25)
> +#define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)
> +#define   VSC_DIP_SW_HEA_DATA		(3 << 25)
> +#define   VDIP_ENABLE_PPS		(1 << 24)
>  #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
>  #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
>  #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
> @@ -4591,15 +4600,6 @@ enum {
>  #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
>  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
>  
> -#define  DRM_DIP_ENABLE			(1 << 28)
> -#define  PSR_VSC_BIT_7_SET		(1 << 27)
> -#define  VSC_SELECT_MASK		(0x3 << 26)
> -#define  VSC_SELECT_SHIFT		26
> -#define  VSC_DIP_HW_HEA_DATA		(0 << 26)
> -#define  VSC_DIP_HW_HEA_SW_DATA		(1 << 26)
> -#define  VSC_DIP_HW_DATA_SW_HEA		(2 << 26)
> -#define  VSC_DIP_SW_HEA_DATA		(3 << 26)
> -#define  VDIP_ENABLE_PPS		(1 << 24)
>  
>  /* Panel power sequencing */
>  #define PPS_BASE			0x61200
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  parent reply	other threads:[~2018-10-04 23:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-04 20:51 [PATCH] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
2018-10-04 21:28 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-10-04 23:03 ` Lucas De Marchi [this message]
2018-10-04 23:13   ` [PATCH] " Dhinakaran Pandiyan
2018-10-04 23:28     ` Manasi Navare
2018-10-05  0:00       ` Dhinakaran Pandiyan
2018-10-05  0:27         ` Manasi Navare
2018-10-05  2:56           ` Dhinakaran Pandiyan
2018-10-05 18:10             ` Manasi Navare
2018-10-05 18:33               ` Dhinakaran Pandiyan
2018-10-04 23:24   ` Rodrigo Vivi
2018-10-05  3:54 ` ✓ Fi.CI.IGT: success for " Patchwork

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