* [PATCH v11 0/2] Add XYUV format support
@ 2018-10-04 12:43 Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Stanislav Lisovskiy @ 2018-10-04 12:43 UTC (permalink / raw)
To: intel-gfx
Cc: Alexandru-Cosmin.Gheorghe, ville.syrjala, martin.peres,
juha-pekka.heikkila
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format support for skl+
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
include/uapi/drm/drm_fourcc.h | 1 +
5 files changed, 21 insertions(+), 1 deletion(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v11 1/2] drm: Introduce new DRM_FORMAT_XYUV
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
@ 2018-10-04 12:43 ` Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Stanislav Lisovskiy @ 2018-10-04 12:43 UTC (permalink / raw)
To: intel-gfx
Cc: Alexandru-Cosmin.Gheorghe, ville.syrjala, martin.peres,
juha-pekka.heikkila
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index be1d6aaef651..46971d9315da 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -190,6 +190,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 139632b87181..40754b18dc90 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,6 +151,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* 2 plane RGB + A
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
@ 2018-10-04 12:43 ` Stanislav Lisovskiy
2018-10-10 19:48 ` Ville Syrjälä
2018-10-04 13:21 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev8) Patchwork
` (4 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Stanislav Lisovskiy @ 2018-10-04 12:43 UTC (permalink / raw)
To: intel-gfx
Cc: Alexandru-Cosmin.Gheorghe, ville.syrjala, martin.peres,
juha-pekka.heikkila
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bc8e730ee1..ac24ac4b1d51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6501,7 +6501,7 @@ enum {
#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b2bab57cd113..9e65c47f3f4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static const uint32_t skl_pri_planar_formats[] = {
@@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
DRM_FORMAT_NV12,
};
@@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV8888;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR2101010:
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+ case DRM_FORMAT_XYUV8888:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_XYUV8888:
+ if (INTEL_GEN(dev_priv) < 9) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format, &format_name));
+ goto err;
+ }
+ break;
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 9600ccfc5b76..dec7546446d5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static uint32_t skl_planar_formats[] = {
@@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV8888,
};
static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev8)
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
@ 2018-10-04 13:21 ` Patchwork
2018-10-04 13:41 ` ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-04 13:21 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev8)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f58818541bcb drm: Introduce new DRM_FORMAT_XYUV
-:32: WARNING:LONG_LINE: line over 100 characters
#32: FILE: drivers/gpu/drm/drm_fourcc.c:228:
+ { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:44: WARNING:LONG_LINE_COMMENT: line over 100 characters
#44: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
total: 0 errors, 2 warnings, 0 checks, 14 lines checked
cb70f1ebba22 drm/i915: Adding YUV444 packed format support for skl+
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for Add XYUV format support (rev8)
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
` (2 preceding siblings ...)
2018-10-04 13:21 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev8) Patchwork
@ 2018-10-04 13:41 ` Patchwork
2018-10-05 9:32 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-04 13:41 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev8)
URL : https://patchwork.freedesktop.org/series/48007/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4931 -> Patchwork_10360 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10360 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10360, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/8/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10360:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_hangcheck:
fi-icl-u: NOTRUN -> INCOMPLETE
== Known issues ==
Here are the changes found in Patchwork_10360 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362)
==== Possible fixes ====
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-cfl-8109u: INCOMPLETE (fdo#108126, fdo#106070) -> PASS
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126
== Participating hosts (48 -> 43) ==
Additional (2): fi-icl-u fi-bdw-samus
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510
== Build changes ==
* Linux: CI_DRM_4931 -> Patchwork_10360
CI_DRM_4931: 826702bf60ae2b37841c051ed769b44af194fbb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4667: 596f48dcd59fd2f8c16671514f3e69d4a2891374 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10360: cb70f1ebba228ce6d6adfcd555a96345cf15fb86 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cb70f1ebba22 drm/i915: Adding YUV444 packed format support for skl+
f58818541bcb drm: Introduce new DRM_FORMAT_XYUV
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10360/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for Add XYUV format support (rev8)
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
` (3 preceding siblings ...)
2018-10-04 13:41 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-10-05 9:32 ` Patchwork
2018-10-05 12:42 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-09 13:34 ` [PATCH v11 0/2] Add XYUV format support Lisovskiy, Stanislav
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-05 9:32 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev8)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4933 -> Patchwork_10375 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/8/mbox/
== Known issues ==
Here are the changes found in Patchwork_10375 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773)
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
== Participating hosts (44 -> 40) ==
Additional (3): fi-glk-j4005 fi-bdw-samus fi-snb-2520m
Missing (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-byt-clapper fi-kbl-r
== Build changes ==
* Linux: CI_DRM_4933 -> Patchwork_10375
CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10375: f7cbdc7b7bcdab324edf99e6dc1f1fd837ccc287 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f7cbdc7b7bcd drm/i915: Adding YUV444 packed format support for skl+
6412f5392100 drm: Introduce new DRM_FORMAT_XYUV
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10375/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for Add XYUV format support (rev8)
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
` (4 preceding siblings ...)
2018-10-05 9:32 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-10-05 12:42 ` Patchwork
2018-10-09 13:34 ` [PATCH v11 0/2] Add XYUV format support Lisovskiy, Stanislav
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-05 12:42 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev8)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4933_full -> Patchwork_10375_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10375_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10375_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10375_full:
=== IGT changes ===
==== Warnings ====
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10375_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-glk: PASS -> INCOMPLETE (fdo#106886, fdo#103359, k.org#198133)
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: NOTRUN -> TIMEOUT (fdo#108039)
igt@gem_userptr_blits@readonly-unsync:
shard-skl: PASS -> INCOMPLETE (fdo#108074)
igt@kms_cursor_crc@cursor-128x42-random:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108)
shard-apl: PASS -> FAIL (fdo#103191, fdo#103232)
igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
shard-hsw: PASS -> FAIL (fdo#105767)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167) +3
igt@kms_plane@pixel-format-pipe-a-planes:
shard-skl: NOTRUN -> DMESG-WARN (fdo#106885)
{igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
shard-skl: NOTRUN -> FAIL (fdo#108146)
{igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +3
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_rotation_crc@exhaust-fences:
shard-skl: NOTRUN -> DMESG-WARN (fdo#105748)
igt@kms_sysfs_edid_timing:
shard-skl: NOTRUN -> FAIL (fdo#100047)
==== Possible fixes ====
igt@drv_suspend@fence-restore-untiled:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_plane@plane-position-covered-pipe-b-planes:
shard-apl: FAIL (fdo#103166) -> PASS
{igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb}:
shard-glk: FAIL (fdo#108145) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
igt@pm_rpm@pm-tiling:
shard-skl: INCOMPLETE (fdo#107807) -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105748 https://bugs.freedesktop.org/show_bug.cgi?id=105748
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4933 -> Patchwork_10375
CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10375: f7cbdc7b7bcdab324edf99e6dc1f1fd837ccc287 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10375/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 0/2] Add XYUV format support
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
` (5 preceding siblings ...)
2018-10-05 12:42 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-09 13:34 ` Lisovskiy, Stanislav
6 siblings, 0 replies; 9+ messages in thread
From: Lisovskiy, Stanislav @ 2018-10-09 13:34 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org
Cc: Alexandru-Cosmin.Gheorghe@arm.com, Syrjala, Ville,
Heikkila, Juha-pekka, Peres, Martin
On Thu, 2018-10-04 at 15:43 +0300, Stanislav Lisovskiy wrote:
> Introduced new XYUV scan-in format for framebuffer and
> added support for it to i915(SkyLake+).
>
> Stanislav Lisovskiy (2):
> drm: Introduce new DRM_FORMAT_XYUV
> drm/i915: Adding YUV444 packed format support for skl+
Ping. Now there are IGT and Intel DDX changes available, checked
with userspace, using GStreamer:
IGT changes:
https://patchwork.freedesktop.org/series/48789/
xf86-video-intel changes:
https://patchwork.freedesktop.org/series/50749/
>
> drivers/gpu/drm/drm_fourcc.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 1 +
> 5 files changed, 21 insertions(+), 1 deletion(-)
>
--
Best Regards,
Lisovskiy Stanislav
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+
2018-10-04 12:43 ` [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
@ 2018-10-10 19:48 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2018-10-10 19:48 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, Alexandru-Cosmin.Gheorghe, ville.syrjala, martin.peres,
juha-pekka.heikkila
On Thu, Oct 04, 2018 at 03:43:49PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic, to reuse code from other case
> labels.
>
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added scaling support for DRM_FORMAT_XYUV
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> v10: Added missing XYUV format to sprite planes for skl+.
>
> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Looks good to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Though one thing we probably want to do still is adjust
intel_plane_check_src_coordinates() to allow odd coordinates for
this format. I think we should be able to just replace those
hardcoded numbers in there with fb->format->[hv]sub and it should
just work (tm).
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 3 +++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09bc8e730ee1..ac24ac4b1d51 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6501,7 +6501,7 @@ enum {
> #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
> #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
> -#define PLANE_CTL_FORMAT_AYUV (8 << 24)
> +#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..9e65c47f3f4c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> };
>
> static const uint32_t skl_pri_planar_formats[] = {
> @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> DRM_FORMAT_NV12,
> };
>
> @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XYUV:
> + return DRM_FORMAT_XYUV8888;
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR2101010:
> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> + case DRM_FORMAT_XYUV8888:
> + return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> case DRM_FORMAT_YVYU:
> @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_XYUV8888:
> + if (INTEL_GEN(dev_priv) < 9) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format, &format_name));
> + goto err;
> + }
> + break;
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_YVYU:
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 9600ccfc5b76..dec7546446d5 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> };
>
> static uint32_t skl_planar_formats[] = {
> @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = {
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> DRM_FORMAT_NV12,
> + DRM_FORMAT_XYUV8888,
> };
>
> static const uint64_t skl_plane_format_modifiers_noccs[] = {
> @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-10-10 19:49 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-04 12:43 [PATCH v11 0/2] Add XYUV format support Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-10-04 12:43 ` [PATCH v11 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
2018-10-10 19:48 ` Ville Syrjälä
2018-10-04 13:21 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev8) Patchwork
2018-10-04 13:41 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-05 9:32 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-05 12:42 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-09 13:34 ` [PATCH v11 0/2] Add XYUV format support Lisovskiy, Stanislav
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