Re: [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote:
> 
> 
> Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed fallthrough logic for the format switch cases.
> >
> > v4: Yet again fixed fallthrough logic, to reuse code from other case
> >     labels.
> >
> > v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >
> > v6: Removed unneeded initializer for new XYUV format.
> >
> > v7: Added scaling support for DRM_FORMAT_XYUV
> >
> > v8: Edited commit message to be more clear about skl+, renamed
> >     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> >     doesn't support per-pixel alpha. Fixed minor code issues.
> >
> > v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >
> > v10: Added missing XYUV format to sprite planes for skl+.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> >  drivers/gpu/drm/i915/intel_sprite.c  |  3 +++
> >  3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 09bc8e730ee1..ac24ac4b1d51 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6501,7 +6501,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
> > -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> > +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
> It's the same format as AYUV, don't add a separate definition here for it.
> The only difference is we ignore the alpha channel.

I think he's just renaming the format that's already been added to be
more consistent with how we name our other PLANE_CTL_FORMAT_
definitions.  I.e., all the rgb types use "XRGB" in the name.

> >  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
> >  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b2bab57cd113..b11f71b306a3 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = {
> >  	DRM_FORMAT_YVYU,
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_XYUV,
> >  };
> >  
> >  static const uint32_t skl_pri_planar_formats[] = {
> > @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> >  	DRM_FORMAT_YVYU,
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_XYUV,
> >  	DRM_FORMAT_NV12,
> I would add AYUV as well, only difference is blending mode used by the alpha channel..

According to the bspec's "Display Features / Surface Formats" matrix,
per-pixel alpha isn't supported for this format (and the
PLANE_CTL/PLANE_COLOR_CTL descriptions seem to agree that alpha is only
supported for RGB formats), so I don't think we want to expose the alpha
version of this format in the userspace-visible format lists.


Matt

> >  };
> >  
> > @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> >  		return DRM_FORMAT_RGB565;
> >  	case PLANE_CTL_FORMAT_NV12:
> >  		return DRM_FORMAT_NV12;
> > +	case PLANE_CTL_FORMAT_XYUV:
> > +		return DRM_FORMAT_XYUV;
> Use PLANE_CTL_FORMAT_AYUV here.
> return alpha ? DRM_FORMAT_AYUV : DRM_FORMAT_XYUV8888.
> 
> 
> >  	default:
> >  	case PLANE_CTL_FORMAT_XRGB_8888:
> >  		if (rgb_order) {
> > @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> >  		return PLANE_CTL_FORMAT_XRGB_2101010;
> >  	case DRM_FORMAT_XBGR2101010:
> >  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> > +	case DRM_FORMAT_XYUV:
> > +		return PLANE_CTL_FORMAT_XYUV;
> >  	case DRM_FORMAT_YUYV:
> >  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> >  	case DRM_FORMAT_YVYU:
> > @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_XYUV:
> >  		break;
> >  	default:
> >  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> > @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_XYUV:
> >  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
> >  			return true;
> >  		/* fall through */
> > @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  			goto err;
> >  		}
> >  		break;
> > +	case DRM_FORMAT_XYUV:
> > +		if (INTEL_GEN(dev_priv) < 9) {
> > +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> > +				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> > +			goto err;
> > +		}
> > +		break;
> >  	case DRM_FORMAT_YUYV:
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_YVYU:
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 9600ccfc5b76..54f74a55e3fb 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = {
> >  	DRM_FORMAT_YVYU,
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_XYUV,
> >  };
> >  
> >  static uint32_t skl_planar_formats[] = {
> > @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = {
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> >  	DRM_FORMAT_NV12,
> > +	DRM_FORMAT_XYUV,
> >  };
> >  
> >  static const uint64_t skl_plane_format_modifiers_noccs[] = {
> > @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_XYUV:
> >  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
> >  			return true;
> >  		/* fall through */
> 
> 
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-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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