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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
Date: Mon, 29 Oct 2018 16:34:56 -0700	[thread overview]
Message-ID: <20181029233455.GD3566@ldmartin-desk.jf.intel.com> (raw)
In-Reply-To: <20181029232315.15539-1-anusha.srivatsa@intel.com>

On Mon, Oct 29, 2018 at 04:23:15PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
> 
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..dd74bc01c64e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
>  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
> +/* FIA Offsets */
> +#define FIA1_BASE			0x163000
> +#define PORT_TX_DFLEXDPMLE1_OFFSET	0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET	0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET	0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET	0x008A0
> +
>  /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
>  #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
>  #define   DFLEXDPMLE1_DPMLETC(n, x)	((x) << (4 * (n)))
>  
> @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>  
> -#define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
>  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
>  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
>  #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
>  #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
>  #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
>  
> -#define PORT_TX_DFLEXDPPMS				_MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
>  #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
>  
> -#define PORT_TX_DFLEXDPCSSS				_MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
>  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
>  
>  #endif /* _I915_REG_H_ */
> -- 
> 2.17.1
> 
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  reply	other threads:[~2018-10-29 23:34 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi [this message]
2018-10-30  0:34 ` ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2) Patchwork
2018-10-30 13:57 ` [PATCH] drm/i915/fia: FIA registers offset implementation Jani Nikula
2018-10-30 15:15   ` Lucas De Marchi
2018-10-31  9:28     ` Jani Nikula
2018-10-31 16:58       ` Srivatsa, Anusha
2018-10-31 17:23         ` Lucas De Marchi
2018-10-31 17:33           ` Srivatsa, Anusha
  -- strict thread matches above, loose matches on Subject: below --
2018-11-01 18:55 Anusha Srivatsa
2018-11-02 17:44 ` Rodrigo Vivi
2018-10-26  5:14 Anusha Srivatsa
2018-10-26 16:21 ` Lucas De Marchi

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