Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
Date: Fri, 2 Nov 2018 10:44:42 -0700	[thread overview]
Message-ID: <20181102174442.GE2233@intel.com> (raw)
In-Reply-To: <20181101185557.29585-1-anusha.srivatsa@intel.com>

On Thu, Nov 01, 2018 at 11:55:57AM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
> 
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
> 
> v3:
> - Remove register offset defines. (Jani)
> - Update comment. (Anusha)
> 
> v4: rebase. Remove comment.(Lucas)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

pushed to dinq. thanks for patch and review.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6c7df179da28..9744cb59acd3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,10 @@ enum i915_power_well_id {
>  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
> +#define FIA1_BASE			0x163000
> +
>  /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + 0x008C0)
>  #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)	(0xf << (4 * (tc_port)))
>  #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)	(1 << (4 * (tc_port)))
>  #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)	(3 << (4 * (tc_port)))
> @@ -11091,17 +11093,17 @@ enum skl_power_gate {
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>  
> -#define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + 0x008A0)
>  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
>  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
>  #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
>  #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
>  #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
>  
> -#define PORT_TX_DFLEXDPPMS				_MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + 0x00890)
>  #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
>  
> -#define PORT_TX_DFLEXDPCSSS				_MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + 0x00894)
>  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
>  
>  #endif /* _I915_REG_H_ */
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-11-02 17:44 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01 18:55 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-11-01 21:01 ` ✓ Fi.CI.BAT: success for drm/i915/fia: FIA registers offset implementation. (rev4) Patchwork
2018-11-02  2:40 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-02 17:44 ` Rodrigo Vivi [this message]
  -- strict thread matches above, loose matches on Subject: below --
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi
2018-10-30 13:57 ` Jani Nikula
2018-10-30 15:15   ` Lucas De Marchi
2018-10-31  9:28     ` Jani Nikula
2018-10-31 16:58       ` Srivatsa, Anusha
2018-10-31 17:23         ` Lucas De Marchi
2018-10-31 17:33           ` Srivatsa, Anusha
2018-10-26  5:14 Anusha Srivatsa
2018-10-26 16:21 ` Lucas De Marchi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181102174442.GE2233@intel.com \
    --to=rodrigo.vivi@intel.com \
    --cc=anusha.srivatsa@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox