* [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
@ 2018-11-30 21:33 Lucas De Marchi
2018-11-30 21:33 ` [CI 2/2] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Lucas De Marchi @ 2018-11-30 21:33 UTC (permalink / raw)
To: intel-gfx
From: Tomasz Lis <tomasz.lis@intel.com>
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. (Joonas)
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 86 +++++++++++++------------------
1 file changed, 36 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871a8c9a..8d08a7b7d534 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,71 +96,57 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+
+#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \
+ (LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \
+ LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \
+ LE_PFM(pfm) | LE_SCF(scf))
+
+#define MOCS_L3CC_VALUE(esc, scc, l3cc) \
+ (L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc))
+
+#define GEN9_MOCS_ENTRIES \
+ [I915_MOCS_UNCACHED] = { \
+ /* 0x00000009 */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC, \
+ 0, 0, 0, 0, 0, 0), \
+ /* 0x0010 */ \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [I915_MOCS_PTE] = { \
+ /* 0x00000038 */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC_ELLC, \
+ 3, 0, 0, 0, 0, 0), \
+ /* 0x0030 */ \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+ GEN9_MOCS_ENTRIES
[I915_MOCS_CACHED] = {
/* 0x0000003b */
- .control_value = LE_CACHEABILITY(LE_WB) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC_ELLC,
+ 3, 0, 0, 0, 0, 0),
/* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
},
};
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
- },
+ GEN9_MOCS_ENTRIES
[I915_MOCS_CACHED] = {
/* 0x00000039 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
+ .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC,
+ 3, 0, 0, 0, 0, 0),
/* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
},
};
+#undef MOCS_CONTROL_VALUE
+#undef MOCS_L3CC_VALUE
+
/**
* get_mocs_settings()
* @dev_priv: i915 device.
--
2.19.1.1.g56c4683e68
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* [CI 2/2] drm/i915/icl: Define MOCS table for Icelake
2018-11-30 21:33 [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
@ 2018-11-30 21:33 ` Lucas De Marchi
2018-11-30 21:59 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2018-11-30 21:33 UTC (permalink / raw)
To: intel-gfx
From: Tomasz Lis <tomasz.lis@intel.com>
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.
v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)
v4: Moved new entries below gen9 ones. Put common entries into
definition to be used in multiple arrays. (Lucas)
v5: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. Switched LE_CoS to upper case. (Joonas)
v6: Removed definitions of reserved entries. (Michal)
Increased limit of entries sent to the hardware on gen11+.
BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v4)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 222 ++++++++++++++++++++++++++----
1 file changed, 197 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 8d08a7b7d534..4eb05c696b90 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
#define LE_SCC(value) ((value) << 8)
#define LE_PFM(value) ((value) << 11)
#define LE_SCF(value) ((value) << 14)
+#define LE_COS(value) ((value) << 15)
+#define LE_SSE(value) ((value) << 17)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -52,6 +54,10 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
+#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+
+#define NUM_MOCS_ENTRIES(i915) \
+ (INTEL_GEN(i915) < 11 ? GEN9_NUM_MOCS_ENTRIES : GEN11_NUM_MOCS_ENTRIES)
/* (e)LLC caching options */
#define LE_PAGETABLE 0
@@ -80,21 +86,21 @@ struct drm_i915_mocs_table {
* LNCFCMOCS0 - LNCFCMOCS32 registers.
*
* These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * userspace is concerned and shouldn't be relied upon.
+ *
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
*
- * NOTE: These tables MUST start with being uncached and the length
- * MUST be less than 63 as the last two registers are reserved
- * by the hardware. These tables are part of the kernel ABI and
- * may only be updated incrementally by adding entries at the
- * end.
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ * interface for ICL+. For older platforms, they are part of kernel
+ * ABI. It is expected that existing entries will remain constant
+ * and the tables will only be updated by adding new entries.
*/
#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \
@@ -147,6 +153,167 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
#undef MOCS_CONTROL_VALUE
#undef MOCS_L3CC_VALUE
+#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf, cos, sse) \
+ (LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \
+ LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \
+ LE_PFM(pfm) | LE_SCF(scf) | LE_COS(cos) | LE_SSE(sse))
+
+#define MOCS_L3CC_VALUE(esc, scc, l3cc) \
+ (L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc))
+
+#define GEN11_MOCS_ENTRIES \
+ [0] = { \
+ /* Base - Uncached (Deprecated) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+ 0, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [1] = { \
+ /* Base - L3 + LeCC:PAT (Deprecated) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC, \
+ 0, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [2] = { \
+ /* Base - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [3] = { \
+ /* Base - Uncached */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+ 0, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [4] = { \
+ /* Base - L3 */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+ 0, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [5] = { \
+ /* Base - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [6] = { \
+ /* Age 0 - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 1, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [7] = { \
+ /* Age 0 - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 1, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [8] = { \
+ /* Age: Don't Chg. - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 2, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [9] = { \
+ /* Age: Don't Chg. - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 2, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [10] = { \
+ /* No AOM - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [11] = { \
+ /* No AOM - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [12] = { \
+ /* No AOM; Age 0 - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 1, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [13] = { \
+ /* No AOM; Age 0 - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 1, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [14] = { \
+ /* No AOM; Age:DC - LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 2, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [15] = { \
+ /* No AOM; Age:DC - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 2, 1, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [18] = { \
+ /* Self-Snoop - L3 + LLC */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 0, 0, 0, 0, 3), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [19] = { \
+ /* Skip Caching - L3 + LLC(12.5%) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 7, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [20] = { \
+ /* Skip Caching - L3 + LLC(25%) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 3, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [21] = { \
+ /* Skip Caching - L3 + LLC(50%) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 1, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [22] = { \
+ /* Skip Caching - L3 + LLC(75%) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 1, 3, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [23] = { \
+ /* Skip Caching - L3 + LLC(87.5%) */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 1, 7, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+ }, \
+ [62] = { \
+ /* HW Reserved - SW program but never use */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ }, \
+ [63] = { \
+ /* HW Reserved - SW program but never use */ \
+ .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+ 3, 0, 0, 0, 0, 0, 0, 0), \
+ .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+ },
+
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+ GEN11_MOCS_ENTRIES
+};
+
+#undef MOCS_CONTROL_VALUE
+#undef MOCS_L3CC_VALUE
+
/**
* get_mocs_settings()
* @dev_priv: i915 device.
@@ -164,8 +331,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
{
bool result = false;
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
- IS_ICELAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ result = true;
+ } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
@@ -228,7 +398,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
if (!get_mocs_settings(dev_priv, &table))
return;
- GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);
+ GEM_BUG_ON(table.size > NUM_MOCS_ENTRIES(dev_priv));
for (index = 0; index < table.size; index++)
I915_WRITE(mocs_register(engine->id, index),
@@ -242,7 +412,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
* Entry 0 in the table is uncached - so we are just writing
* that value to all the used entries.
*/
- for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
+ for (; index < NUM_MOCS_ENTRIES(dev_priv); index++)
I915_WRITE(mocs_register(engine->id, index),
table.table[0].control_value);
}
@@ -260,18 +430,19 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
static int emit_mocs_control_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table)
{
+ struct drm_i915_private *i915 = rq->i915;
enum intel_engine_id engine = rq->engine->id;
unsigned int index;
u32 *cs;
- if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+ if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915)))
return -ENODEV;
- cs = intel_ring_begin(rq, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
+ cs = intel_ring_begin(rq, 2 + 2 * NUM_MOCS_ENTRIES(i915));
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
+ *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915));
for (index = 0; index < table->size; index++) {
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
@@ -286,7 +457,7 @@ static int emit_mocs_control_table(struct i915_request *rq,
* Entry 0 in the table is uncached - so we are just writing
* that value to all the used entries.
*/
- for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
+ for (; index < NUM_MOCS_ENTRIES(i915); index++) {
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
*cs++ = table->table[0].control_value;
}
@@ -319,17 +490,18 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
static int emit_mocs_l3cc_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table)
{
+ struct drm_i915_private *i915 = rq->i915;
unsigned int i;
u32 *cs;
- if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+ if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915)))
return -ENODEV;
- cs = intel_ring_begin(rq, 2 + GEN9_NUM_MOCS_ENTRIES);
+ cs = intel_ring_begin(rq, 2 + NUM_MOCS_ENTRIES(i915));
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
+ *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915) / 2);
for (i = 0; i < table->size/2; i++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
@@ -348,7 +520,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
* this will be uncached. Leave the last pair uninitialised as
* they are reserved by the hardware.
*/
- for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
+ for (; i < NUM_MOCS_ENTRIES(i915) / 2; i++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
*cs++ = l3cc_combine(table, 0, 0);
}
@@ -395,7 +567,7 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
* this will be uncached. Leave the last pair as initialised as
* they are reserved by the hardware.
*/
- for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
+ for (; i < (NUM_MOCS_ENTRIES(dev_priv) / 2); i++)
I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
}
--
2.19.1.1.g56c4683e68
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 21:33 [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
2018-11-30 21:33 ` [CI 2/2] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
@ 2018-11-30 21:59 ` Patchwork
2018-11-30 21:59 ` [CI 1/2] " Chris Wilson
2018-12-01 17:15 ` ✓ Fi.CI.IGT: success for series starting with [CI,1/2] " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-11-30 21:59 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL : https://patchwork.freedesktop.org/series/53337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5236 -> Patchwork_10983
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53337/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_10983 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-bsw-kefka: PASS -> FAIL [fdo#108656]
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: PASS -> FAIL [fdo#104008]
* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-bsw-kefka: DMESG-FAIL [fdo#108656] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
Participating hosts (48 -> 43)
------------------------------
Additional (2): fi-icl-y fi-pnv-d510
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600
Build changes
-------------
* Linux: CI_DRM_5236 -> Patchwork_10983
CI_DRM_5236: f9cd6a3ffb4400071d46dd123347802c1422d9da @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10983: 9e03c0a762706f4e9d6e0c10c1c4e3f647ba7c13 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9e03c0a76270 drm/i915/icl: Define MOCS table for Icelake
454290da2817 drm/i915/skl: Rework MOCS tables to keep common part in a define
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10983/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 21:33 [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
2018-11-30 21:33 ` [CI 2/2] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
2018-11-30 21:59 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
@ 2018-11-30 21:59 ` Chris Wilson
2018-11-30 23:19 ` Lucas De Marchi
2018-12-01 17:15 ` ✓ Fi.CI.IGT: success for series starting with [CI,1/2] " Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Chris Wilson @ 2018-11-30 21:59 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Quoting Lucas De Marchi (2018-11-30 21:33:03)
> From: Tomasz Lis <tomasz.lis@intel.com>
>
> The MOCS tables are going to be very similar across platforms.
>
> To reduce the amount of copied code, this patch rips the common part and
> puts it into a definition valid for all gen9 platforms.
>
> v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> to MOCS_ENTRIES. (Joonas)
>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
Lucas, this needs your s-o-b if you are sending it for inclusion (to
state that you do have the legal authority to do so).
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 21:59 ` [CI 1/2] " Chris Wilson
@ 2018-11-30 23:19 ` Lucas De Marchi
2018-11-30 23:35 ` Chris Wilson
0 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2018-11-30 23:19 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Lucas De Marchi
On Fri, Nov 30, 2018 at 09:59:53PM +0000, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > From: Tomasz Lis <tomasz.lis@intel.com>
> >
> > The MOCS tables are going to be very similar across platforms.
> >
> > To reduce the amount of copied code, this patch rips the common part and
> > puts it into a definition valid for all gen9 platforms.
> >
> > v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> > to MOCS_ENTRIES. (Joonas)
> >
> > Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> > Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
>
> Lucas, this needs your s-o-b if you are sending it for inclusion (to
> state that you do have the legal authority to do so).
Did I misunderstand the meaning of the CI tag? These are exactly the
same commits as https://patchwork.freedesktop.org/series/51258/
I'm only sending again to get them to run properly on CI since patchwork
got confused with the in-reply-to used there.
And I'm not going to apply these myself, so adding the s-o-b didn't seem
appropriate.
Lucas De Marchi
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 23:19 ` Lucas De Marchi
@ 2018-11-30 23:35 ` Chris Wilson
2018-11-30 23:37 ` Chris Wilson
2018-11-30 23:47 ` Lucas De Marchi
0 siblings, 2 replies; 9+ messages in thread
From: Chris Wilson @ 2018-11-30 23:35 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi
Quoting Lucas De Marchi (2018-11-30 23:19:18)
> On Fri, Nov 30, 2018 at 09:59:53PM +0000, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > From: Tomasz Lis <tomasz.lis@intel.com>
> > >
> > > The MOCS tables are going to be very similar across platforms.
> > >
> > > To reduce the amount of copied code, this patch rips the common part and
> > > puts it into a definition valid for all gen9 platforms.
> > >
> > > v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> > > to MOCS_ENTRIES. (Joonas)
> > >
> > > Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> > > Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
> >
> > Lucas, this needs your s-o-b if you are sending it for inclusion (to
> > state that you do have the legal authority to do so).
>
> Did I misunderstand the meaning of the CI tag? These are exactly the
> same commits as https://patchwork.freedesktop.org/series/51258/
> I'm only sending again to get them to run properly on CI since patchwork
> got confused with the in-reply-to used there.
>
> And I'm not going to apply these myself, so adding the s-o-b didn't seem
> appropriate.
If you ask someone else to apply this series as is, it has passed
through your hands and you need to affirm that you do have authority to
be supplying these patches.
I may have misunderstood your intent (if the commits remained the same
as before, you could have just requeued the earlier series for testing)
as I thought your intent here was to get CI results before applying
these patches (be that yourself or by proxy).
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 23:35 ` Chris Wilson
@ 2018-11-30 23:37 ` Chris Wilson
2018-11-30 23:47 ` Lucas De Marchi
1 sibling, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2018-11-30 23:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi
Quoting Chris Wilson (2018-11-30 23:35:25)
> I may have misunderstood your intent (if the commits remained the same
> as before, you could have just requeued the earlier series for testing)
> as I thought your intent here was to get CI results before applying
> these patches (be that yourself or by proxy).
Or perhaps even more appropriate would have been to use intel-gfx-trybot@
if this was just for private retesting.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 23:35 ` Chris Wilson
2018-11-30 23:37 ` Chris Wilson
@ 2018-11-30 23:47 ` Lucas De Marchi
1 sibling, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2018-11-30 23:47 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Lucas De Marchi
On Fri, Nov 30, 2018 at 11:35:25PM +0000, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-11-30 23:19:18)
> > On Fri, Nov 30, 2018 at 09:59:53PM +0000, Chris Wilson wrote:
> > > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > > From: Tomasz Lis <tomasz.lis@intel.com>
> > > >
> > > > The MOCS tables are going to be very similar across platforms.
> > > >
> > > > To reduce the amount of copied code, this patch rips the common part and
> > > > puts it into a definition valid for all gen9 platforms.
> > > >
> > > > v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> > > > to MOCS_ENTRIES. (Joonas)
> > > >
> > > > Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> > > > Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
> > >
> > > Lucas, this needs your s-o-b if you are sending it for inclusion (to
> > > state that you do have the legal authority to do so).
> >
> > Did I misunderstand the meaning of the CI tag? These are exactly the
> > same commits as https://patchwork.freedesktop.org/series/51258/
> > I'm only sending again to get them to run properly on CI since patchwork
> > got confused with the in-reply-to used there.
> >
> > And I'm not going to apply these myself, so adding the s-o-b didn't seem
> > appropriate.
>
> If you ask someone else to apply this series as is, it has passed
> through your hands and you need to affirm that you do have authority to
> be supplying these patches.
>
> I may have misunderstood your intent (if the commits remained the same
> as before, you could have just requeued the earlier series for testing)
> as I thought your intent here was to get CI results before applying
> these patches (be that yourself or by proxy).
My intent was to requeue the patch in the way I know it works, and that
I thought was the normal way to do... patchwork got upset with the email
headers there and no amount of clicks on "retest" would work since it
doesn't know how to apply the patches.
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-30 21:33 [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
` (2 preceding siblings ...)
2018-11-30 21:59 ` [CI 1/2] " Chris Wilson
@ 2018-12-01 17:15 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-12-01 17:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL : https://patchwork.freedesktop.org/series/53337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5236_full -> Patchwork_10983_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_10983_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@forcewake:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- {shard-iclb}: PASS -> WARN [fdo#108336] +4
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@basic-flip-vs-wf_vblank:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +20
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-apl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +5
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-skl: PASS -> FAIL [fdo#105682] +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-skl: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-a-planes:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +14
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@primary-rotation-180:
- shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815]
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +17
* igt@perf@short-reads:
- shard-skl: PASS -> FAIL [fdo#103183]
* igt@pm_rpm@debugfs-forcewake-user:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@dpms-lpsp:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]
#### Possible fixes ####
* igt@gem_pwrite_pread@snooped-copy-performance:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_ccs@pipe-a-missing-ccs-buffer:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS +8
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +2
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled:
- {shard-iclb}: WARN [fdo#108336] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> PASS +6
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- {shard-iclb}: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@pm_rpm@cursor-dpms:
- {shard-iclb}: INCOMPLETE [fdo#108840] -> PASS
#### Warnings ####
* igt@i915_selftest@live_contexts:
- {shard-iclb}: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#107725]
* igt@kms_ccs@pipe-b-crc-primary-rotation-180:
- {shard-iclb}: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- {shard-iclb}: FAIL [fdo#103232] -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_cursor_crc@cursor-256x256-random:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232]
* igt@kms_hdmi_inject@inject-audio:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> FAIL [fdo#102370]
* igt@kms_plane@pixel-format-pipe-c-planes:
- {shard-iclb}: FAIL [fdo#103166] -> DMESG-WARN [fdo#107724] / [fdo#108336]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102370]: https://bugs.freedesktop.org/show_bug.cgi?id=102370
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103925]: https://bugs.freedesktop.org/show_bug.cgi?id=103925
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5236 -> Patchwork_10983
CI_DRM_5236: f9cd6a3ffb4400071d46dd123347802c1422d9da @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10983: 9e03c0a762706f4e9d6e0c10c1c4e3f647ba7c13 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10983/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-12-01 17:15 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-11-30 21:33 [CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
2018-11-30 21:33 ` [CI 2/2] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
2018-11-30 21:59 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
2018-11-30 21:59 ` [CI 1/2] " Chris Wilson
2018-11-30 23:19 ` Lucas De Marchi
2018-11-30 23:35 ` Chris Wilson
2018-11-30 23:37 ` Chris Wilson
2018-11-30 23:47 ` Lucas De Marchi
2018-12-01 17:15 ` ✓ Fi.CI.IGT: success for series starting with [CI,1/2] " Patchwork
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