[PATCH 1/6] drm/i915: Shrink ilk-bdw wm storage by using u16

[PATCH 1/6] drm/i915: Shrink ilk-bdw wm storage by using u16

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The maximum watermark value we can ever have on ilk-bdw is
11 bits. Thus we can safely store all of these values in
u16.

Also toss in a few s/uint16_t/u16/ etc. while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  16 ++---
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 101 +++++++++++++++----------------
 3 files changed, 58 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e70707e79386..9264fd1b8662 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1031,17 +1031,17 @@ enum intel_ddb_partitioning {
 
 struct intel_wm_level {
 	bool enable;
-	uint32_t pri_val;
-	uint32_t spr_val;
-	uint32_t cur_val;
-	uint32_t fbc_val;
+	u16 pri_val;
+	u16 spr_val;
+	u16 cur_val;
+	u16 fbc_val;
 };
 
 struct ilk_wm_values {
-	uint32_t wm_pipe[3];
-	uint32_t wm_lp[3];
-	uint32_t wm_lp_spr[3];
-	uint32_t wm_linetime[3];
+	u32 wm_pipe[3];
+	u32 wm_lp[3];
+	u32 wm_lp_spr[3];
+	u32 wm_linetime[3];
 	bool enable_fbc_wm;
 	enum intel_ddb_partitioning partitioning;
 };
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d08f08f607dd..09abc1035335 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -630,7 +630,7 @@ struct intel_crtc_scaler_state {
 
 struct intel_pipe_wm {
 	struct intel_wm_level wm[5];
-	uint32_t linetime;
+	u32 linetime;
 	bool fbc_wm_enabled;
 	bool pipe_enabled;
 	bool sprites_enabled;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6d074f2e69d3..f23ea4631f9b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1188,9 +1188,9 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
 	return dirty;
 }
 
-static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
-				   const struct intel_plane_state *pstate,
-				   uint32_t pri_val);
+static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
+			      const struct intel_plane_state *pstate,
+			      u16 pri_val);
 
 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state)
@@ -2436,7 +2436,7 @@ static unsigned int ilk_wm_method1(unsigned int pixel_rate,
 	ret = intel_wm_method1(pixel_rate, cpp, latency);
 	ret = DIV_ROUND_UP(ret, 64) + 2;
 
-	return ret;
+	return min_t(unsigned int, ret, USHRT_MAX);
 }
 
 /* latency must be in 0.1us units. */
@@ -2452,11 +2452,11 @@ static unsigned int ilk_wm_method2(unsigned int pixel_rate,
 			       width, cpp, latency);
 	ret = DIV_ROUND_UP(ret, 64) + 2;
 
-	return ret;
+	return min_t(unsigned int, ret, USHRT_MAX);
 }
 
-static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
-			   uint8_t cpp)
+static u16 ilk_wm_fbc(u16 pri_val, unsigned int horiz_pixels,
+		      unsigned int cpp)
 {
 	/*
 	 * Neither of these should be possible since this function shouldn't be
@@ -2473,26 +2473,26 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
 }
 
 struct ilk_wm_maximums {
-	uint16_t pri;
-	uint16_t spr;
-	uint16_t cur;
-	uint16_t fbc;
+	u16 pri;
+	u16 spr;
+	u16 cur;
+	u16 fbc;
 };
 
 /*
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
-				   const struct intel_plane_state *pstate,
-				   uint32_t mem_value,
-				   bool is_lp)
+static u16 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
+			      const struct intel_plane_state *pstate,
+			      unsigned int mem_value,
+			      bool is_lp)
 {
-	uint32_t method1, method2;
+	u16 method1, method2;
 	int cpp;
 
 	if (mem_value == 0)
-		return U32_MAX;
+		return U16_MAX;
 
 	if (!intel_wm_plane_visible(cstate, pstate))
 		return 0;
@@ -2516,15 +2516,15 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
-				   const struct intel_plane_state *pstate,
-				   uint32_t mem_value)
+static u16 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
+			      const struct intel_plane_state *pstate,
+			      unsigned int mem_value)
 {
-	uint32_t method1, method2;
+	u16 method1, method2;
 	int cpp;
 
 	if (mem_value == 0)
-		return U32_MAX;
+		return U16_MAX;
 
 	if (!intel_wm_plane_visible(cstate, pstate))
 		return 0;
@@ -2543,14 +2543,14 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
-				   const struct intel_plane_state *pstate,
-				   uint32_t mem_value)
+static u16 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
+			      const struct intel_plane_state *pstate,
+			      unsigned int mem_value)
 {
 	int cpp;
 
 	if (mem_value == 0)
-		return U32_MAX;
+		return U16_MAX;
 
 	if (!intel_wm_plane_visible(cstate, pstate))
 		return 0;
@@ -2563,9 +2563,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
 }
 
 /* Only for WM_LP. */
-static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
-				   const struct intel_plane_state *pstate,
-				   uint32_t pri_val)
+static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
+			      const struct intel_plane_state *pstate,
+			      u16 pri_val)
 {
 	int cpp;
 
@@ -2577,8 +2577,7 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
 	return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
 }
 
-static unsigned int
-ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
+static u16 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) >= 8)
 		return 3072;
@@ -2588,9 +2587,8 @@ ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
 		return 512;
 }
 
-static unsigned int
-ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
-		     int level, bool is_sprite)
+static u16 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
+				int level, bool is_sprite)
 {
 	if (INTEL_GEN(dev_priv) >= 8)
 		/* BDW primary/sprite plane watermarks */
@@ -2606,8 +2604,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
 		return level == 0 ? 63 : 255;
 }
 
-static unsigned int
-ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
+static u16 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 {
 	if (INTEL_GEN(dev_priv) >= 7)
 		return level == 0 ? 63 : 255;
@@ -2615,7 +2612,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 		return level == 0 ? 31 : 63;
 }
 
-static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
+static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) >= 8)
 		return 31;
@@ -2624,13 +2621,13 @@ static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
 }
 
 /* Calculate the maximum primary/sprite plane watermark */
-static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
-				     int level,
-				     const struct intel_wm_config *config,
-				     enum intel_ddb_partitioning ddb_partitioning,
-				     bool is_sprite)
+static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
+			    int level,
+			    const struct intel_wm_config *config,
+			    enum intel_ddb_partitioning ddb_partitioning,
+			    bool is_sprite)
 {
-	unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
+	u16 fifo_size = ilk_display_fifo_size(dev_priv);
 
 	/* if sprites aren't enabled, sprites get nothing */
 	if (is_sprite && !config->sprites_enabled)
@@ -2665,9 +2662,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
 }
 
 /* Calculate the maximum cursor plane watermark */
-static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
-				      int level,
-				      const struct intel_wm_config *config)
+static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
+			     int level,
+			     const struct intel_wm_config *config)
 {
 	/* HSW LP1+ watermarks w/ multiple pipes */
 	if (level > 0 && config->num_pipes_active > 1)
@@ -2731,9 +2728,9 @@ static bool ilk_validate_wm_level(int level,
 			DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
 				      level, result->cur_val, max->cur);
 
-		result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
-		result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
-		result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
+		result->pri_val = min(result->pri_val, max->pri);
+		result->spr_val = min(result->spr_val, max->spr);
+		result->cur_val = min(result->cur_val, max->cur);
 		result->enable = true;
 	}
 
@@ -2749,9 +2746,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
 				 const struct intel_plane_state *curstate,
 				 struct intel_wm_level *result)
 {
-	uint16_t pri_latency = dev_priv->wm.pri_latency[level];
-	uint16_t spr_latency = dev_priv->wm.spr_latency[level];
-	uint16_t cur_latency = dev_priv->wm.cur_latency[level];
+	u16 pri_latency = dev_priv->wm.pri_latency[level];
+	u16 spr_latency = dev_priv->wm.spr_latency[level];
+	u16 cur_latency = dev_priv->wm.cur_latency[level];
 
 	/* WM1+ latency values stored in 0.5us units */
 	if (level > 0) {
-- 
2.18.1

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[PATCH 2/6] drm/i915: Rename ilk watermark structs/enums

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename all the watermark related structs/enums specific to ilk-bdw
to have an ilk_ prefix rather than an intel_ prefix. Should make it
less confusing for everyone when it's clear where these things
get used.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 12 ++--
 drivers/gpu/drm/i915/intel_drv.h | 10 ++--
 drivers/gpu/drm/i915/intel_pm.c  | 96 ++++++++++++++++----------------
 3 files changed, 58 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9264fd1b8662..95231f5f813d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1024,12 +1024,12 @@ struct intel_vbt_data {
 	struct sdvo_device_mapping sdvo_mappings[2];
 };
 
-enum intel_ddb_partitioning {
-	INTEL_DDB_PART_1_2,
-	INTEL_DDB_PART_5_6, /* IVB+ */
+enum ilk_ddb_partitioning {
+	ILK_DDB_PART_1_2,
+	ILK_DDB_PART_5_6, /* IVB+ */
 };
 
-struct intel_wm_level {
+struct ilk_wm_level {
 	bool enable;
 	u16 pri_val;
 	u16 spr_val;
@@ -1043,7 +1043,7 @@ struct ilk_wm_values {
 	u32 wm_lp_spr[3];
 	u32 wm_linetime[3];
 	bool enable_fbc_wm;
-	enum intel_ddb_partitioning partitioning;
+	enum ilk_ddb_partitioning partitioning;
 };
 
 struct g4x_pipe_wm {
@@ -1195,7 +1195,7 @@ struct i915_virtual_gpu {
 };
 
 /* used in computing the new watermarks state */
-struct intel_wm_config {
+struct ilk_wm_config {
 	unsigned int num_pipes_active;
 	bool sprites_enabled;
 	bool sprites_scaled;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 09abc1035335..cc4d8d8382b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -628,8 +628,8 @@ struct intel_crtc_scaler_state {
 /* Flag to get scanline using frame time stamps */
 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 
-struct intel_pipe_wm {
-	struct intel_wm_level wm[5];
+struct ilk_pipe_wm {
+	struct ilk_wm_level wm[5];
 	u32 linetime;
 	bool fbc_wm_enabled;
 	bool pipe_enabled;
@@ -693,13 +693,13 @@ struct intel_crtc_wm_state {
 			 * switching away from and the new
 			 * configuration we're switching to.
 			 */
-			struct intel_pipe_wm intermediate;
+			struct ilk_pipe_wm intermediate;
 
 			/*
 			 * Optimal watermarks, programmed post-vblank
 			 * when this state is committed.
 			 */
-			struct intel_pipe_wm optimal;
+			struct ilk_pipe_wm optimal;
 		} ilk;
 
 		struct {
@@ -982,7 +982,7 @@ struct intel_crtc {
 	struct {
 		/* watermarks currently being used  */
 		union {
-			struct intel_pipe_wm ilk;
+			struct ilk_pipe_wm ilk;
 			struct vlv_wm_state vlv;
 			struct g4x_wm_state g4x;
 		} active;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f23ea4631f9b..6328f0f8aa88 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2485,8 +2485,7 @@ struct ilk_wm_maximums {
  */
 static u16 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
 			      const struct intel_plane_state *pstate,
-			      unsigned int mem_value,
-			      bool is_lp)
+			      unsigned int mem_value, bool is_lp)
 {
 	u16 method1, method2;
 	int cpp;
@@ -2623,8 +2622,8 @@ static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
 /* Calculate the maximum primary/sprite plane watermark */
 static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
 			    int level,
-			    const struct intel_wm_config *config,
-			    enum intel_ddb_partitioning ddb_partitioning,
+			    const struct ilk_wm_config *config,
+			    enum ilk_ddb_partitioning ddb_partitioning,
 			    bool is_sprite)
 {
 	u16 fifo_size = ilk_display_fifo_size(dev_priv);
@@ -2648,7 +2647,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
 
 	if (config->sprites_enabled) {
 		/* level 0 is always calculated with 1:1 split */
-		if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
+		if (level > 0 && ddb_partitioning == ILK_DDB_PART_5_6) {
 			if (is_sprite)
 				fifo_size *= 5;
 			fifo_size /= 6;
@@ -2664,7 +2663,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
 /* Calculate the maximum cursor plane watermark */
 static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
 			     int level,
-			     const struct intel_wm_config *config)
+			     const struct ilk_wm_config *config)
 {
 	/* HSW LP1+ watermarks w/ multiple pipes */
 	if (level > 0 && config->num_pipes_active > 1)
@@ -2676,8 +2675,8 @@ static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
 
 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
 				    int level,
-				    const struct intel_wm_config *config,
-				    enum intel_ddb_partitioning ddb_partitioning,
+				    const struct ilk_wm_config *config,
+				    enum ilk_ddb_partitioning ddb_partitioning,
 				    struct ilk_wm_maximums *max)
 {
 	max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
@@ -2698,7 +2697,7 @@ static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
 
 static bool ilk_validate_wm_level(int level,
 				  const struct ilk_wm_maximums *max,
-				  struct intel_wm_level *result)
+				  struct ilk_wm_level *result)
 {
 	bool ret;
 
@@ -2744,7 +2743,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
 				 const struct intel_plane_state *pristate,
 				 const struct intel_plane_state *sprstate,
 				 const struct intel_plane_state *curstate,
-				 struct intel_wm_level *result)
+				 struct ilk_wm_level *result)
 {
 	u16 pri_latency = dev_priv->wm.pri_latency[level];
 	u16 spr_latency = dev_priv->wm.spr_latency[level];
@@ -3068,10 +3067,10 @@ static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
 }
 
 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
-				 struct intel_pipe_wm *pipe_wm)
+				 struct ilk_pipe_wm *pipe_wm)
 {
 	/* LP0 watermark maximums depend on this pipe alone */
-	const struct intel_wm_config config = {
+	const struct ilk_wm_config config = {
 		.num_pipes_active = 1,
 		.sprites_enabled = pipe_wm->sprites_enabled,
 		.sprites_scaled = pipe_wm->sprites_scaled,
@@ -3079,7 +3078,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
 	struct ilk_wm_maximums max;
 
 	/* LP0 watermarks always use 1/2 DDB partitioning */
-	ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
+	ilk_compute_wm_maximums(dev_priv, 0, &config, ILK_DDB_PART_1_2, &max);
 
 	/* At least LP0 must be valid */
 	if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
@@ -3095,7 +3094,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
 {
 	struct drm_atomic_state *state = cstate->base.state;
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
-	struct intel_pipe_wm *pipe_wm;
+	struct ilk_pipe_wm *pipe_wm;
 	struct drm_device *dev = state->dev;
 	const struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_plane *plane;
@@ -3150,7 +3149,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
 	ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
 
 	for (level = 1; level <= usable_level; level++) {
-		struct intel_wm_level *wm = &pipe_wm->wm[level];
+		struct ilk_wm_level *wm = &pipe_wm->wm[level];
 
 		ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
 				     pristate, sprstate, curstate, wm);
@@ -3178,12 +3177,12 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
-	struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
+	struct ilk_pipe_wm *a = &newstate->wm.ilk.intermediate;
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(newstate->base.state);
 	const struct intel_crtc_state *oldstate =
 		intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
-	const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
+	const struct ilk_pipe_wm *b = &oldstate->wm.ilk.optimal;
 	int level, max_level = ilk_wm_max_level(dev_priv);
 
 	/*
@@ -3201,8 +3200,8 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
 	a->sprites_scaled |= b->sprites_scaled;
 
 	for (level = 0; level <= max_level; level++) {
-		struct intel_wm_level *a_wm = &a->wm[level];
-		const struct intel_wm_level *b_wm = &b->wm[level];
+		struct ilk_wm_level *a_wm = &a->wm[level];
+		const struct ilk_wm_level *b_wm = &b->wm[level];
 
 		a_wm->enable &= b_wm->enable;
 		a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
@@ -3235,15 +3234,15 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
  */
 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
 			       int level,
-			       struct intel_wm_level *ret_wm)
+			       struct ilk_wm_level *ret_wm)
 {
 	const struct intel_crtc *intel_crtc;
 
 	ret_wm->enable = true;
 
 	for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
-		const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
-		const struct intel_wm_level *wm = &active->wm[level];
+		const struct ilk_pipe_wm *active = &intel_crtc->wm.active.ilk;
+		const struct ilk_wm_level *wm = &active->wm[level];
 
 		if (!active->pipe_enabled)
 			continue;
@@ -3267,9 +3266,9 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
  * Merge all low power watermarks for all active pipes.
  */
 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
-			 const struct intel_wm_config *config,
+			 const struct ilk_wm_config *config,
 			 const struct ilk_wm_maximums *max,
-			 struct intel_pipe_wm *merged)
+			 struct ilk_pipe_wm *merged)
 {
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	int last_enabled_level = max_level;
@@ -3284,7 +3283,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
 
 	/* merge each WM1+ level */
 	for (level = 1; level <= max_level; level++) {
-		struct intel_wm_level *wm = &merged->wm[level];
+		struct ilk_wm_level *wm = &merged->wm[level];
 
 		ilk_merge_wm_level(dev_priv, level, wm);
 
@@ -3314,14 +3313,14 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
 	if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
 	    intel_fbc_is_active(dev_priv)) {
 		for (level = 2; level <= max_level; level++) {
-			struct intel_wm_level *wm = &merged->wm[level];
+			struct ilk_wm_level *wm = &merged->wm[level];
 
 			wm->enable = false;
 		}
 	}
 }
 
-static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
+static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm)
 {
 	/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
 	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
@@ -3338,8 +3337,8 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
 }
 
 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
-				   const struct intel_pipe_wm *merged,
-				   enum intel_ddb_partitioning partitioning,
+				   const struct ilk_pipe_wm *merged,
+				   enum ilk_ddb_partitioning partitioning,
 				   struct ilk_wm_values *results)
 {
 	struct intel_crtc *intel_crtc;
@@ -3350,7 +3349,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 
 	/* LP1+ register values */
 	for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
-		const struct intel_wm_level *r;
+		const struct ilk_wm_level *r;
 
 		level = ilk_wm_lp_to_level(wm_lp, merged);
 
@@ -3389,7 +3388,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 	/* LP0 register values */
 	for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
 		enum pipe pipe = intel_crtc->pipe;
-		const struct intel_wm_level *r =
+		const struct ilk_wm_level *r =
 			&intel_crtc->wm.active.ilk.wm[0];
 
 		if (WARN_ON(!r->enable))
@@ -3406,10 +3405,10 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 
 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
  * case both are at the same level. Prefer r1 in case they're the same. */
-static struct intel_pipe_wm *
+static struct ilk_pipe_wm *
 ilk_find_best_result(struct drm_i915_private *dev_priv,
-		     struct intel_pipe_wm *r1,
-		     struct intel_pipe_wm *r2)
+		     struct ilk_pipe_wm *r1,
+		     struct ilk_pipe_wm *r2)
 {
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	int level1 = 0, level2 = 0;
@@ -3557,14 +3556,14 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	if (dirty & WM_DIRTY_DDB) {
 		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 			val = I915_READ(WM_MISC);
-			if (results->partitioning == INTEL_DDB_PART_1_2)
+			if (results->partitioning == ILK_DDB_PART_1_2)
 				val &= ~WM_MISC_DATA_PARTITION_5_6;
 			else
 				val |= WM_MISC_DATA_PARTITION_5_6;
 			I915_WRITE(WM_MISC, val);
 		} else {
 			val = I915_READ(DISP_ARB_CTL2);
-			if (results->partitioning == INTEL_DDB_PART_1_2)
+			if (results->partitioning == ILK_DDB_PART_1_2)
 				val &= ~DISP_DATA_PARTITION_5_6;
 			else
 				val |= DISP_DATA_PARTITION_5_6;
@@ -5482,13 +5481,13 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 }
 
 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
-				  struct intel_wm_config *config)
+				  struct ilk_wm_config *config)
 {
 	struct intel_crtc *crtc;
 
 	/* Compute the currently _active_ config */
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
+		const struct ilk_pipe_wm *wm = &crtc->wm.active.ilk;
 
 		if (!wm->pipe_enabled)
 			continue;
@@ -5501,21 +5500,21 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
 
 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
+	struct ilk_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
 	struct ilk_wm_maximums max;
-	struct intel_wm_config config = {};
+	struct ilk_wm_config config = {};
 	struct ilk_wm_values results = {};
-	enum intel_ddb_partitioning partitioning;
+	enum ilk_ddb_partitioning partitioning;
 
 	ilk_compute_wm_config(dev_priv, &config);
 
-	ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
+	ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_1_2, &max);
 	ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
 
 	/* 5/6 split only in single pipe config on IVB+ */
 	if (INTEL_GEN(dev_priv) >= 7 &&
 	    config.num_pipes_active == 1 && config.sprites_enabled) {
-		ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
+		ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
 
 		best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
@@ -5524,7 +5523,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 	}
 
 	partitioning = (best_lp_wm == &lp_wm_1_2) ?
-		       INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
+		       ILK_DDB_PART_1_2 : ILK_DDB_PART_5_6;
 
 	ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
 
@@ -5628,11 +5627,10 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct ilk_wm_values *hw = &dev_priv->wm.hw;
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
-	struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
+	struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal;
 	enum pipe pipe = crtc->pipe;
 	static const i915_reg_t wm0_pipe_reg[] = {
 		[PIPE_A] = WM0_PIPEA_ILK,
@@ -6108,10 +6106,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
-			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
+			ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2;
 	else if (IS_IVYBRIDGE(dev_priv))
 		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
-			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
+			ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2;
 
 	hw->enable_fbc_wm =
 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
-- 
2.18.1

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[PATCH 3/6] drm/i915: Stash away the original SSKPD latency values

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On ILK-IVB we must write the latency value read from SSKPD into
the latency field in the WM_LP registers. While bspec was never
clear on how the punit (or whatever) interprets these values
empirical evidence has shown that these are treated as a cookie
rather than as a literal latency value. That is, if we write a
value that we didn't get from SSKPD (just off by one is sufficient)
the system no longer appears to enter the corresponding power
saving state.

This was made much more obvious on HSW/BDW since there we longer
write the latency value into the WM_LP registers, and rather we
write the desired watermark level number (well, 2x the level
number).

Since we allow the user to adjust the latency values via debugfs,
and since we have some quirks where we adjust the values automagically,
we must stash away the originals read from SSKPD for later use
in the WM_LP registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  6 ++++++
 drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++++----------
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95231f5f813d..c0204802d9cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1778,6 +1778,12 @@ struct drm_i915_private {
 		 * (which we don't fully trust).
 		 */
 		bool distrust_bios_wm;
+
+		/*
+		 * The values we must write to the LP watermark
+		 * registers' latency field on ILK-BDW.
+		 */
+		u16 ilk_wm_lp_latency[5];
 	} wm;
 
 	struct dram_info {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6328f0f8aa88..d5ad84be769d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3038,10 +3038,35 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
 	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
 }
 
+/* The value we need to program into the WM_LPx latency field */
+static u16 ilk_wm_lp_latency(struct drm_i915_private *dev_priv, int level)
+{
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		return 2 * level;
+	else
+		return dev_priv->wm.pri_latency[level];
+}
+
+static void ilk_setup_wm_lp_latency(struct drm_i915_private *dev_priv)
+{
+	int level, max_level = ilk_wm_max_level(dev_priv);
+
+	for (level = 1; level <= max_level; level++)
+		dev_priv->wm.ilk_wm_lp_latency[level] =
+			ilk_wm_lp_latency(dev_priv, level);
+}
+
 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
 {
 	intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
 
+	/*
+	 * On ILK-IVB the values written to the LP watermark register
+	 * latency field must match SSKPD 100%. So do this before any
+	 * adjustments are made to the latency values we got from SSKPD.
+	 */
+	ilk_setup_wm_lp_latency(dev_priv);
+
 	memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
 	       sizeof(dev_priv->wm.pri_latency));
 	memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
@@ -3326,16 +3351,6 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm)
 	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
 }
 
-/* The value we need to program into the WM_LPx latency field */
-static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
-				      int level)
-{
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-		return 2 * level;
-	else
-		return dev_priv->wm.pri_latency[level];
-}
-
 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 				   const struct ilk_pipe_wm *merged,
 				   enum ilk_ddb_partitioning partitioning,
@@ -3360,7 +3375,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 		 * disabled. Doing otherwise could cause underruns.
 		 */
 		results->wm_lp[wm_lp - 1] =
-			(ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
+			(dev_priv->wm.ilk_wm_lp_latency[level] << WM1_LP_LATENCY_SHIFT) |
 			(r->pri_val << WM1_LP_SR_SHIFT) |
 			r->cur_val;
 
-- 
2.18.1

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[PATCH 4/6] drm/i915: Remove gen6_check_mch_setup()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

snb_wm_latency_quirk() already boosts up the latency values
so the extra warning about the SSKPD value being insufficient
is now redundant. Drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 --
 drivers/gpu/drm/i915/intel_pm.c | 14 --------------
 2 files changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d60509ca7..9dce09ed47f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3538,8 +3538,6 @@ enum i915_power_well_id {
 
 /* snb MCH registers for priority tuning */
 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define   MCH_SSKPD_WM0_MASK		0x3f
-#define   MCH_SSKPD_WM0_VAL		0xc
 
 #define MCH_SECP_NRG_STTS		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ad84be769d..1a9ad431efbd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8612,16 +8612,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
-{
-	uint32_t tmp;
-
-	tmp = I915_READ(MCH_SSKPD);
-	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
-		DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
-			      tmp);
-}
-
 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -8712,8 +8702,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 	g4x_disable_trickle_feed(dev_priv);
 
 	cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
@@ -9081,8 +9069,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	if (!HAS_PCH_NOP(dev_priv))
 		cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.18.1

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[PATCH 5/6] drm/i915: Clean up SSKPD defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Give names to the HSW/BDW SSKPD mask/shift values, give
and _SNB suffix to the SNB/IVB mask/shift values, and
drop the bogus non-mirrored SSKPD register define.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++++++---------
 drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++----------
 2 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9dce09ed47f7..ea9a664980a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3536,8 +3536,24 @@ enum i915_power_well_id {
 #define   MAD_DIMM_A_SIZE_SHIFT		0
 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
 
-/* snb MCH registers for priority tuning */
 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
+#define SSKPD_WM0_SHIFT_SNB		0
+#define SSKPD_WM1_SHIFT_SNB		8
+#define SSKPD_WM2_SHIFT_SNB		16
+#define SSKPD_WM3_SHIFT_SNB		24
+#define SSKPD_WM_MASK_SNB		0x3f
+#define SSKPD_NEW_WM0_SHIFT_HSW		56
+#define SSKPD_NEW_WM0_MASK_HSW		0xff
+#define SSKPD_OLD_WM0_SHIFT_HSW		0
+#define SSKPD_OLD_WM0_MASK_HSW		0xf
+#define SSKPD_WM1_SHIFT_HSW		4
+#define SSKPD_WM1_MASK_HSW		0xff
+#define SSKPD_WM2_SHIFT_HSW		12
+#define SSKPD_WM2_MASK_HSW		0xff
+#define SSKPD_WM3_SHIFT_HSW		20
+#define SSKPD_WM3_MASK_HSW		0x1ff
+#define SSKPD_WM4_SHIFT_HSW		32
+#define SSKPD_WM4_MASK_HSW		0x1ff
 
 #define MCH_SECP_NRG_STTS		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
 
@@ -6016,14 +6032,6 @@ enum {
 #define  ILK_SRLT_MASK		0x3f
 
 
-/* the address where we get all kinds of latency value */
-#define SSKPD			_MMIO(0x5d10)
-#define SSKPD_WM_MASK		0x3f
-#define SSKPD_WM0_SHIFT		0
-#define SSKPD_WM1_SHIFT		8
-#define SSKPD_WM2_SHIFT		16
-#define SSKPD_WM3_SHIFT		24
-
 /*
  * The two pipe frame counter registers are not synchronized, so
  * reading a stable value is somewhat tricky. The following code
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a9ad431efbd..6ebde7bbac4e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2889,20 +2889,20 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		uint64_t sskpd = I915_READ64(MCH_SSKPD);
 
-		wm[0] = (sskpd >> 56) & 0xFF;
+		wm[0] = (sskpd >> SSKPD_NEW_WM0_SHIFT_HSW) & SSKPD_NEW_WM0_MASK_HSW;
 		if (wm[0] == 0)
-			wm[0] = sskpd & 0xF;
-		wm[1] = (sskpd >> 4) & 0xFF;
-		wm[2] = (sskpd >> 12) & 0xFF;
-		wm[3] = (sskpd >> 20) & 0x1FF;
-		wm[4] = (sskpd >> 32) & 0x1FF;
+			wm[0] = (sskpd >> SSKPD_OLD_WM0_SHIFT_HSW) & SSKPD_OLD_WM0_MASK_HSW;
+		wm[1] = (sskpd >> SSKPD_WM1_SHIFT_HSW) & SSKPD_WM1_MASK_HSW;
+		wm[2] = (sskpd >> SSKPD_WM2_SHIFT_HSW) & SSKPD_WM2_MASK_HSW;
+		wm[3] = (sskpd >> SSKPD_WM3_SHIFT_HSW) & SSKPD_WM3_MASK_HSW;
+		wm[4] = (sskpd >> SSKPD_WM4_SHIFT_HSW) & SSKPD_WM4_MASK_HSW;
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		uint32_t sskpd = I915_READ(MCH_SSKPD);
 
-		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
-		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
-		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
-		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
+		wm[0] = (sskpd >> SSKPD_WM0_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+		wm[1] = (sskpd >> SSKPD_WM1_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+		wm[2] = (sskpd >> SSKPD_WM2_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+		wm[3] = (sskpd >> SSKPD_WM3_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
 	} else if (INTEL_GEN(dev_priv) >= 5) {
 		uint32_t mltr = I915_READ(MLTR_ILK);
 
-- 
2.18.1

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[PATCH 6/6] drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remove the hand rolled array of WM0_PIPE register offsets
and use the standard _MMIO_PIPE3() instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  9 +++++----
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++---------
 2 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea9a664980a6..246e5e77e7c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5992,15 +5992,16 @@ enum {
 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
 
 /* define the Watermark register on Ironlake */
-#define WM0_PIPEA_ILK		_MMIO(0x45100)
+#define _WM0_PIPEA_ILK		0x45100
+#define _WM0_PIPEB_ILK		0x45104
+#define _WM0_PIPEC_IVB		0x45200
+#define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
+					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
 #define  WM0_PIPE_PLANE_SHIFT	16
 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
 #define  WM0_PIPE_SPRITE_SHIFT	8
 #define  WM0_PIPE_CURSOR_MASK	(0xff)
-
-#define WM0_PIPEB_ILK		_MMIO(0x45104)
-#define WM0_PIPEC_IVB		_MMIO(0x45200)
 #define WM1_LP_ILK		_MMIO(0x45108)
 #define  WM1_LP_SR_EN		(1 << 31)
 #define  WM1_LP_LATENCY_SHIFT	24
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ebde7bbac4e..46f8c8728847 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3555,11 +3555,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	_ilk_disable_lp_wm(dev_priv, dirty);
 
 	if (dirty & WM_DIRTY_PIPE(PIPE_A))
-		I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_B))
-		I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_C))
-		I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
 
 	if (dirty & WM_DIRTY_LINETIME(PIPE_A))
 		I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
@@ -5647,13 +5647,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
 	struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal;
 	enum pipe pipe = crtc->pipe;
-	static const i915_reg_t wm0_pipe_reg[] = {
-		[PIPE_A] = WM0_PIPEA_ILK,
-		[PIPE_B] = WM0_PIPEB_ILK,
-		[PIPE_C] = WM0_PIPEC_IVB,
-	};
 
-	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
+	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
 
-- 
2.18.1

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[PATCH v2 6/6] drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remove the hand rolled array of WM0_PIPE register offsets
and use the standard _MMIO_PIPE3() instead.

v2: Take care of gvt too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c |  6 +++---
 drivers/gpu/drm/i915/i915_reg.h     |  9 +++++----
 drivers/gpu/drm/i915/intel_pm.c     | 13 ++++---------
 3 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b5475c91e2ef..2edab387221d 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2120,9 +2120,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
 	MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
 
-	MMIO_D(WM0_PIPEA_ILK, D_ALL);
-	MMIO_D(WM0_PIPEB_ILK, D_ALL);
-	MMIO_D(WM0_PIPEC_IVB, D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
 	MMIO_D(WM1_LP_ILK, D_ALL);
 	MMIO_D(WM2_LP_ILK, D_ALL);
 	MMIO_D(WM3_LP_ILK, D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea9a664980a6..246e5e77e7c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5992,15 +5992,16 @@ enum {
 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
 
 /* define the Watermark register on Ironlake */
-#define WM0_PIPEA_ILK		_MMIO(0x45100)
+#define _WM0_PIPEA_ILK		0x45100
+#define _WM0_PIPEB_ILK		0x45104
+#define _WM0_PIPEC_IVB		0x45200
+#define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
+					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
 #define  WM0_PIPE_PLANE_SHIFT	16
 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
 #define  WM0_PIPE_SPRITE_SHIFT	8
 #define  WM0_PIPE_CURSOR_MASK	(0xff)
-
-#define WM0_PIPEB_ILK		_MMIO(0x45104)
-#define WM0_PIPEC_IVB		_MMIO(0x45200)
 #define WM1_LP_ILK		_MMIO(0x45108)
 #define  WM1_LP_SR_EN		(1 << 31)
 #define  WM1_LP_LATENCY_SHIFT	24
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ebde7bbac4e..46f8c8728847 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3555,11 +3555,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	_ilk_disable_lp_wm(dev_priv, dirty);
 
 	if (dirty & WM_DIRTY_PIPE(PIPE_A))
-		I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_B))
-		I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_C))
-		I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
 
 	if (dirty & WM_DIRTY_LINETIME(PIPE_A))
 		I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
@@ -5647,13 +5647,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
 	struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal;
 	enum pipe pipe = crtc->pipe;
-	static const i915_reg_t wm0_pipe_reg[] = {
-		[PIPE_A] = WM0_PIPEA_ILK,
-		[PIPE_B] = WM0_PIPEB_ILK,
-		[PIPE_C] = WM0_PIPEC_IVB,
-	};
 
-	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
+	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
 
-- 
2.18.1

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Re: [PATCH v2 6/6] drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers

[Lucas De Marchi]

On Wed, Dec 12, 2018 at 11:17:38PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Remove the hand rolled array of WM0_PIPE register offsets
> and use the standard _MMIO_PIPE3() instead.
> 
> v2: Take care of gvt too
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/gvt/handlers.c |  6 +++---
>  drivers/gpu/drm/i915/i915_reg.h     |  9 +++++----
>  drivers/gpu/drm/i915/intel_pm.c     | 13 ++++---------
>  3 files changed, 12 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index b5475c91e2ef..2edab387221d 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2120,9 +2120,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>  	MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>  
> -	MMIO_D(WM0_PIPEA_ILK, D_ALL);
> -	MMIO_D(WM0_PIPEB_ILK, D_ALL);
> -	MMIO_D(WM0_PIPEC_IVB, D_ALL);
> +	MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> +	MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> +	MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>  	MMIO_D(WM1_LP_ILK, D_ALL);
>  	MMIO_D(WM2_LP_ILK, D_ALL);
>  	MMIO_D(WM3_LP_ILK, D_ALL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ea9a664980a6..246e5e77e7c5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5992,15 +5992,16 @@ enum {
>  	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
>  
>  /* define the Watermark register on Ironlake */
> -#define WM0_PIPEA_ILK		_MMIO(0x45100)
> +#define _WM0_PIPEA_ILK		0x45100
> +#define _WM0_PIPEB_ILK		0x45104
> +#define _WM0_PIPEC_IVB		0x45200
> +#define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
> +					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
>  #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
>  #define  WM0_PIPE_PLANE_SHIFT	16
>  #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
>  #define  WM0_PIPE_SPRITE_SHIFT	8
>  #define  WM0_PIPE_CURSOR_MASK	(0xff)
> -
> -#define WM0_PIPEB_ILK		_MMIO(0x45104)
> -#define WM0_PIPEC_IVB		_MMIO(0x45200)
>  #define WM1_LP_ILK		_MMIO(0x45108)
>  #define  WM1_LP_SR_EN		(1 << 31)
>  #define  WM1_LP_LATENCY_SHIFT	24
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6ebde7bbac4e..46f8c8728847 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3555,11 +3555,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>  	_ilk_disable_lp_wm(dev_priv, dirty);
>  
>  	if (dirty & WM_DIRTY_PIPE(PIPE_A))
> -		I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
> +		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
>  	if (dirty & WM_DIRTY_PIPE(PIPE_B))
> -		I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
> +		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
>  	if (dirty & WM_DIRTY_PIPE(PIPE_C))
> -		I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
> +		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
>  
>  	if (dirty & WM_DIRTY_LINETIME(PIPE_A))
>  		I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
> @@ -5647,13 +5647,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
>  	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
>  	struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal;
>  	enum pipe pipe = crtc->pipe;
> -	static const i915_reg_t wm0_pipe_reg[] = {
> -		[PIPE_A] = WM0_PIPEA_ILK,
> -		[PIPE_B] = WM0_PIPEB_ILK,
> -		[PIPE_C] = WM0_PIPEC_IVB,
> -	};
>  
> -	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
> +	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
>  
> -- 
> 2.18.1
> 
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✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16
URL   : https://patchwork.freedesktop.org/series/53962/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gvt/handlers.o
drivers/gpu/drm/i915/gvt/handlers.c: In function ‘init_generic_mmio_info’:
drivers/gpu/drm/i915/gvt/handlers.c:2123:9: error: ‘WM0_PIPEA_ILK’ undeclared (first use in this function); did you mean ‘_WM0_PIPEA_ILK’?
  MMIO_D(WM0_PIPEA_ILK, D_ALL);
         ^
drivers/gpu/drm/i915/gvt/handlers.c:1767:48: note: in definition of macro ‘MMIO_F’
  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
                                                ^~~
drivers/gpu/drm/i915/gvt/handlers.c:2123:2: note: in expansion of macro ‘MMIO_D’
  MMIO_D(WM0_PIPEA_ILK, D_ALL);
  ^~~~~~
drivers/gpu/drm/i915/gvt/handlers.c:2123:9: note: each undeclared identifier is reported only once for each function it appears in
  MMIO_D(WM0_PIPEA_ILK, D_ALL);
         ^
drivers/gpu/drm/i915/gvt/handlers.c:1767:48: note: in definition of macro ‘MMIO_F’
  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
                                                ^~~
drivers/gpu/drm/i915/gvt/handlers.c:2123:2: note: in expansion of macro ‘MMIO_D’
  MMIO_D(WM0_PIPEA_ILK, D_ALL);
  ^~~~~~
drivers/gpu/drm/i915/gvt/handlers.c:2124:9: error: ‘WM0_PIPEB_ILK’ undeclared (first use in this function); did you mean ‘WM0_PIPEA_ILK’?
  MMIO_D(WM0_PIPEB_ILK, D_ALL);
         ^
drivers/gpu/drm/i915/gvt/handlers.c:1767:48: note: in definition of macro ‘MMIO_F’
  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
                                                ^~~
drivers/gpu/drm/i915/gvt/handlers.c:2124:2: note: in expansion of macro ‘MMIO_D’
  MMIO_D(WM0_PIPEB_ILK, D_ALL);
  ^~~~~~
drivers/gpu/drm/i915/gvt/handlers.c:2125:9: error: ‘WM0_PIPEC_IVB’ undeclared (first use in this function); did you mean ‘_WM0_PIPEC_IVB’?
  MMIO_D(WM0_PIPEC_IVB, D_ALL);
         ^
drivers/gpu/drm/i915/gvt/handlers.c:1767:48: note: in definition of macro ‘MMIO_F’
  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
                                                ^~~
drivers/gpu/drm/i915/gvt/handlers.c:2125:2: note: in expansion of macro ‘MMIO_D’
  MMIO_D(WM0_PIPEC_IVB, D_ALL);
  ^~~~~~
scripts/Makefile.build:291: recipe for target 'drivers/gpu/drm/i915/gvt/handlers.o' failed
make[4]: *** [drivers/gpu/drm/i915/gvt/handlers.o] Error 1
scripts/Makefile.build:516: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:516: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:516: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16 (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16 (rev2)
URL   : https://patchwork.freedesktop.org/series/53962/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Shrink ilk-bdw wm storage by using u16
+drivers/gpu/drm/i915/intel_pm.c:2439:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2455:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2735:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2735:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2736:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2736:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2731:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2731:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2732:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2732:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2733:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2733:35: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_pm.c:4852:30: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_pm.c:4852:30: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_pm.c:6615:24: warning: too many warnings
+drivers/gpu/drm/i915/intel_pm.c:4852:30: warning: too many warnings

Commit: drm/i915: Rename ilk watermark structs/enums
-O:drivers/gpu/drm/i915/intel_pm.c:3208:33: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:3208:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:3207:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:3207:33: warning: expression using sizeof(void)

Commit: drm/i915: Stash away the original SSKPD latency values
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3561:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void)

Commit: drm/i915: Remove gen6_check_mch_setup()
Okay!

Commit: drm/i915: Clean up SSKPD defines
Okay!

Commit: drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
Okay!

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✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16 (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Shrink ilk-bdw wm storage by using u16 (rev2)
URL   : https://patchwork.freedesktop.org/series/53962/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5308 -> Patchwork_11080
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11080 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11080, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53962/revisions/2/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11080:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       PASS -> SKIP +33

  
Known issues
------------

  Here are the changes found in Patchwork_11080 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@amdgpu/amd_prime@amd-to-i915:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#107341]

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-7500u:       PASS -> DMESG-WARN [fdo#105128] / [fdo#107139]
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-skl-guc:         PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         PASS -> FAIL [fdo#104008]

  * {igt@runner@aborted}:
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       DMESG-WARN [fdo#108965] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965


Participating hosts (48 -> 44)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 


Build changes
-------------

    * Linux: CI_DRM_5308 -> Patchwork_11080

  CI_DRM_5308: e7cbffbd8fd1b6d713128ceb891d7d6205390ee4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11080: f542917d1f7c20c1fee9535302982f1ff7038b13 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f542917d1f7c drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
a65c8a2538bb drm/i915: Clean up SSKPD defines
15479c03167b drm/i915: Remove gen6_check_mch_setup()
436a44ebac02 drm/i915: Stash away the original SSKPD latency values
633566de8c23 drm/i915: Rename ilk watermark structs/enums
4552b667487e drm/i915: Shrink ilk-bdw wm storage by using u16

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11080/
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