* [PATCH 1/2] drm/i915: Enable render context support for Ironlake (gen5)
2019-01-08 12:28 Logical (HW) contexts for gen4/gen5 Chris Wilson
@ 2019-01-08 12:28 ` Chris Wilson
2019-01-08 12:28 ` [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-01-08 12:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Ironlake does support being able to saving and reloading context specific
registers between contexts, providing isolation of the basic GPU state
(as programmable by userspace). This allows userspace to assume that the
GPU retains their state from one batch to the next, minimising the
amount of state it needs to reload, or manually save and restore.
v2: Fix off-by-one in reading CXT_SIZE, and add a comment that the
CXT_SIZE and context-layout do not match in bspec, but the difference is
irrelevant as we overallocate the full page anyway (Ville).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 236cd040f271..f89b8f199e3f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -219,6 +219,22 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ /*
+ * There is a discrepancy here between the size reported
+ * by the register and the size of the context layout
+ * in the docs. Both are described as authorative!
+ *
+ * The discrepancy is on the order of a few cachelines,
+ * but the total is under one page (4k), which is our
+ * minimum allocation anyway so it should all come
+ * out in the wash.
+ */
+ cxt_size = I915_READ(CXT_SIZE) + 1;
+ DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+ INTEL_GEN(dev_priv),
+ cxt_size * 64,
+ cxt_size - 1);
+ return round_up(cxt_size * 64, PAGE_SIZE);
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6e2661e86d18..81bbc83d0cfe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1625,11 +1625,14 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
/* These flags are for resource streamer on HSW+ */
flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
else
+ /* We need to save the extended state for powersaving modes */
flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
len = 4;
if (IS_GEN(i915, 7))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+ else if (IS_GEN(i915, 5))
+ len += 2;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
flags &= ~MI_FORCE_RESTORE;
@@ -1658,6 +1661,14 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+ } else if (IS_GEN(i915, 5)) {
+ /*
+ * This w/a is only listed for pre-production ilk a/b steppings,
+ * but is also mentioned for programming the powerctx. To be
+ * safe, just apply the workaround; we do not use SyncFlush so
+ * this should never take effect and so be a no-op!
+ */
+ *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
if (force_restore) {
@@ -1712,6 +1723,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ } else if (IS_GEN(i915, 5)) {
+ *cs++ = MI_SUSPEND_FLUSH;
}
intel_ring_advance(rq, cs);
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-08 12:28 Logical (HW) contexts for gen4/gen5 Chris Wilson
2019-01-08 12:28 ` [PATCH 1/2] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
@ 2019-01-08 12:28 ` Chris Wilson
2019-01-08 13:11 ` Ville Syrjälä
2019-01-09 1:02 ` Chris Wilson
2019-01-08 14:17 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) Patchwork
` (2 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Chris Wilson @ 2019-01-08 12:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimising the amount of state it needs to reload and manually save
across batches.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f89b8f199e3f..88109e0de051 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -219,6 +219,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ case 4:
/*
* There is a discrepancy here between the size reported
* by the register and the size of the context layout
@@ -235,7 +236,6 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
- case 4:
case 3:
case 2:
/* For the special day when i810 gets merged. */
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-08 12:28 ` [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
@ 2019-01-08 13:11 ` Ville Syrjälä
2019-01-09 1:02 ` Chris Wilson
1 sibling, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2019-01-08 13:11 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Kenneth Graunke
On Tue, Jan 08, 2019 at 12:28:18PM +0000, Chris Wilson wrote:
> Broadwater and the rest of gen4 do support being able to saving and
> reloading context specific registers between contexts, providing isolation
> of the basic GPU state (as programmable by userspace). This allows
> userspace to assume that the GPU retains their state from one batch to the
> next, minimising the amount of state it needs to reload and manually save
> across batches.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
Reading through the old mails on the subject this looks fine.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f89b8f199e3f..88109e0de051 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -219,6 +219,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
> return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
> PAGE_SIZE);
> case 5:
> + case 4:
> /*
> * There is a discrepancy here between the size reported
> * by the register and the size of the context layout
> @@ -235,7 +236,6 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
> cxt_size * 64,
> cxt_size - 1);
> return round_up(cxt_size * 64, PAGE_SIZE);
> - case 4:
> case 3:
> case 2:
> /* For the special day when i810 gets merged. */
> --
> 2.20.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-08 12:28 ` [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
2019-01-08 13:11 ` Ville Syrjälä
@ 2019-01-09 1:02 ` Chris Wilson
2019-01-09 9:02 ` Kenneth Graunke
1 sibling, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2019-01-09 1:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Quoting Chris Wilson (2019-01-08 12:28:18)
> Broadwater and the rest of gen4 do support being able to saving and
> reloading context specific registers between contexts, providing isolation
> of the basic GPU state (as programmable by userspace). This allows
> userspace to assume that the GPU retains their state from one batch to the
> next, minimising the amount of state it needs to reload and manually save
> across batches.
Well Crestline's render context contains a nasty booby trap.
[ 152.065764] hangcheck rcs0
[ 152.065770] hangcheck current seqno 1b89, last 1bc5, hangcheck 1b89 [5984 ms]
[ 152.065773] hangcheck Reset count: 0 (global 0)
[ 152.065774] hangcheck Requests:
[ 152.065779] hangcheck first 1b8a* [5:1b8a] @ 7376ms: rcs0
[ 152.065783] hangcheck last 1bc5+ [5:1bc5] @ 7328ms: rcs0
[ 152.065786] hangcheck active 1b8a* [5:1b8a] @ 7376ms: rcs0
[ 152.065789] hangcheck ring->start: 0x00004000
[ 152.065792] hangcheck ring->head: 0x00017dd0
[ 152.065794] hangcheck ring->tail: 0x00019fb0
[ 152.065795] hangcheck ring->emit: 0x00019fb0
[ 152.065797] hangcheck ring->space: 0x000050a0
[ 152.065801] hangcheck [head 17df0, postfix 17e60, tail 17e80, batch 0x00000000_00335000]:
[ 152.065809] hangcheck [0000] 02000002 7a004002 1fffe004 00000000 00000000 02000000 02000000 02000000
[ 152.065813] hangcheck [0020] 02000000 02000000 02000000 02000000 02000000 02000000 02000000 02000000
[ 152.065817] hangcheck [0040] 02000000 7a004002 1fffe004 00000000 00000000 02000002 00000000 0c000000
[ 152.065821] hangcheck [0060] 0032f10c 00000000 18800180 00335000 02000000 10800001 00000100 00001b8a
[ 152.065825] hangcheck [0080] 10800001 000000c0 00001b8a 01000000
[ 152.065829] hangcheck CCID: 0x0003210d
[ 152.065831] hangcheck RING_START: 0x00004000
[ 152.065834] hangcheck RING_HEAD: 0x00017e54
[ 152.065836] hangcheck RING_TAIL: 0x00019fb0
[ 152.065839] hangcheck RING_CTL: 0x0001f001
[ 152.065841] hangcheck RING_MODE: 0x00000040
[ 152.065844] hangcheck ACTHD: 0x00000000_00e17e54
[ 152.065847] hangcheck BBADDR: 0x00000000_002f81e0
[ 152.065849] hangcheck DMA_FADDR: 0x00000000_0001be50
[ 152.065851] hangcheck IPEIR: 0x00000000
[ 152.065853] hangcheck IPEHR: 0x60020100 # CONSTANT_BUFFER see 0x1d4
[ 152.065860] hangcheck E 1b8a* [5:1b8a] @ 7376ms: rcs0
[ 152.065864] hangcheck E 1b8b+ [5:1b8b] @ 7376ms: rcs0
[ 152.065867] hangcheck E 1b8c [5:1b8c] @ 7376ms: rcs0
[ 152.065870] hangcheck E 1b8d [5:1b8d] @ 7376ms: rcs0
[ 152.065873] hangcheck E 1b8e [5:1b8e] @ 7376ms: rcs0
[ 152.065877] hangcheck E 1b8f [5:1b8f] @ 7376ms: rcs0
[ 152.065880] hangcheck E 1b90 [5:1b90] @ 7372ms: rcs0
[ 152.065888] hangcheck ...skipping 52 executing requests...
[ 152.065891] hangcheck E 1bc5+ [5:1bc5] @ 7328ms: rcs0
[ 152.065893] hangcheck Queue priority: -2147483648
[ 152.065909] hangcheck HWSP:
[ 152.065913] hangcheck [0000] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.065915] hangcheck *
[ 152.065919] hangcheck [00c0] 00001b89 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.065923] hangcheck [00e0] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.065927] hangcheck [0100] 00001b89 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.065931] hangcheck [0120] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.065933] hangcheck *
[ 152.065945] hangcheck Context:
[ 152.065960] hangcheck [0000] 00000000 1100002b 00002120 ffff6800 00002124 ffff0180 000020e4 ffff0044
[ 152.065966] hangcheck [0020] 000020c0 ffff0000 00002310 00000010 00002314 00000000 00002318 00000008
[ 152.065970] hangcheck [0040] 0000231c 00000000 00002320 00000000 00002324 00000000 00002328 00000000
[ 152.065975] hangcheck [0060] 0000232c 00000000 00002330 00000000 00002334 00000000 00002338 00000000
[ 152.065980] hangcheck [0080] 0000233c 00000000 00002340 00000000 00002344 00000000 00002348 00000000
[ 152.065985] hangcheck [00a0] 0000234c 00000000 00002350 00000000 00002354 00000000 00000000 00000000
[ 152.065990] hangcheck [00c0] 61040000 60010000 00000014 60003f01 0320a020 10000042 60020000 00000001
[ 152.065994] hangcheck [00e0] 61010004 00000001 00316001 00000001 00000001 00000001 61020000 00000000
[ 152.065999] hangcheck [0100] 79000002 00000000 00000000 00000000 79050003 2c08007f 00035000 00000000
[ 152.066004] hangcheck [0120] 00000000 79040002 00000000 f792ec01 0f9fa8a6 79040002 40000000 f7bdfd51
[ 152.066009] hangcheck [0140] 2fdfb8e7 79040002 80000000 7392fc15 efdfacb6 79040002 c0000000 b5d2ec43
[ 152.066014] hangcheck [0160] 4fffabae 79010003 00000000 00000000 00000000 00000000 79090000 1ac4814a
[ 152.066019] hangcheck [0180] 79060000 00001603 79080001 8020d7bb 1eb70165 00000000 00000000 00000000
[ 152.066024] hangcheck [01a0] 78000005 00316160 00000000 00316181 00316140 003160c0 00316040 78010004
[ 152.066028] hangcheck [01c0] 00000000 00000000 00000000 00000000 00000080 60020100 0031e001 00000000
[ 152.066033] hangcheck [01e0] 40400006 00000000 00000000 00000000 00000000 00000000 00026000 00000000
[ 152.066038] hangcheck [0200] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066043] hangcheck [0220] 780a0001 00000000 00000000 78080043 0000002c 0032e000 00000000 00000000
[ 152.066047] hangcheck [0240] 08000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000
[ 152.066053] hangcheck [0260] 18000000 00000000 00000000 00000000 20000000 00000000 00000000 00000000
[ 152.066058] hangcheck [0280] 28000000 00000000 00000000 00000000 30000000 00000000 00000000 00000000
[ 152.066064] hangcheck [02a0] 38000000 00000000 00000000 00000000 40000000 00000000 00000000 00000000
[ 152.066069] hangcheck [02c0] 48000000 00000000 00000000 00000000 50000000 00000000 00000000 00000000
[ 152.066074] hangcheck [02e0] 58000000 00000000 00000000 00000000 60000000 00000000 00000000 00000000
[ 152.066079] hangcheck [0300] 68000000 00000000 00000000 00000000 70000000 00000000 00000000 00000000
[ 152.066084] hangcheck [0320] 78000000 00000000 00000000 00000000 80000000 00000000 00000000 00000000
[ 152.066089] hangcheck [0340] 78090023 04400000 11130000 00000000 00000000 00000000 00000000 00000000
[ 152.066094] hangcheck [0360] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066099] hangcheck *
[ 152.066110] hangcheck [03c0] 00000000 00000000 00000000 00000000 00000000 780b0001 00000000 00000000
[ 152.066118] hangcheck [03e0] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066123] hangcheck [0400] 7902000f ff90acdd ffa52f5d ff212a45 ff63edb4 ffa5aaed ffe9b9e5 ffd2ffcc
[ 152.066128] hangcheck [0420] ff65a3fc ff60a110 ff8928f4 ff51ae6d ffb052cd ff11c3f0 ff60bad6 ffc05bc9
[ 152.066133] hangcheck [0440] ffa87c10 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066138] hangcheck [0460] 7907001f 3c57ff12 30577d53 30136d15 3055fe5b 70577a56 3017dd16 3057fd12
[ 152.066142] hangcheck [0480] b15fd962 387379d4 2257fb10 3043fd30 a4773d50 3417de10 185b651c 3017f512
[ 152.066147] hangcheck [04a0] b819fd54 12576d8a 70c31900 a6666500 f870bd16 31769f3a bc7b5dc2 2497bb48
[ 152.066152] hangcheck [04c0] 30577d32 b0554d12 3c173d1a f0c73f90 7255fd93 307e7c92 381e5f88 24167552
[ 152.066156] hangcheck [04e0] 31532d1a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066161] hangcheck [0500] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 152.066169] hangcheck *
[ 152.066455] hangcheck Idle? no
[ 152.066456] hangcheck Signals:
[ 152.066459] hangcheck [5:1b8b] @ 7376ms
[ 152.066462] hangcheck [5:1bc5] @ 7328ms
The issue, I think, in that is the CONSTANT_BUFFER command does an
immediate load from the specified address,
Context:
[01d4] 60020100 CONSTANT_BUFFER
[01d8] 0031e001 address | length
and since this is a context image that address is not known to us and
indeed may not any more be valid (the target buffer having been evicted).
(But if it is a valid address but no longer populated, it should be
reading scratch not hanging?)
The crazy thing is
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/inte
index 18fa319..e2aab92 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1709,6 +1709,17 @@ static inline int mi_set_context(struct i915_request *rq,
int len;
u32 *cs;
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = 0;
+ *cs++ = i915_ggtt_offset(rq->hw_context->state) + 0x1d4;
+ *cs++ = 0x60020000; // replace active CONSTANT_BUFFER with inactive
+
+ intel_ring_advance(rq, cs);
+
works.
Eh?
-Chris
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-09 1:02 ` Chris Wilson
@ 2019-01-09 9:02 ` Kenneth Graunke
2019-01-09 11:00 ` Chris Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Kenneth Graunke @ 2019-01-09 9:02 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 9602 bytes --]
On Tuesday, January 8, 2019 5:02:59 PM PST Chris Wilson wrote:
> Quoting Chris Wilson (2019-01-08 12:28:18)
> > Broadwater and the rest of gen4 do support being able to saving and
> > reloading context specific registers between contexts, providing isolation
> > of the basic GPU state (as programmable by userspace). This allows
> > userspace to assume that the GPU retains their state from one batch to the
> > next, minimising the amount of state it needs to reload and manually save
> > across batches.
>
> Well Crestline's render context contains a nasty booby trap.
>
> [ 152.065764] hangcheck rcs0
> [ 152.065770] hangcheck current seqno 1b89, last 1bc5, hangcheck 1b89 [5984 ms]
> [ 152.065773] hangcheck Reset count: 0 (global 0)
> [ 152.065774] hangcheck Requests:
> [ 152.065779] hangcheck first 1b8a* [5:1b8a] @ 7376ms: rcs0
> [ 152.065783] hangcheck last 1bc5+ [5:1bc5] @ 7328ms: rcs0
> [ 152.065786] hangcheck active 1b8a* [5:1b8a] @ 7376ms: rcs0
> [ 152.065789] hangcheck ring->start: 0x00004000
> [ 152.065792] hangcheck ring->head: 0x00017dd0
> [ 152.065794] hangcheck ring->tail: 0x00019fb0
> [ 152.065795] hangcheck ring->emit: 0x00019fb0
> [ 152.065797] hangcheck ring->space: 0x000050a0
> [ 152.065801] hangcheck [head 17df0, postfix 17e60, tail 17e80, batch 0x00000000_00335000]:
> [ 152.065809] hangcheck [0000] 02000002 7a004002 1fffe004 00000000 00000000 02000000 02000000 02000000
> [ 152.065813] hangcheck [0020] 02000000 02000000 02000000 02000000 02000000 02000000 02000000 02000000
> [ 152.065817] hangcheck [0040] 02000000 7a004002 1fffe004 00000000 00000000 02000002 00000000 0c000000
> [ 152.065821] hangcheck [0060] 0032f10c 00000000 18800180 00335000 02000000 10800001 00000100 00001b8a
> [ 152.065825] hangcheck [0080] 10800001 000000c0 00001b8a 01000000
> [ 152.065829] hangcheck CCID: 0x0003210d
> [ 152.065831] hangcheck RING_START: 0x00004000
> [ 152.065834] hangcheck RING_HEAD: 0x00017e54
> [ 152.065836] hangcheck RING_TAIL: 0x00019fb0
> [ 152.065839] hangcheck RING_CTL: 0x0001f001
> [ 152.065841] hangcheck RING_MODE: 0x00000040
> [ 152.065844] hangcheck ACTHD: 0x00000000_00e17e54
> [ 152.065847] hangcheck BBADDR: 0x00000000_002f81e0
> [ 152.065849] hangcheck DMA_FADDR: 0x00000000_0001be50
> [ 152.065851] hangcheck IPEIR: 0x00000000
> [ 152.065853] hangcheck IPEHR: 0x60020100 # CONSTANT_BUFFER see 0x1d4
> [ 152.065860] hangcheck E 1b8a* [5:1b8a] @ 7376ms: rcs0
> [ 152.065864] hangcheck E 1b8b+ [5:1b8b] @ 7376ms: rcs0
> [ 152.065867] hangcheck E 1b8c [5:1b8c] @ 7376ms: rcs0
> [ 152.065870] hangcheck E 1b8d [5:1b8d] @ 7376ms: rcs0
> [ 152.065873] hangcheck E 1b8e [5:1b8e] @ 7376ms: rcs0
> [ 152.065877] hangcheck E 1b8f [5:1b8f] @ 7376ms: rcs0
> [ 152.065880] hangcheck E 1b90 [5:1b90] @ 7372ms: rcs0
> [ 152.065888] hangcheck ...skipping 52 executing requests...
> [ 152.065891] hangcheck E 1bc5+ [5:1bc5] @ 7328ms: rcs0
> [ 152.065893] hangcheck Queue priority: -2147483648
> [ 152.065909] hangcheck HWSP:
> [ 152.065913] hangcheck [0000] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.065915] hangcheck *
> [ 152.065919] hangcheck [00c0] 00001b89 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.065923] hangcheck [00e0] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.065927] hangcheck [0100] 00001b89 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.065931] hangcheck [0120] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.065933] hangcheck *
> [ 152.065945] hangcheck Context:
> [ 152.065960] hangcheck [0000] 00000000 1100002b 00002120 ffff6800 00002124 ffff0180 000020e4 ffff0044
> [ 152.065966] hangcheck [0020] 000020c0 ffff0000 00002310 00000010 00002314 00000000 00002318 00000008
> [ 152.065970] hangcheck [0040] 0000231c 00000000 00002320 00000000 00002324 00000000 00002328 00000000
> [ 152.065975] hangcheck [0060] 0000232c 00000000 00002330 00000000 00002334 00000000 00002338 00000000
> [ 152.065980] hangcheck [0080] 0000233c 00000000 00002340 00000000 00002344 00000000 00002348 00000000
> [ 152.065985] hangcheck [00a0] 0000234c 00000000 00002350 00000000 00002354 00000000 00000000 00000000
> [ 152.065990] hangcheck [00c0] 61040000 60010000 00000014 60003f01 0320a020 10000042 60020000 00000001
> [ 152.065994] hangcheck [00e0] 61010004 00000001 00316001 00000001 00000001 00000001 61020000 00000000
> [ 152.065999] hangcheck [0100] 79000002 00000000 00000000 00000000 79050003 2c08007f 00035000 00000000
> [ 152.066004] hangcheck [0120] 00000000 79040002 00000000 f792ec01 0f9fa8a6 79040002 40000000 f7bdfd51
> [ 152.066009] hangcheck [0140] 2fdfb8e7 79040002 80000000 7392fc15 efdfacb6 79040002 c0000000 b5d2ec43
> [ 152.066014] hangcheck [0160] 4fffabae 79010003 00000000 00000000 00000000 00000000 79090000 1ac4814a
> [ 152.066019] hangcheck [0180] 79060000 00001603 79080001 8020d7bb 1eb70165 00000000 00000000 00000000
> [ 152.066024] hangcheck [01a0] 78000005 00316160 00000000 00316181 00316140 003160c0 00316040 78010004
> [ 152.066028] hangcheck [01c0] 00000000 00000000 00000000 00000000 00000080 60020100 0031e001 00000000
> [ 152.066033] hangcheck [01e0] 40400006 00000000 00000000 00000000 00000000 00000000 00026000 00000000
> [ 152.066038] hangcheck [0200] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066043] hangcheck [0220] 780a0001 00000000 00000000 78080043 0000002c 0032e000 00000000 00000000
> [ 152.066047] hangcheck [0240] 08000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000
> [ 152.066053] hangcheck [0260] 18000000 00000000 00000000 00000000 20000000 00000000 00000000 00000000
> [ 152.066058] hangcheck [0280] 28000000 00000000 00000000 00000000 30000000 00000000 00000000 00000000
> [ 152.066064] hangcheck [02a0] 38000000 00000000 00000000 00000000 40000000 00000000 00000000 00000000
> [ 152.066069] hangcheck [02c0] 48000000 00000000 00000000 00000000 50000000 00000000 00000000 00000000
> [ 152.066074] hangcheck [02e0] 58000000 00000000 00000000 00000000 60000000 00000000 00000000 00000000
> [ 152.066079] hangcheck [0300] 68000000 00000000 00000000 00000000 70000000 00000000 00000000 00000000
> [ 152.066084] hangcheck [0320] 78000000 00000000 00000000 00000000 80000000 00000000 00000000 00000000
> [ 152.066089] hangcheck [0340] 78090023 04400000 11130000 00000000 00000000 00000000 00000000 00000000
> [ 152.066094] hangcheck [0360] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066099] hangcheck *
> [ 152.066110] hangcheck [03c0] 00000000 00000000 00000000 00000000 00000000 780b0001 00000000 00000000
> [ 152.066118] hangcheck [03e0] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066123] hangcheck [0400] 7902000f ff90acdd ffa52f5d ff212a45 ff63edb4 ffa5aaed ffe9b9e5 ffd2ffcc
> [ 152.066128] hangcheck [0420] ff65a3fc ff60a110 ff8928f4 ff51ae6d ffb052cd ff11c3f0 ff60bad6 ffc05bc9
> [ 152.066133] hangcheck [0440] ffa87c10 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066138] hangcheck [0460] 7907001f 3c57ff12 30577d53 30136d15 3055fe5b 70577a56 3017dd16 3057fd12
> [ 152.066142] hangcheck [0480] b15fd962 387379d4 2257fb10 3043fd30 a4773d50 3417de10 185b651c 3017f512
> [ 152.066147] hangcheck [04a0] b819fd54 12576d8a 70c31900 a6666500 f870bd16 31769f3a bc7b5dc2 2497bb48
> [ 152.066152] hangcheck [04c0] 30577d32 b0554d12 3c173d1a f0c73f90 7255fd93 307e7c92 381e5f88 24167552
> [ 152.066156] hangcheck [04e0] 31532d1a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066161] hangcheck [0500] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 152.066169] hangcheck *
> [ 152.066455] hangcheck Idle? no
> [ 152.066456] hangcheck Signals:
> [ 152.066459] hangcheck [5:1b8b] @ 7376ms
> [ 152.066462] hangcheck [5:1bc5] @ 7328ms
>
> The issue, I think, in that is the CONSTANT_BUFFER command does an
> immediate load from the specified address,
>
> Context:
> [01d4] 60020100 CONSTANT_BUFFER
> [01d8] 0031e001 address | length
>
> and since this is a context image that address is not known to us and
> indeed may not any more be valid (the target buffer having been evicted).
> (But if it is a valid address but no longer populated, it should be
> reading scratch not hanging?)
>
> The crazy thing is
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/inte
> index 18fa319..e2aab92 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1709,6 +1709,17 @@ static inline int mi_set_context(struct i915_request *rq,
> int len;
> u32 *cs;
>
> + cs = intel_ring_begin(rq, 4);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = 0;
> + *cs++ = i915_ggtt_offset(rq->hw_context->state) + 0x1d4;
> + *cs++ = 0x60020000; // replace active CONSTANT_BUFFER with inactive
> +
> + intel_ring_advance(rq, cs);
> +
>
> works.
>
> Eh?
> -Chris
Does it work if you emit 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP after
MI_SET_CONTEXT? That was the source of most CONSTANT_BUFFER hangs
I saw on Broadwater/Crestline. Notably, it's also a bug that was
fixed on Eaglelake/Cantiga...
https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_curbe.c#L317
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-09 9:02 ` Kenneth Graunke
@ 2019-01-09 11:00 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-01-09 11:00 UTC (permalink / raw)
To: Kenneth Graunke; +Cc: intel-gfx
Quoting Kenneth Graunke (2019-01-09 09:02:35)
> Does it work if you emit 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP after
> MI_SET_CONTEXT? That was the source of most CONSTANT_BUFFER hangs
> I saw on Broadwater/Crestline. Notably, it's also a bug that was
> fixed on Eaglelake/Cantiga...
Thanks for the suggestion, but alas no. Which makes sense if my
understanding is correct and it is the immediate execution of
CONSTANT_BUFFER inside the context image that is triggering the hang --
we don't even reach the next primitive.
I think have DevCL happy (at least as far as a few runs through piglit
can determine), now to double check DevCTG, DevILK. Alas I have no
gen4/gen5 desktop machines to hand.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5)
2019-01-08 12:28 Logical (HW) contexts for gen4/gen5 Chris Wilson
2019-01-08 12:28 ` [PATCH 1/2] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
2019-01-08 12:28 ` [PATCH 2/2] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
@ 2019-01-08 14:17 ` Patchwork
2019-01-08 14:18 ` Chris Wilson
2019-01-08 19:15 ` ✓ Fi.CI.IGT: " Patchwork
2019-01-09 1:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) (rev2) Patchwork
4 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2019-01-08 14:17 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5)
URL : https://patchwork.freedesktop.org/series/54876/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5378 -> Patchwork_11249
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11249 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11249, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/54876/revisions/1/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11249:
### IGT changes ###
#### Warnings ####
* igt@gem_ctx_create@basic:
- fi-elk-e7500: SKIP -> PASS +6
* igt@gem_ctx_exec@basic:
- fi-bwr-2160: SKIP -> PASS +6
* igt@gem_ctx_param@basic-default:
- fi-ilk-650: SKIP -> PASS +6
Known issues
------------
Here are the changes found in Patchwork_11249 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#107341]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> DMESG-WARN [fdo#108622]
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#108767]
* igt@kms_flip@basic-flip-vs-modeset:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s4-devices:
- fi-bsw-kefka: DMESG-WARN -> PASS
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: DMESG-FAIL [fdo#109228] -> PASS
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: DMESG-WARN [fdo#105998] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: INCOMPLETE [fdo#102657] -> PASS
* igt@kms_psr@sprite_plane_onoff:
- fi-skl-6700hq: FAIL [fdo#107383] -> PASS +3
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109228]: https://bugs.freedesktop.org/show_bug.cgi?id=109228
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
Participating hosts (48 -> 45)
------------------------------
Additional (1): fi-icl-y
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-glk-j4005
Build changes
-------------
* Linux: CI_DRM_5378 -> Patchwork_11249
CI_DRM_5378: 96b07848e43c024bd6a5a44970371c4866140a1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11249: 3363ea3660ad8b4167a53705bd690865eaadae21 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3363ea3660ad drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
f601c883f361 drm/i915: Enable render context support for Ironlake (gen5)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11249/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5)
2019-01-08 12:28 Logical (HW) contexts for gen4/gen5 Chris Wilson
` (2 preceding siblings ...)
2019-01-08 14:17 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) Patchwork
@ 2019-01-08 19:15 ` Patchwork
2019-01-09 1:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) (rev2) Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-01-08 19:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5)
URL : https://patchwork.freedesktop.org/series/54876/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5378_full -> Patchwork_11249_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_11249_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@gem_userptr_blits@readonly-unsync:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +4
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: PASS -> FAIL [fdo#108682]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-kbl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +5
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- shard-skl: PASS -> FAIL [fdo#107362]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-iclb: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-kbl: NOTRUN -> FAIL [fdo#103166]
* igt@pm_rpm@dpms-lpsp:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@legacy-planes:
- shard-iclb: PASS -> DMESG-WARN [fdo#108654]
* igt@pm_rpm@modeset-stress-extra-wait:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@pm_rps@min-max-config-loaded:
- shard-skl: PASS -> FAIL [fdo#102250]
#### Possible fixes ####
* igt@i915_selftest@live_workarounds:
- shard-iclb: DMESG-FAIL [fdo#108954] -> PASS
* igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing:
- shard-iclb: DMESG-WARN [fdo#107724] / [fdo#109225] -> PASS +1
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
- shard-glk: FAIL [fdo#103232] -> PASS +2
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
- shard-iclb: WARN [fdo#108336] -> PASS +4
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: DMESG-FAIL [fdo#107724] -> PASS +5
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: DMESG-FAIL [fdo#107720] / [fdo#107724] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +13
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-iclb: DMESG-FAIL [fdo#103166] / [fdo#107724] -> PASS
* igt@kms_plane@plane-panning-top-left-pipe-a-planes:
- shard-skl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@perf_pmu@event-wait-rcs0:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +23
* igt@pm_rpm@gem-execbuf:
- shard-iclb: INCOMPLETE [fdo#108840] -> PASS
* igt@pm_rpm@modeset-lpsp-stress:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@pm_rpm@modeset-stress-extra-wait:
- shard-iclb: DMESG-WARN [fdo#108654] -> PASS
* igt@pm_rps@min-max-config-loaded:
- shard-apl: FAIL [fdo#102250] -> PASS
#### Warnings ####
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#107725]
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: DMESG-FAIL [fdo#107724] -> FAIL [fdo#107882]
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107720]: https://bugs.freedesktop.org/show_bug.cgi?id=107720
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
[fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5378 -> Patchwork_11249
CI_DRM_5378: 96b07848e43c024bd6a5a44970371c4866140a1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11249: 3363ea3660ad8b4167a53705bd690865eaadae21 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11249/
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^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) (rev2)
2019-01-08 12:28 Logical (HW) contexts for gen4/gen5 Chris Wilson
` (3 preceding siblings ...)
2019-01-08 19:15 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-01-09 1:13 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-01-09 1:13 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable render context support for Ironlake (gen5) (rev2)
URL : https://patchwork.freedesktop.org/series/54876/
State : failure
== Summary ==
Applying: drm/i915: Enable render context support for Ironlake (gen5)
Applying: drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
error: corrupt patch at line 21
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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^ permalink raw reply [flat|nested] 11+ messages in thread