* [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
@ 2019-01-28 21:52 Chris Wilson
2019-01-28 21:52 ` [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Chris Wilson @ 2019-01-28 21:52 UTC (permalink / raw)
To: intel-gfx
Despite what I think the prm recommends, commit f2253bd9859b
("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
to be a huge mistake when enabling Ironlake contexts as the GPU would
hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
simple rendercopies with igt, do not suffer).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ee3719324e2d..db21606095d2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1968,12 +1968,12 @@ static int ring_request_alloc(struct i915_request *request)
*/
request->reserved_space += LEGACY_REQUEST_SIZE;
- ret = switch_context(request);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
if (ret)
return ret;
- /* Unconditionally invalidate GPU caches and TLBs. */
- ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
+ ret = switch_context(request);
if (ret)
return ret;
--
2.20.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5)
2019-01-28 21:52 [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Chris Wilson
@ 2019-01-28 21:52 ` Chris Wilson
2019-01-28 21:52 ` [PATCH 3/3] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-01-28 21:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Ironlake does support being able to saving and reloading context specific
registers between contexts, providing isolation of the basic GPU state
(as programmable by userspace). This allows userspace to assume that the
GPU retains their state from one batch to the next, minimising the
amount of state it needs to reload, or manually save and restore.
v2: Fix off-by-one in reading CXT_SIZE, and add a comment that the
CXT_SIZE and context-layout do not match in bspec, but the difference is
irrelevant as we overallocate the full page anyway (Ville).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index ead9c4371fe1..148c3e06a2eb 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -220,6 +220,22 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ /*
+ * There is a discrepancy here between the size reported
+ * by the register and the size of the context layout
+ * in the docs. Both are described as authorative!
+ *
+ * The discrepancy is on the order of a few cachelines,
+ * but the total is under one page (4k), which is our
+ * minimum allocation anyway so it should all come
+ * out in the wash.
+ */
+ cxt_size = I915_READ(CXT_SIZE) + 1;
+ DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+ INTEL_GEN(dev_priv),
+ cxt_size * 64,
+ cxt_size - 1);
+ return round_up(cxt_size * 64, PAGE_SIZE);
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index db21606095d2..19def67bf1c5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1726,11 +1726,14 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
/* These flags are for resource streamer on HSW+ */
flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
else
+ /* We need to save the extended state for powersaving modes */
flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
len = 4;
if (IS_GEN(i915, 7))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+ else if (IS_GEN(i915, 5))
+ len += 2;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
flags &= ~MI_FORCE_RESTORE;
@@ -1759,6 +1762,14 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+ } else if (IS_GEN(i915, 5)) {
+ /*
+ * This w/a is only listed for pre-production ilk a/b steppings,
+ * but is also mentioned for programming the powerctx. To be
+ * safe, just apply the workaround; we do not use SyncFlush so
+ * this should never take effect and so be a no-op!
+ */
+ *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
if (force_restore) {
@@ -1813,6 +1824,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ } else if (IS_GEN(i915, 5)) {
+ *cs++ = MI_SUSPEND_FLUSH;
}
intel_ring_advance(rq, cs);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/3] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
2019-01-28 21:52 [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Chris Wilson
2019-01-28 21:52 ` [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
@ 2019-01-28 21:52 ` Chris Wilson
2019-01-28 23:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Patchwork
2019-01-29 6:50 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-01-28 21:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimising the amount of state it needs to reload and manually save
across batches.
v2: CONSTANT_BUFFER woes
Running through piglit turned up an interesting issue, a GPU hang inside
the context load. The context image includes the CONSTANT_BUFFER command
that loads an address into a on-gpu buffer, and the context load was
executing that immediately. However, since it was reading from the GTT
there is no guarantee that the GTT retains the same configuration as
when the context was saved, resulting in stray reads and a GPU hang.
Having tried issuing a CONSTANT_BUFFER (to disable the command) from the
ring before saving the context to no avail, we resort to patching out
the instruction inside the context image before loading.
This does impose that gen4 always reissues CONSTANT_BUFFER commands on
each batch, but due to the use of a shared GTT that was and will remain
a requirement.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #v1
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_gpu_commands.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 17 +++++++++++++++++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 148c3e06a2eb..32bd850eec30 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -220,6 +220,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ case 4:
/*
* There is a discrepancy here between the size reported
* by the register and the size of the context layout
@@ -236,7 +237,6 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
- case 4:
case 3:
case 2:
/* For the special day when i810 gets merged. */
diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h b/drivers/gpu/drm/i915/intel_gpu_commands.h
index b96a31bc1080..a95bfd922c41 100644
--- a/drivers/gpu/drm/i915/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/intel_gpu_commands.h
@@ -265,6 +265,9 @@
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
+#define GFX_OP_CONSTANT_BUFFER \
+ (0x3 << 29 | 0x0 << 27 | 0x0 << 24 | 0x2 << 16)
+
#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
#define COLOR_BLT ((0x2<<29)|(0x40<<22))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 19def67bf1c5..c03d156d59d9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1734,6 +1734,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
else if (IS_GEN(i915, 5))
len += 2;
+ else if (IS_GEN(i915, 4))
+ len += 4;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
flags &= ~MI_FORCE_RESTORE;
@@ -1770,6 +1772,21 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
* this should never take effect and so be a no-op!
*/
*cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
+ } else if (IS_GEN(i915, 4)) {
+ /*
+ * Disable CONSTANT_BUFFER before it is loaded from the context
+ * image. For as it is loaded, it is executed and the stored
+ * address may no longer be valid, leading to a GPU hang.
+ *
+ * This imposes the requirement that userspace reload their
+ * CONSTANT_BUFFER on every batch, fortunately a requirement
+ * they are already accustomed to from before contexts were
+ * enabled.
+ */
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = 0;
+ *cs++ = i915_ggtt_offset(rq->hw_context->state) + 0x1d4;
+ *cs++ = GFX_OP_CONSTANT_BUFFER; /* inactive */
}
if (force_restore) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
2019-01-28 21:52 [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Chris Wilson
2019-01-28 21:52 ` [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
2019-01-28 21:52 ` [PATCH 3/3] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
@ 2019-01-28 23:18 ` Patchwork
2019-01-29 6:50 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-01-28 23:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
URL : https://patchwork.freedesktop.org/series/55874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5498 -> Patchwork_12063
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55874/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12063 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@gem_ctx_create@basic:
- fi-elk-e7500: {SKIP} [fdo#109271] -> PASS +5
* igt@gem_ctx_exec@basic:
- fi-bwr-2160: {SKIP} [fdo#109271] -> PASS +5
* igt@gem_ctx_param@basic-default:
- fi-ilk-650: {SKIP} [fdo#109271] -> PASS +5
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108756]: https://bugs.freedesktop.org/show_bug.cgi?id=108756
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (44 -> 41)
------------------------------
Missing (3): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_5498 -> Patchwork_12063
CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12063: 54975717b65be43e905bf56bc7d7f8329f9871ae @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
54975717b65b drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
e469a783cf96 drm/i915: Enable render context support for Ironlake (gen5)
43137479bd30 drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12063/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
2019-01-28 21:52 [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Chris Wilson
` (2 preceding siblings ...)
2019-01-28 23:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Patchwork
@ 2019-01-29 6:50 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-01-29 6:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
URL : https://patchwork.freedesktop.org/series/55874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5498_full -> Patchwork_12063_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_12063_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12063_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12063_full:
### IGT changes ###
#### Warnings ####
* igt@kms_vblank@crtc-id:
- shard-snb: {SKIP} [fdo#109271] -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12063_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-write-wc:
- shard-apl: PASS -> INCOMPLETE [fdo#103927] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-apl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_draw_crc@fill-fb:
- shard-glk: PASS -> FAIL [fdo#103184]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-glk: PASS -> FAIL [fdo#103166] +1
#### Possible fixes ####
* igt@gem_mmap_gtt@hang:
- shard-glk: FAIL [fdo#109469] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-kbl: FAIL [fdo#99912] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-kbl: INCOMPLETE [fdo#103665] / [fdo#106886] -> DMESG-WARN [fdo#109244]
- shard-snb: DMESG-WARN [fdo#109244] -> INCOMPLETE [fdo#105411] / [fdo#106886]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109469]: https://bugs.freedesktop.org/show_bug.cgi?id=109469
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 5)
------------------------------
Missing (1): shard-skl
Build changes
-------------
* Linux: CI_DRM_5498 -> Patchwork_12063
CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12063: 54975717b65be43e905bf56bc7d7f8329f9871ae @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12063/
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
@ 2019-04-19 11:17 Chris Wilson
2019-04-19 13:15 ` ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2019-04-19 11:17 UTC (permalink / raw)
To: intel-gfx
Despite what I think the prm recommends, commit f2253bd9859b
("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
to be a huge mistake when enabling Ironlake contexts as the GPU would
hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
simple rendercopies with igt, do not suffer).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3844581f622c..8feb2d9b7b60 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1882,12 +1882,12 @@ static int ring_request_alloc(struct i915_request *request)
*/
request->reserved_space += LEGACY_REQUEST_SIZE;
- ret = switch_context(request);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
if (ret)
return ret;
- /* Unconditionally invalidate GPU caches and TLBs. */
- ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
+ ret = switch_context(request);
if (ret)
return ret;
--
2.20.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Logical (HW) contexts for gen4/5
@ 2019-01-10 10:38 Chris Wilson
2019-01-10 15:56 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Patchwork
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2019-01-10 10:38 UTC (permalink / raw)
To: intel-gfx
I've completed a run through with piglit on Crestline, Cantiga and
Ironlake (missing desktops Broadwater, Eaglelake) and fixed up the fails
found. Currently piglit seems happy with both contexts disabled (so just
using the per-fd default context isolation) and contexts enabled in mesa.
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-04-19 13:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-01-28 21:52 [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Chris Wilson
2019-01-28 21:52 ` [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5) Chris Wilson
2019-01-28 21:52 ` [PATCH 3/3] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) Chris Wilson
2019-01-28 23:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Patchwork
2019-01-29 6:50 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-04-19 11:17 [PATCH 1/3] " Chris Wilson
2019-04-19 13:15 ` ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
2019-01-10 10:38 Logical (HW) contexts for gen4/5 Chris Wilson
2019-01-10 15:56 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context Patchwork
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