From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [RFC 2/6] drm/i915/dp: Add a config function for YCBCR420 outputs
Date: Thu, 31 Jan 2019 23:10:42 +0200 [thread overview]
Message-ID: <20190131211046.18603-3-gwan-gyeong.mun@intel.com> (raw)
In-Reply-To: <20190131211046.18603-1-gwan-gyeong.mun@intel.com>
This patch checks a support of YCBCR420 outputs on an encoder level.
If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
output, else it continues with RGB output mode.
It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
a pipe scaler as RGB to YCbCr 4:4:4.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ad7382d3be86..a61aff23c8b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2098,6 +2098,31 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
return 0;
}
+static bool
+intel_dp_ycbcr420_config(struct drm_connector *connector,
+ struct intel_crtc_state *config)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+
+ if (!connector->ycbcr_420_allowed) {
+ DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+ return false;
+ }
+
+ config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
+ /* YCBCR 420 output conversion needs a scaler */
+ if (skl_update_scaler_crtc(config)) {
+ DRM_DEBUG_KMS("Scaler allocation for output failed\n");
+ return false;
+ }
+
+ intel_pch_panel_fitting(intel_crtc, config,
+ DRM_MODE_SCALE_FULLSCREEN);
+
+ return true;
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2115,6 +2140,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int ret;
+ struct drm_connector *connector = conn_state->connector;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2123,6 +2149,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (lspcon->active)
lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
+ if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
+ if (!intel_dp_ycbcr420_config(connector, pipe_config)) {
+ DRM_ERROR("Can't support YCBCR420 output\n");
+ return false;
+ }
+ }
+
pipe_config->has_drrs = false;
if (IS_G4X(dev_priv) || port == PORT_A)
pipe_config->has_audio = false;
--
2.20.1
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next prev parent reply other threads:[~2019-01-31 21:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 21:10 [RFC 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs Gwan-gyeong Mun
2019-01-31 21:10 ` [RFC 1/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 Gwan-gyeong Mun
2019-02-08 15:24 ` Maarten Lankhorst
2019-02-21 18:48 ` Mun, Gwan-gyeong
2019-01-31 21:10 ` Gwan-gyeong Mun [this message]
2019-01-31 21:10 ` [RFC 3/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats Gwan-gyeong Mun
2019-01-31 21:10 ` [RFC 4/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format Gwan-gyeong Mun
2019-02-08 15:31 ` Maarten Lankhorst
2019-02-21 19:14 ` Mun, Gwan-gyeong
2019-01-31 21:10 ` [RFC 5/6] drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA Gwan-gyeong Mun
2019-01-31 21:10 ` [RFC 6/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs Gwan-gyeong Mun
2019-02-08 15:29 ` Maarten Lankhorst
2019-01-31 21:22 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Preliminary support " Patchwork
2019-02-18 9:44 ` Jani Nikula
2019-02-21 18:47 ` Mun, Gwan-gyeong
2019-01-31 21:25 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-01-31 21:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-02-01 2:53 ` ✓ Fi.CI.IGT: " Patchwork
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