[RFC v2 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[RFC v2 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Gwan-gyeong Mun]

On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need
to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP.
In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0
to MSA and VSC SDP.

This patches are RFC patches that add a VSC structure for handling
Pixel Encoding/Colorimetry Formats and program YCBCR 4:2:0 to MSA and VSC SDP.

This is currently not tested, but I wanted to get some inputs on this approach.
The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the
same approach used in YCbCr 4:2:0 on HDMI.

v2: Addressed Maarten's review comments, fixed minor coding and block comment
style. And reordered a first patch  ("drm/i915/dp: Support DP ports
YUV 4:2:0 output to GEN11") as a last patch.

Gwan-gyeong Mun (6):
  drm/i915/dp: Add a config function for YCBCR420 outputs
  drm: Add a VSC structure for handling Pixel Encoding/Colorimetry
    Formats
  drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry
    Format
  drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
  drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
  drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c |  16 +++-
 drivers/gpu/drm/i915/intel_dp.c  | 148 +++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 include/drm/drm_dp_helper.h      |  17 ++++
 5 files changed, 177 insertions(+), 7 deletions(-)

-- 
2.20.1

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[RFC v2 1/6] drm/i915/dp: Add a config function for YCBCR420 outputs

[Gwan-gyeong Mun]

This patch checks a support of YCBCR420 outputs on an encoder level.
If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
output, else it continues with RGB output mode.
It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
a pipe scaler as RGB to YCbCr 4:4:4.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e1a051c0fbfe..d0bf2102dfc2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2104,6 +2104,31 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static bool
+intel_dp_ycbcr420_config(struct drm_connector *connector,
+			 struct intel_crtc_state *config)
+{
+	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+
+	if (!connector->ycbcr_420_allowed) {
+		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+		return false;
+	}
+
+	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
+	/* YCBCR 420 output conversion needs a scaler */
+	if (skl_update_scaler_crtc(config)) {
+		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
+		return false;
+	}
+
+	intel_pch_panel_fitting(intel_crtc, config,
+				DRM_MODE_SCALE_FULLSCREEN);
+
+	return true;
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2121,6 +2146,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
 					   DP_DPCD_QUIRK_CONSTANT_N);
 	int ret;
+	struct drm_connector *connector = conn_state->connector;
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
@@ -2129,6 +2155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (lspcon->active)
 		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
 
+	if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
+		if (!intel_dp_ycbcr420_config(connector, pipe_config)) {
+			DRM_ERROR("Can't support YCBCR420 output\n");
+			return false;
+		}
+	}
+
 	pipe_config->has_drrs = false;
 	if (IS_G4X(dev_priv) || port == PORT_A)
 		pipe_config->has_audio = false;
-- 
2.20.1

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Re: [RFC v2 1/6] drm/i915/dp: Add a config function for YCBCR420 outputs

[Ville Syrjälä]

On Thu, Feb 21, 2019 at 09:27:26PM +0200, Gwan-gyeong Mun wrote:
> This patch checks a support of YCBCR420 outputs on an encoder level.
> If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
> output, else it continues with RGB output mode.
> It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
> a pipe scaler as RGB to YCbCr 4:4:4.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e1a051c0fbfe..d0bf2102dfc2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2104,6 +2104,31 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	return 0;
>  }
>  
> +static bool
> +intel_dp_ycbcr420_config(struct drm_connector *connector,
> +			 struct intel_crtc_state *config)

s/config/crtc_state/

Let's try to avoid spreading the naming mess any further.

> +{
> +	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);

s/intel_crtc/crtc/ for the same reason.

> +
> +	if (!connector->ycbcr_420_allowed) {
> +		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
> +		return false;
> +	}
> +
> +	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> +
> +	/* YCBCR 420 output conversion needs a scaler */
> +	if (skl_update_scaler_crtc(config)) {
> +		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
> +		return false;
> +	}
> +
> +	intel_pch_panel_fitting(intel_crtc, config,
> +				DRM_MODE_SCALE_FULLSCREEN);
> +
> +	return true;
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config,
> @@ -2121,6 +2146,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
>  					   DP_DPCD_QUIRK_CONSTANT_N);
>  	int ret;
> +	struct drm_connector *connector = conn_state->connector;
>  
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
>  		pipe_config->has_pch_encoder = true;
> @@ -2129,6 +2155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (lspcon->active)
>  		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
>  
> +	if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
> +		if (!intel_dp_ycbcr420_config(connector, pipe_config)) {
> +			DRM_ERROR("Can't support YCBCR420 output\n");
> +			return false;
> +		}
> +	}

This will clobber what lspcon_ycbcr420_config() did. So I suggest 

if (lspcon)
	lspcon_ycbcr420_config()
else
	intel_dp_ycbcr420_config()

ie. also move the 420_only check into the function itself.

> +
>  	pipe_config->has_drrs = false;
>  	if (IS_G4X(dev_priv) || port == PORT_A)
>  		pipe_config->has_audio = false;
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [RFC v2 1/6] drm/i915/dp: Add a config function for YCBCR420 outputs

[Mun, Gwan-gyeong]

On Thu, 2019-02-21 at 21:37 +0200, Ville Syrjälä wrote:
> On Thu, Feb 21, 2019 at 09:27:26PM +0200, Gwan-gyeong Mun wrote:
> > This patch checks a support of YCBCR420 outputs on an encoder
> > level.
> > If the input mode is YCBCR420-only mode then it prepares DP as an
> > YCBCR420
> > output, else it continues with RGB output mode.
> > It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to
> > using
> > a pipe scaler as RGB to YCbCr 4:4:4.
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 33
> > +++++++++++++++++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index e1a051c0fbfe..d0bf2102dfc2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2104,6 +2104,31 @@ intel_dp_compute_link_config(struct
> > intel_encoder *encoder,
> >  	return 0;
> >  }
> >  
> > +static bool
> > +intel_dp_ycbcr420_config(struct drm_connector *connector,
> > +			 struct intel_crtc_state *config)
> 
> s/config/crtc_state/
> 
> Let's try to avoid spreading the naming mess any further.
> 
I'll fix the naming mess.
> > +{
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(config-
> > >base.crtc);
> 
> s/intel_crtc/crtc/ for the same reason.
> 
I'll fix the naming.
> > +
> > +	if (!connector->ycbcr_420_allowed) {
> > +		DRM_ERROR("Platform doesn't support YCBCR420
> > output\n");
> > +		return false;
> > +	}
> > +
> > +	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> > +
> > +	/* YCBCR 420 output conversion needs a scaler */
> > +	if (skl_update_scaler_crtc(config)) {
> > +		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
> > +		return false;
> > +	}
> > +
> > +	intel_pch_panel_fitting(intel_crtc, config,
> > +				DRM_MODE_SCALE_FULLSCREEN);
> > +
> > +	return true;
> > +}
> > +
> >  int
> >  intel_dp_compute_config(struct intel_encoder *encoder,
> >  			struct intel_crtc_state *pipe_config,
> > @@ -2121,6 +2146,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >  	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> >  					   DP_DPCD_QUIRK_CONSTANT_N);
> >  	int ret;
> > +	struct drm_connector *connector = conn_state->connector;
> >  
> >  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port !=
> > PORT_A)
> >  		pipe_config->has_pch_encoder = true;
> > @@ -2129,6 +2155,13 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >  	if (lspcon->active)
> >  		lspcon_ycbcr420_config(&intel_connector->base,
> > pipe_config);
> >  
> > +	if (drm_mode_is_420_only(&connector->display_info,
> > adjusted_mode)) {
> > +		if (!intel_dp_ycbcr420_config(connector, pipe_config))
> > {
> > +			DRM_ERROR("Can't support YCBCR420 output\n");
> > +			return false;
> > +		}
> > +	}
> 
> This will clobber what lspcon_ycbcr420_config() did. So I suggest 
> 
> if (lspcon)
> 	lspcon_ycbcr420_config()
> else
> 	intel_dp_ycbcr420_config()
> 
> ie. also move the 420_only check into the function itself.
> 
I'll fix them as you guide.
> > +
> >  	pipe_config->has_drrs = false;
> >  	if (IS_G4X(dev_priv) || port == PORT_A)
> >  		pipe_config->has_audio = false;
> > -- 
> > 2.20.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[RFC v2 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Gwan-gyeong Mun]

SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 include/drm/drm_dp_helper.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 97ce790a5b5a..3793bea7b7fe 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
 	u8 DB8_31[24]; /* Reserved */
 } __packed;
 
+struct dp_vsc_sdp {
+	struct dp_sdp_header sdp_header;
+	u8 DB0; /* Stereo Interface */
+	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+	u8 DB8_15[8];  /* Reserved */
+	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
+	u8 DB17; /* Dynamic Range and Component Bit Depth */
+	u8 DB18; /* Content Type */
+	u8 DB19_31[13]; /* Reserved */
+} __packed;
+
 #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
-- 
2.20.1

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[RFC v2 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Gwan-gyeong Mun]

Function intel_pixel_encoding_setup_vsc handles vsc header and data block
setup for pixel encoding / colorimetry format.

Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
for pixel encoding / colorimetry format as per dp 1.4a spec,
section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120:VSC SDP Payload for DB16 through DB18.

v2:
  Minor style fix. [Maarten]
  Refer to commit ids instead of patchwork. [Maarten]

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c  | 73 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  2 +
 3 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ea83071a22c4..22ed203426de 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3400,6 +3400,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
+	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d0bf2102dfc2..a2f70b7a81de 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4408,6 +4408,79 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static void
+intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct dp_vsc_sdp vsc_sdp;
+
+	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)
+		return;
+
+	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
+	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
+	vsc_sdp.sdp_header.HB0 = 0;
+	vsc_sdp.sdp_header.HB1 = 0x7;
+
+	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication. A DP Source device is allowed
+	 * to indicate the pixel encoding/colorimetry format to the DP Sink
+	 * device with VSC SDP only when the DP Sink device supports it
+	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the register
+	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to 1)
+	 */
+	vsc_sdp.sdp_header.HB2 = 0x5;
+
+	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
+	 * Colorimetry Format indication (HB2 = 05h).
+	 */
+	vsc_sdp.sdp_header.HB3 = 0x13;
+	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
+	 * DB16[3:0] DP 1.4a spec, Table 2-120
+	 */
+
+	/* Commit id (25edf91501b8 "drm/i915: prepare csc unit for YCBCR420 output")
+	 * uses the BT.709 color space to perform RGB->YCBCR conversion.
+	 */
+	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
+	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
+
+	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
+	 * the following Component Bit Depth values are defined:
+	 * 001b = 8bpc.
+	 * 010b = 10bpc.
+	 * 011b = 12bpc.
+	 * 100b = 16bpc.
+	 */
+	vsc_sdp.DB17 = 0x1;
+
+	/*
+	 * Content Type (Bits 2:0)
+	 * 000b = Not defined.
+	 * 001b = Graphics.
+	 * 010b = Photo.
+	 * 011b = Video.
+	 * 100b = Game
+	 * All other values are RESERVED.
+	 * Note: See CTA-861-G for the definition and expected
+	 * processing by a stream sink for the above contect types.
+	 */
+	vsc_sdp.DB18 = 0;
+
+	intel_dig_port->write_infoframe(&intel_dig_port->base,
+			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
+}
+
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+		return;
+
+	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
+}
+
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 81ec73e4a083..a4411c352768 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1965,6 +1965,8 @@ u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
 				int mode_clock, int mode_hdisplay);
 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
 				int mode_hdisplay);
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
 
 /* intel_vdsc.c */
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
-- 
2.20.1

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[RFC v2 4/6] drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA

[Gwan-gyeong Mun]

When YCBCR 4:2:0 outputs is used for DP, we should program YCBCR 4:2:0 to
MSA and VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of Color
Encoding Format and Content Color Gamut] while sending YCBCR 420 signals
we should program MSA MISC1 fields which indicate VSC SDP for the Pixel
Encoding/Colorimetry Format.

v2: Block comment style fix.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 730bb1917fd1..92d082256641 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9472,6 +9472,7 @@ enum skl_power_gate {
 #define  TRANS_MSA_12_BPC		(3 << 5)
 #define  TRANS_MSA_16_BPC		(4 << 5)
 #define  TRANS_MSA_CEA_RANGE		(1 << 3)
+#define  TRANS_MSA_USE_VSC_SDP		(1 << 13)
 
 /* LCPLL Control */
 #define LCPLL_CTL			_MMIO(0x130040)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 22ed203426de..30825ae67903 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1732,6 +1732,14 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
+	/*
+	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+	 * of Color Encoding Format and Content Color Gamut] while sending
+	 * YCBCR 420 signals we should program MSA MISC1 fields which
+	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		temp |= TRANS_MSA_USE_VSC_SDP;
 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
-- 
2.20.1

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[RFC v2 5/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs

[Gwan-gyeong Mun]

pipe_bpp value was assumed RGB therefore it was multiplied with 3.
But YCbCr 4:2:0 requires multiplier value to 1.5 therefore it divides
pipe_bpp to 2.
 - RGB bpp = bpc x 3
 - YCbCr 4:2:0 bpp = bpc x 1.5

v2: Minor style fix.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  7 +++++-
 drivers/gpu/drm/i915/intel_dp.c  | 41 ++++++++++++++++++++++++++------
 2 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 30825ae67903..801fc9463306 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1696,6 +1696,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
+	int bpp;
 
 	if (!intel_crtc_has_dp_encoder(crtc_state))
 		return;
@@ -1707,7 +1708,11 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->limited_color_range)
 		temp |= TRANS_MSA_CEA_RANGE;
 
-	switch (crtc_state->pipe_bpp) {
+	bpp = crtc_state->pipe_bpp;
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		bpp *= 2;
+
+	switch (bpp) {
 	case 18:
 		temp |= TRANS_MSA_6_BPC;
 		break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2f70b7a81de..50a270a5f4bd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1767,12 +1767,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int bpp, bpc;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
 	bpp = pipe_config->pipe_bpp;
 	bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
 
 	if (bpc > 0)
-		bpp = min(bpp, 3*bpc);
+		bpp = min(bpp, 3 * bpc / bpp_divider);
 
 	if (intel_dp_is_edp(intel_dp)) {
 		/* Get bpp from vbt only for panels that dont have bpp in edid */
@@ -1793,12 +1794,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *pipe_config,
 				  struct link_config_limits *limits)
 {
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+
 	/* For DP Compliance we override the computed bpp for the pipe */
 	if (intel_dp->compliance.test_data.bpc != 0) {
-		int bpp = 3 * intel_dp->compliance.test_data.bpc;
+		int bpp = 3 * intel_dp->compliance.test_data.bpc / bpp_divider;
 
 		limits->min_bpp = limits->max_bpp = bpp;
-		pipe_config->dither_force_disable = bpp == 6 * 3;
+		pipe_config->dither_force_disable = bpp == 6 * 3 / bpp_divider;
 
 		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
 	}
@@ -1832,8 +1835,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int bpp, clock, lane_count;
 	int mode_rate, link_clock, link_avail;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
-	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 
@@ -1868,8 +1872,9 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int bpp, clock, lane_count;
 	int mode_rate, link_clock, link_avail;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
-	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 
@@ -2015,6 +2020,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	struct link_config_limits limits;
 	int common_len;
 	int ret;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
 						    intel_dp->max_link_rate);
@@ -2028,7 +2034,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_lane_count = 1;
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = 6 * 3;
+	limits.min_bpp = 6 * 3 / bpp_divider;
 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 
 	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
@@ -2116,6 +2122,11 @@ intel_dp_ycbcr420_config(struct drm_connector *connector,
 	}
 
 	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+	/* pipe_bpp value was assumed RGB therefore it was multiplied
+	 * with 3. But YCbCr 4:2:0 requires multiplier value to 1.5
+	 * therefore it divides pipe_bpp to 2.
+	 */
+	config->pipe_bpp /= 2;
 
 	/* YCBCR 420 output conversion needs a scaler */
 	if (skl_update_scaler_crtc(config)) {
@@ -4453,7 +4464,23 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 	 * 011b = 12bpc.
 	 * 100b = 16bpc.
 	 */
-	vsc_sdp.DB17 = 0x1;
+	switch (crtc_state->pipe_bpp) {
+	case 12: /* 8bpc */
+		vsc_sdp.DB17 = 0x1;
+		break;
+	case 15: /* 10bpc */
+		vsc_sdp.DB17 = 0x2;
+		break;
+	case 18: /* 12bpc */
+		vsc_sdp.DB17 = 0x3;
+		break;
+	case 24: /* 16bpc */
+		vsc_sdp.DB17 = 0x4;
+		break;
+	default:
+		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
+		break;
+	}
 
 	/*
 	 * Content Type (Bits 2:0)
-- 
2.20.1

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Re: [RFC v2 5/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs

[Ville Syrjälä]

On Thu, Feb 21, 2019 at 09:27:30PM +0200, Gwan-gyeong Mun wrote:
> pipe_bpp value was assumed RGB therefore it was multiplied with 3.
> But YCbCr 4:2:0 requires multiplier value to 1.5 therefore it divides
> pipe_bpp to 2.
>  - RGB bpp = bpc x 3
>  - YCbCr 4:2:0 bpp = bpc x 1.5
> 
> v2: Minor style fix.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  7 +++++-
>  drivers/gpu/drm/i915/intel_dp.c  | 41 ++++++++++++++++++++++++++------
>  2 files changed, 40 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 30825ae67903..801fc9463306 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1696,6 +1696,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> +	int bpp;
>  
>  	if (!intel_crtc_has_dp_encoder(crtc_state))
>  		return;
> @@ -1707,7 +1708,11 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->limited_color_range)
>  		temp |= TRANS_MSA_CEA_RANGE;
>  
> -	switch (crtc_state->pipe_bpp) {
> +	bpp = crtc_state->pipe_bpp;
> +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		bpp *= 2;
> +
> +	switch (bpp) {
>  	case 18:
>  		temp |= TRANS_MSA_6_BPC;
>  		break;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a2f70b7a81de..50a270a5f4bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1767,12 +1767,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	int bpp, bpc;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
>  	bpp = pipe_config->pipe_bpp;
>  	bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
>  
>  	if (bpc > 0)
> -		bpp = min(bpp, 3*bpc);
> +		bpp = min(bpp, 3 * bpc / bpp_divider);
>  
>  	if (intel_dp_is_edp(intel_dp)) {
>  		/* Get bpp from vbt only for panels that dont have bpp in edid */
> @@ -1793,12 +1794,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *pipe_config,
>  				  struct link_config_limits *limits)
>  {
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
> +
>  	/* For DP Compliance we override the computed bpp for the pipe */
>  	if (intel_dp->compliance.test_data.bpc != 0) {
> -		int bpp = 3 * intel_dp->compliance.test_data.bpc;
> +		int bpp = 3 * intel_dp->compliance.test_data.bpc / bpp_divider;
>  
>  		limits->min_bpp = limits->max_bpp = bpp;
> -		pipe_config->dither_force_disable = bpp == 6 * 3;
> +		pipe_config->dither_force_disable = bpp == 6 * 3 / bpp_divider;
>  
>  		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
>  	}
> @@ -1832,8 +1835,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int bpp, clock, lane_count;
>  	int mode_rate, link_clock, link_avail;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
> -	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> +	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   bpp);
>  
> @@ -1868,8 +1872,9 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
>  	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int bpp, clock, lane_count;
>  	int mode_rate, link_clock, link_avail;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
> -	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> +	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   bpp);
>  
> @@ -2015,6 +2020,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	struct link_config_limits limits;
>  	int common_len;
>  	int ret;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
>  	common_len = intel_dp_common_len_rate_limit(intel_dp,
>  						    intel_dp->max_link_rate);
> @@ -2028,7 +2034,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = 6 * 3;
> +	limits.min_bpp = 6 * 3 / bpp_divider;
>  	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>  
>  	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
> @@ -2116,6 +2122,11 @@ intel_dp_ycbcr420_config(struct drm_connector *connector,
>  	}
>  
>  	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> +	/* pipe_bpp value was assumed RGB therefore it was multiplied
> +	 * with 3. But YCbCr 4:2:0 requires multiplier value to 1.5
> +	 * therefore it divides pipe_bpp to 2.
> +	 */
> +	config->pipe_bpp /= 2;

This seems wrong to me. The pipe is still running at the full bpp
(well pipe_bpp in general is a bit of a incorrect concept, but we'll
ignbore that issue for now). More importantly this is not how we
did it for HDMI.

Is there anywhere else besides the link bw computation where you
actually need to know the actual bpc going over the link? If that's
the only place then we should leave pipe_bpp alone and just adjust
there.

>  
>  	/* YCBCR 420 output conversion needs a scaler */
>  	if (skl_update_scaler_crtc(config)) {
> @@ -4453,7 +4464,23 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
>  	 * 011b = 12bpc.
>  	 * 100b = 16bpc.
>  	 */
> -	vsc_sdp.DB17 = 0x1;
> +	switch (crtc_state->pipe_bpp) {
> +	case 12: /* 8bpc */
> +		vsc_sdp.DB17 = 0x1;
> +		break;
> +	case 15: /* 10bpc */
> +		vsc_sdp.DB17 = 0x2;
> +		break;
> +	case 18: /* 12bpc */
> +		vsc_sdp.DB17 = 0x3;
> +		break;
> +	case 24: /* 16bpc */
> +		vsc_sdp.DB17 = 0x4;
> +		break;
> +	default:
> +		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
> +		break;
> +	}
>  
>  	/*
>  	 * Content Type (Bits 2:0)
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[RFC v2 6/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

[Gwan-gyeong Mun]

Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to
HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and
HDMI ports.

v2: Minor style fix.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 50a270a5f4bd..1542031adf57 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -7408,6 +7408,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		connector->ycbcr_420_allowed = true;
+
 	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 
 	intel_dp_aux_init(intel_dp);
-- 
2.20.1

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✗ Fi.CI.SPARSE: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/56059/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dp: Add a config function for YCBCR420 outputs
Okay!

Commit: drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
Okay!

Commit: drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
Okay!

Commit: drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
Okay!

Commit: drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
-O:drivers/gpu/drm/i915/intel_dp.c:1775:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:1775:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1776:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1776:23: warning: expression using sizeof(void)

Commit: drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
Okay!

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✓ Fi.CI.BAT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/56059/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5650 -> Patchwork_12277
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56059/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12277 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-skl-6700k2:      PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       PASS -> FAIL [fdo#109485]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         PASS -> DMESG-FAIL [fdo#103182]

  
#### Possible fixes ####

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         FAIL [fdo#104008] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
  [fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
  [fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530


Participating hosts (44 -> 39)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5650 -> Patchwork_12277

  CI_DRM_5650: a4c5c4791699aeebfff694c222c76abb61900fca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4849: e5088c8218d1c2b559a9e1645d34f929d05c3889 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12277: 0d5135f2c606b0bee3102bb8d006ce5d2c73496a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0d5135f2c606 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
fa8887dafc40 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
db12c10a14ff drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
e48f5ca55282 drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
be4a4dee41bd drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
8d26f53b5669 drm/i915/dp: Add a config function for YCBCR420 outputs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12277/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/56059/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5650_full -> Patchwork_12277_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12277_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@extended-semaphore-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109275] / [fdo#109276]

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109281] +1

  * igt@gem_exec_parse@oacontrol-tracking:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109289]

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +9

  * igt@gem_mocs_settings@mocs-reset-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] / [fdo#109287]

  * igt@gem_mocs_settings@mocs-reset-ctx-render:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109287] +2

  * igt@gem_pwrite@huge-cpu-backwards:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109290]

  * igt@gem_stolen@stolen-fill-purge:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277]

  * igt@i915_pm_rpm@debugfs-read:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#108840]

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109308]

  * igt@i915_pm_rpm@modeset-stress-extra-wait:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724]

  * igt@i915_pm_rpm@system-suspend-devices:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#107724]

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         NOTRUN -> FAIL [fdo#102250]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#107956]
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +4

  * igt@kms_ccs@pipe-a-crc-primary-basic:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107725]

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
    - shard-apl:          PASS -> FAIL [fdo#106510] / [fdo#108145]

  * igt@kms_chamelium@hdmi-edid-read:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +2

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x21-sliding:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-apl:          PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +5

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_flip@flip-vs-suspend:
    - shard-kbl:          PASS -> INCOMPLETE [fdo#103665]

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#109507]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +8
    - shard-glk:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +15

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-iclb:         PASS -> FAIL [fdo#103166] +2

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-apl:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-iclb:         PASS -> FAIL [fdo#109016]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_setmode@basic:
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@kms_tv_load_detect@load-detect:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109309]

  * igt@perf_pmu@rc6:
    - shard-kbl:          PASS -> SKIP [fdo#109271]

  * igt@prime_nv_pcopy@test3_3:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291]

  
#### Possible fixes ####

  * igt@i915_pm_rpm@gem-evict-pwrite:
    - shard-iclb:         INCOMPLETE [fdo#108840] -> PASS

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +4

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
    - shard-hsw:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-c-legacy-gamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-onscreen:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +2

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-iclb:         FAIL [fdo#103166] -> PASS

  
#### Warnings ####

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          FAIL [fdo#109016] -> DMESG-FAIL [fdo#105763]

  
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109275]: https://bugs.freedesktop.org/show_bug.cgi?id=109275
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109281]: https://bugs.freedesktop.org/show_bug.cgi?id=109281
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (6 -> 5)
------------------------------

  Missing    (1): shard-skl 


Build changes
-------------

    * Linux: CI_DRM_5650 -> Patchwork_12277

  CI_DRM_5650: a4c5c4791699aeebfff694c222c76abb61900fca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4849: e5088c8218d1c2b559a9e1645d34f929d05c3889 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12277: 0d5135f2c606b0bee3102bb8d006ce5d2c73496a @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12277/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx