* [PATCH v2 01/12] drm/i915: Store DIMM rank information as a number
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 02/12] drm/i915: Extract functions to derive SKL+ DIMM info Ville Syrjala
` (14 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Life will be easier later if we have the ranks stored
as a bare number.
v2: s/%d/%u/ all over (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 92 +++++++++++++++------------------
drivers/gpu/drm/i915/i915_drv.h | 11 ++--
2 files changed, 45 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b548c292738c..ec3fb349d49e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1068,28 +1068,28 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
intel_gvt_sanitize_options(dev_priv);
}
-static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
+static int skl_get_dimm_ranks(u8 size, u32 rank)
{
if (size == 0)
- return I915_DRAM_RANK_INVALID;
+ return 0;
if (rank == SKL_DRAM_RANK_SINGLE)
- return I915_DRAM_RANK_SINGLE;
+ return 1;
else if (rank == SKL_DRAM_RANK_DUAL)
- return I915_DRAM_RANK_DUAL;
+ return 2;
- return I915_DRAM_RANK_INVALID;
+ return 0;
}
static bool
-skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
+skl_is_16gb_dimm(u8 ranks, u8 size, u8 width)
{
- if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
+ if (ranks == 1 && width == 8 && size == 16)
return true;
- else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
+ else if (ranks == 2 && width == 8 && size == 32)
return true;
- else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
+ else if (ranks == 1 && width == 16 && size == 8)
return true;
- else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
+ else if (ranks == 2 && width == 16 && size == 16)
return true;
return false;
@@ -1120,28 +1120,24 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
tmp_l = val & SKL_DRAM_RANK_MASK;
tmp_s = s_val & SKL_DRAM_RANK_MASK;
- ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
- ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
-
- if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
- ch->s_info.rank == I915_DRAM_RANK_DUAL)
- ch->rank = I915_DRAM_RANK_DUAL;
- else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
- ch->s_info.rank == I915_DRAM_RANK_SINGLE)
- ch->rank = I915_DRAM_RANK_DUAL;
+ ch->l_info.ranks = skl_get_dimm_ranks(ch->l_info.size, tmp_l);
+ ch->s_info.ranks = skl_get_dimm_ranks(ch->s_info.size, tmp_s);
+
+ if (ch->l_info.ranks == 2 || ch->s_info.ranks == 2)
+ ch->ranks = 2;
+ else if (ch->l_info.ranks == 1 && ch->s_info.ranks == 1)
+ ch->ranks = 2;
else
- ch->rank = I915_DRAM_RANK_SINGLE;
+ ch->ranks = 1;
- ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
+ ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.ranks, ch->l_info.size,
ch->l_info.width) ||
- skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
+ skl_is_16gb_dimm(ch->s_info.ranks, ch->s_info.size,
ch->s_info.width);
- DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
- ch->l_info.size, ch->l_info.width,
- ch->l_info.rank ? "dual" : "single",
- ch->s_info.size, ch->s_info.width,
- ch->s_info.rank ? "dual" : "single");
+ DRM_DEBUG_KMS("(size:width:ranks) L(%uGB:X%u:%u) S(%uGB:X%u:%u)\n",
+ ch->l_info.size, ch->l_info.width, ch->l_info.ranks,
+ ch->s_info.size, ch->s_info.width, ch->s_info.ranks);
return 0;
}
@@ -1154,7 +1150,7 @@ intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
(ch0->s_info.size == 0 ||
(ch0->l_info.size == ch0->s_info.size &&
ch0->l_info.width == ch0->s_info.width &&
- ch0->l_info.rank == ch0->s_info.rank)));
+ ch0->l_info.ranks == ch0->s_info.ranks)));
}
static int
@@ -1185,13 +1181,12 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
* will be same as if single rank memory, so consider single rank
* memory.
*/
- if (ch0.rank == I915_DRAM_RANK_SINGLE ||
- ch1.rank == I915_DRAM_RANK_SINGLE)
- dram_info->rank = I915_DRAM_RANK_SINGLE;
+ if (ch0.ranks == 1 || ch1.ranks == 1)
+ dram_info->ranks = 1;
else
- dram_info->rank = max(ch0.rank, ch1.rank);
+ dram_info->ranks = max(ch0.ranks, ch1.ranks);
- if (dram_info->rank == I915_DRAM_RANK_INVALID) {
+ if (dram_info->ranks == 0) {
DRM_INFO("couldn't get memory rank information\n");
return -EINVAL;
}
@@ -1262,8 +1257,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
* Now read each DUNIT8/9/10/11 to check the rank of each dimms.
*/
for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
- u8 size, width;
- enum dram_rank rank;
+ u8 size, width, ranks;
u32 tmp;
val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
@@ -1274,11 +1268,11 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
tmp = val & BXT_DRAM_RANK_MASK;
if (tmp == BXT_DRAM_RANK_SINGLE)
- rank = I915_DRAM_RANK_SINGLE;
+ ranks = 1;
else if (tmp == BXT_DRAM_RANK_DUAL)
- rank = I915_DRAM_RANK_DUAL;
+ ranks = 2;
else
- rank = I915_DRAM_RANK_INVALID;
+ ranks = 0;
tmp = val & BXT_DRAM_SIZE_MASK;
if (tmp == BXT_DRAM_SIZE_4GB)
@@ -1296,22 +1290,21 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
width = (1 << tmp) * 8;
- DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
- width, rank == I915_DRAM_RANK_SINGLE ? "single" :
- rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
+ DRM_DEBUG_KMS("dram size:%uGB width:X%u ranks:%u\n",
+ size, width, ranks);
/*
* If any of the channel is single rank channel,
* worst case output will be same as if single rank
* memory, so consider single rank memory.
*/
- if (dram_info->rank == I915_DRAM_RANK_INVALID)
- dram_info->rank = rank;
- else if (rank == I915_DRAM_RANK_SINGLE)
- dram_info->rank = I915_DRAM_RANK_SINGLE;
+ if (dram_info->ranks == 0)
+ dram_info->ranks = ranks;
+ else if (ranks == 1)
+ dram_info->ranks = 1;
}
- if (dram_info->rank == I915_DRAM_RANK_INVALID) {
+ if (dram_info->ranks == 0) {
DRM_INFO("couldn't get memory rank information\n");
return -EINVAL;
}
@@ -1328,7 +1321,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
int ret;
dram_info->valid = false;
- dram_info->rank = I915_DRAM_RANK_INVALID;
+ dram_info->ranks = 0;
dram_info->bandwidth_kbps = 0;
dram_info->num_channels = 0;
@@ -1358,9 +1351,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
sprintf(bandwidth_str, "unknown");
DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
bandwidth_str, dram_info->num_channels);
- DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
- (dram_info->rank == I915_DRAM_RANK_DUAL) ?
- "dual" : "single", yesno(dram_info->is_16gb_dimm));
+ DRM_DEBUG_KMS("DRAM ranks: %u, 16GB-dimm:%s\n",
+ dram_info->ranks, yesno(dram_info->is_16gb_dimm));
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3b8e354ec8b3..6f8e9910bb47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1826,11 +1826,7 @@ struct drm_i915_private {
bool valid;
bool is_16gb_dimm;
u8 num_channels;
- enum dram_rank {
- I915_DRAM_RANK_INVALID = 0,
- I915_DRAM_RANK_SINGLE,
- I915_DRAM_RANK_DUAL
- } rank;
+ u8 ranks;
u32 bandwidth_kbps;
bool symmetric_memory;
} dram_info;
@@ -2058,10 +2054,9 @@ struct drm_i915_private {
struct dram_channel_info {
struct info {
- u8 size, width;
- enum dram_rank rank;
+ u8 size, width, ranks;
} l_info, s_info;
- enum dram_rank rank;
+ u8 ranks;
bool is_16gb_dimm;
};
--
2.19.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 02/12] drm/i915: Extract functions to derive SKL+ DIMM info
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 01/12] drm/i915: Store DIMM rank information as a number Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 03/12] drm/i915: Polish skl_is_16gb_dimm() Ville Syrjala
` (13 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the code less repetitive by extracting a few small helpers.
v2: Squash in the switch removal for skl_get_dimm_ranks()
(it got misplaced in a rebase accident)
Document what skl_get_dimm_size() returns (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 63 ++++++++++++++++++++-------------
1 file changed, 38 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ec3fb349d49e..45d70ecd9037 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1068,16 +1068,37 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
intel_gvt_sanitize_options(dev_priv);
}
-static int skl_get_dimm_ranks(u8 size, u32 rank)
+/* Returns total GB for the whole DIMM */
+static int skl_get_dimm_size(u16 val)
{
- if (size == 0)
+ return val & SKL_DRAM_SIZE_MASK;
+}
+
+static int skl_get_dimm_width(u16 val)
+{
+ if (skl_get_dimm_size(val) == 0)
return 0;
- if (rank == SKL_DRAM_RANK_SINGLE)
- return 1;
- else if (rank == SKL_DRAM_RANK_DUAL)
- return 2;
- return 0;
+ switch (val & SKL_DRAM_WIDTH_MASK) {
+ case SKL_DRAM_WIDTH_X8:
+ case SKL_DRAM_WIDTH_X16:
+ case SKL_DRAM_WIDTH_X32:
+ val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
+ return 8 << val;
+ default:
+ MISSING_CASE(val);
+ return 0;
+ }
+}
+
+static int skl_get_dimm_ranks(u16 val)
+{
+ if (skl_get_dimm_size(val) == 0)
+ return 0;
+
+ val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
+
+ return val + 1;
}
static bool
@@ -1098,30 +1119,22 @@ skl_is_16gb_dimm(u8 ranks, u8 size, u8 width)
static int
skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
{
- u32 tmp_l, tmp_s;
- u32 s_val = val >> SKL_DRAM_S_SHIFT;
+ u16 tmp_l, tmp_s;
- if (!val)
- return -EINVAL;
+ tmp_l = val & 0xffff;
+ tmp_s = val >> 16;
- tmp_l = val & SKL_DRAM_SIZE_MASK;
- tmp_s = s_val & SKL_DRAM_SIZE_MASK;
+ ch->l_info.size = skl_get_dimm_size(tmp_l);
+ ch->s_info.size = skl_get_dimm_size(tmp_s);
- if (tmp_l == 0 && tmp_s == 0)
+ if (ch->l_info.size == 0 && ch->s_info.size == 0)
return -EINVAL;
- ch->l_info.size = tmp_l;
- ch->s_info.size = tmp_s;
-
- tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
- tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
- ch->l_info.width = (1 << tmp_l) * 8;
- ch->s_info.width = (1 << tmp_s) * 8;
+ ch->l_info.width = skl_get_dimm_width(tmp_l);
+ ch->s_info.width = skl_get_dimm_width(tmp_s);
- tmp_l = val & SKL_DRAM_RANK_MASK;
- tmp_s = s_val & SKL_DRAM_RANK_MASK;
- ch->l_info.ranks = skl_get_dimm_ranks(ch->l_info.size, tmp_l);
- ch->s_info.ranks = skl_get_dimm_ranks(ch->s_info.size, tmp_s);
+ ch->l_info.ranks = skl_get_dimm_ranks(tmp_l);
+ ch->s_info.ranks = skl_get_dimm_ranks(tmp_s);
if (ch->l_info.ranks == 2 || ch->s_info.ranks == 2)
ch->ranks = 2;
--
2.19.2
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 03/12] drm/i915: Polish skl_is_16gb_dimm()
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 01/12] drm/i915: Store DIMM rank information as a number Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 02/12] drm/i915: Extract functions to derive SKL+ DIMM info Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 04/12] drm/i915: Extract BXT DIMM helpers Ville Syrjala
` (12 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass the dimm struct to skl_is_16gb_dimm() rather than passing each
value separately. And let's replace the hardcoded set of values with
some simple arithmetic.
Also fix the byte vs. bit inconsistency in the debug message,
and polish the wording otherwise as well.
v2: Deobfuscate the math (Chris)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 28 ++++++++++++----------------
drivers/gpu/drm/i915/i915_drv.h | 8 +++++---
2 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 45d70ecd9037..e35a75be3a2a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1068,6 +1068,11 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
intel_gvt_sanitize_options(dev_priv);
}
+static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
+{
+ return dimm->ranks * 64 / (dimm->width ?: 1);
+}
+
/* Returns total GB for the whole DIMM */
static int skl_get_dimm_size(u16 val)
{
@@ -1102,18 +1107,10 @@ static int skl_get_dimm_ranks(u16 val)
}
static bool
-skl_is_16gb_dimm(u8 ranks, u8 size, u8 width)
+skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
{
- if (ranks == 1 && width == 8 && size == 16)
- return true;
- else if (ranks == 2 && width == 8 && size == 32)
- return true;
- else if (ranks == 1 && width == 16 && size == 8)
- return true;
- else if (ranks == 2 && width == 16 && size == 16)
- return true;
-
- return false;
+ /* Convert total GB to Gb per DRAM device */
+ return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
}
static int
@@ -1143,10 +1140,9 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
else
ch->ranks = 1;
- ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.ranks, ch->l_info.size,
- ch->l_info.width) ||
- skl_is_16gb_dimm(ch->s_info.ranks, ch->s_info.size,
- ch->s_info.width);
+ ch->is_16gb_dimm =
+ skl_is_16gb_dimm(&ch->l_info) ||
+ skl_is_16gb_dimm(&ch->s_info);
DRM_DEBUG_KMS("(size:width:ranks) L(%uGB:X%u:%u) S(%uGB:X%u:%u)\n",
ch->l_info.size, ch->l_info.width, ch->l_info.ranks,
@@ -1364,7 +1360,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
sprintf(bandwidth_str, "unknown");
DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
bandwidth_str, dram_info->num_channels);
- DRM_DEBUG_KMS("DRAM ranks: %u, 16GB-dimm:%s\n",
+ DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
dram_info->ranks, yesno(dram_info->is_16gb_dimm));
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f8e9910bb47..84e3e3a0bd1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2052,10 +2052,12 @@ struct drm_i915_private {
*/
};
+struct dram_dimm_info {
+ u8 size, width, ranks;
+};
+
struct dram_channel_info {
- struct info {
- u8 size, width, ranks;
- } l_info, s_info;
+ struct dram_dimm_info l_info, s_info;
u8 ranks;
bool is_16gb_dimm;
};
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 04/12] drm/i915: Extract BXT DIMM helpers
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (2 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 03/12] drm/i915: Polish skl_is_16gb_dimm() Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 05/12] drm/i915: Fix DRAM size reporting for BXT Ville Syrjala
` (11 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Polish the bxt DIMM parsing by extracting a few small helpers.
v2: Use struct dram_dimm_info
v3: Document what bxt_get_dimm_size() returns (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 94 ++++++++++++++++++++++-----------
1 file changed, 63 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e35a75be3a2a..bba051d9f21d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1238,6 +1238,60 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
return 0;
}
+/* Returns Gb per DRAM device */
+static int bxt_get_dimm_size(u32 val)
+{
+ switch (val & BXT_DRAM_SIZE_MASK) {
+ case BXT_DRAM_SIZE_4GB:
+ return 4;
+ case BXT_DRAM_SIZE_6GB:
+ return 6;
+ case BXT_DRAM_SIZE_8GB:
+ return 8;
+ case BXT_DRAM_SIZE_12GB:
+ return 12;
+ case BXT_DRAM_SIZE_16GB:
+ return 16;
+ default:
+ MISSING_CASE(val);
+ return 0;
+ }
+}
+
+static int bxt_get_dimm_width(u32 val)
+{
+ if (!bxt_get_dimm_size(val))
+ return 0;
+
+ val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
+
+ return 8 << val;
+}
+
+static int bxt_get_dimm_ranks(u32 val)
+{
+ if (!bxt_get_dimm_size(val))
+ return 0;
+
+ switch (val & BXT_DRAM_RANK_MASK) {
+ case BXT_DRAM_RANK_SINGLE:
+ return 1;
+ case BXT_DRAM_RANK_DUAL:
+ return 2;
+ default:
+ MISSING_CASE(val);
+ return 0;
+ }
+}
+
+static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
+ u32 val)
+{
+ dimm->size = bxt_get_dimm_size(val);
+ dimm->width = bxt_get_dimm_width(val);
+ dimm->ranks = bxt_get_dimm_ranks(val);
+}
+
static int
bxt_get_dram_info(struct drm_i915_private *dev_priv)
{
@@ -1266,41 +1320,19 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
* Now read each DUNIT8/9/10/11 to check the rank of each dimms.
*/
for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
- u8 size, width, ranks;
- u32 tmp;
+ struct dram_dimm_info dimm;
val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
if (val == 0xFFFFFFFF)
continue;
dram_info->num_channels++;
- tmp = val & BXT_DRAM_RANK_MASK;
-
- if (tmp == BXT_DRAM_RANK_SINGLE)
- ranks = 1;
- else if (tmp == BXT_DRAM_RANK_DUAL)
- ranks = 2;
- else
- ranks = 0;
-
- tmp = val & BXT_DRAM_SIZE_MASK;
- if (tmp == BXT_DRAM_SIZE_4GB)
- size = 4;
- else if (tmp == BXT_DRAM_SIZE_6GB)
- size = 6;
- else if (tmp == BXT_DRAM_SIZE_8GB)
- size = 8;
- else if (tmp == BXT_DRAM_SIZE_12GB)
- size = 12;
- else if (tmp == BXT_DRAM_SIZE_16GB)
- size = 16;
- else
- size = 0;
-
- tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
- width = (1 << tmp) * 8;
- DRM_DEBUG_KMS("dram size:%uGB width:X%u ranks:%u\n",
- size, width, ranks);
+
+ bxt_get_dimm_info(&dimm, val);
+
+ DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u\n",
+ i - BXT_D_CR_DRP0_DUNIT_START,
+ dimm.size, dimm.width, dimm.ranks);
/*
* If any of the channel is single rank channel,
@@ -1308,8 +1340,8 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
* memory, so consider single rank memory.
*/
if (dram_info->ranks == 0)
- dram_info->ranks = ranks;
- else if (ranks == 1)
+ dram_info->ranks = dimm.ranks;
+ else if (dimm.ranks == 1)
dram_info->ranks = 1;
}
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 05/12] drm/i915: Fix DRAM size reporting for BXT
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (3 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 04/12] drm/i915: Extract BXT DIMM helpers Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 06/12] drm/i915: Extract DIMM info on GLK too Ville Syrjala
` (10 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The BXT DUNIT register tells us the size of each DRAM device
in Gb. We want to report the size of the whole DIMM in GB, so
that it matches how we report it for non-LP platforms.
v2: Deobfuscate the math (Chris)
s/GB/GBIT/ in the register bit definitions (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 17 +++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bba051d9f21d..a3cf74a00b3f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1242,15 +1242,15 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
static int bxt_get_dimm_size(u32 val)
{
switch (val & BXT_DRAM_SIZE_MASK) {
- case BXT_DRAM_SIZE_4GB:
+ case BXT_DRAM_SIZE_4GBIT:
return 4;
- case BXT_DRAM_SIZE_6GB:
+ case BXT_DRAM_SIZE_6GBIT:
return 6;
- case BXT_DRAM_SIZE_8GB:
+ case BXT_DRAM_SIZE_8GBIT:
return 8;
- case BXT_DRAM_SIZE_12GB:
+ case BXT_DRAM_SIZE_12GBIT:
return 12;
- case BXT_DRAM_SIZE_16GB:
+ case BXT_DRAM_SIZE_16GBIT:
return 16;
default:
MISSING_CASE(val);
@@ -1287,9 +1287,14 @@ static int bxt_get_dimm_ranks(u32 val)
static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
u32 val)
{
- dimm->size = bxt_get_dimm_size(val);
dimm->width = bxt_get_dimm_width(val);
dimm->ranks = bxt_get_dimm_ranks(val);
+
+ /*
+ * Size in register is Gb per DRAM device. Convert to total
+ * GB to match the way we report this for non-LP platforms.
+ */
+ dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
}
static int
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 16ce9c609c65..75236b4f0daf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9856,11 +9856,11 @@ enum skl_power_gate {
#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
#define BXT_DRAM_SIZE_MASK (0x7 << 6)
#define BXT_DRAM_SIZE_SHIFT 6
-#define BXT_DRAM_SIZE_4GB (0x0 << 6)
-#define BXT_DRAM_SIZE_6GB (0x1 << 6)
-#define BXT_DRAM_SIZE_8GB (0x2 << 6)
-#define BXT_DRAM_SIZE_12GB (0x3 << 6)
-#define BXT_DRAM_SIZE_16GB (0x4 << 6)
+#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
+#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
+#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
+#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
+#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 06/12] drm/i915: Extract DIMM info on GLK too
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (4 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 05/12] drm/i915: Fix DRAM size reporting for BXT Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 07/12] drm/i915: Use dram_dimm_info more Ville Syrjala
` (9 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The BXT code for parsing DIMM info works for GLK too. Let's
dig it out even if we might not need it immediately.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a3cf74a00b3f..7f8bdebd9f1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1378,11 +1378,11 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
*/
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
- if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) < 9)
return;
/* Need to calculate bandwidth only for Gen9 */
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ret = bxt_get_dram_info(dev_priv);
else if (IS_GEN(dev_priv, 9))
ret = skl_get_dram_info(dev_priv);
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 07/12] drm/i915: Use dram_dimm_info more
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (5 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 06/12] drm/i915: Extract DIMM info on GLK too Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 08/12] drm/i915: Generalize intel_is_dram_symmetric() Ville Syrjala
` (8 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reduce the code duplication a bit by sharing the same
code for parsing both DIMMs on a channel.
v2: s/%d/%u/ all over (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++++++++++++---------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7f8bdebd9f1a..71a4da5caee7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1113,25 +1113,30 @@ skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
}
-static int
-skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
+static void
+skl_dram_get_dimm_info(struct dram_dimm_info *dimm,
+ int channel, char dimm_name, u16 val)
{
- u16 tmp_l, tmp_s;
+ dimm->size = skl_get_dimm_size(val);
+ dimm->width = skl_get_dimm_width(val);
+ dimm->ranks = skl_get_dimm_ranks(val);
- tmp_l = val & 0xffff;
- tmp_s = val >> 16;
+ DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
+ channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
+ yesno(skl_is_16gb_dimm(dimm)));
+}
- ch->l_info.size = skl_get_dimm_size(tmp_l);
- ch->s_info.size = skl_get_dimm_size(tmp_s);
+static int
+skl_dram_get_channel_info(struct dram_channel_info *ch,
+ int channel, u32 val)
+{
+ skl_dram_get_dimm_info(&ch->l_info, channel, 'L', val & 0xffff);
+ skl_dram_get_dimm_info(&ch->s_info, channel, 'S', val >> 16);
- if (ch->l_info.size == 0 && ch->s_info.size == 0)
+ if (ch->l_info.size == 0 && ch->s_info.size == 0) {
+ DRM_DEBUG_KMS("CH%u not populated\n", channel);
return -EINVAL;
-
- ch->l_info.width = skl_get_dimm_width(tmp_l);
- ch->s_info.width = skl_get_dimm_width(tmp_s);
-
- ch->l_info.ranks = skl_get_dimm_ranks(tmp_l);
- ch->s_info.ranks = skl_get_dimm_ranks(tmp_s);
+ }
if (ch->l_info.ranks == 2 || ch->s_info.ranks == 2)
ch->ranks = 2;
@@ -1144,9 +1149,8 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
skl_is_16gb_dimm(&ch->l_info) ||
skl_is_16gb_dimm(&ch->s_info);
- DRM_DEBUG_KMS("(size:width:ranks) L(%uGB:X%u:%u) S(%uGB:X%u:%u)\n",
- ch->l_info.size, ch->l_info.width, ch->l_info.ranks,
- ch->s_info.size, ch->s_info.width, ch->s_info.ranks);
+ DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
+ channel, ch->ranks, yesno(ch->is_16gb_dimm));
return 0;
}
@@ -1166,17 +1170,17 @@ static int
skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
{
struct dram_info *dram_info = &dev_priv->dram_info;
- struct dram_channel_info ch0, ch1;
+ struct dram_channel_info ch0 = {}, ch1 = {};
u32 val_ch0, val_ch1;
int ret;
val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch0, val_ch0);
+ ret = skl_dram_get_channel_info(&ch0, 0, val_ch0);
if (ret == 0)
dram_info->num_channels++;
val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch1, val_ch1);
+ ret = skl_dram_get_channel_info(&ch1, 1, val_ch1);
if (ret == 0)
dram_info->num_channels++;
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 08/12] drm/i915: Generalize intel_is_dram_symmetric()
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (6 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 07/12] drm/i915: Use dram_dimm_info more Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 09/12] drm/i914: s/l_info/dimm_l/ etc Ville Syrjala
` (7 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Decouple intel_is_dram_symmetric() from the raw register values
by comparing just the dram_channel_info structs.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 71a4da5caee7..08914761303d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1156,14 +1156,12 @@ skl_dram_get_channel_info(struct dram_channel_info *ch,
}
static bool
-intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
- struct dram_channel_info *ch0)
+intel_is_dram_symmetric(const struct dram_channel_info *ch0,
+ const struct dram_channel_info *ch1)
{
- return (val_ch0 == val_ch1 &&
+ return !memcmp(ch0, ch1, sizeof(*ch0)) &&
(ch0->s_info.size == 0 ||
- (ch0->l_info.size == ch0->s_info.size &&
- ch0->l_info.width == ch0->s_info.width &&
- ch0->l_info.ranks == ch0->s_info.ranks)));
+ !memcmp(&ch0->l_info, &ch0->s_info, sizeof(ch0->l_info)));
}
static int
@@ -1171,16 +1169,16 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
{
struct dram_info *dram_info = &dev_priv->dram_info;
struct dram_channel_info ch0 = {}, ch1 = {};
- u32 val_ch0, val_ch1;
+ u32 val;
int ret;
- val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch0, 0, val_ch0);
+ val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+ ret = skl_dram_get_channel_info(&ch0, 0, val);
if (ret == 0)
dram_info->num_channels++;
- val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch1, 1, val_ch1);
+ val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+ ret = skl_dram_get_channel_info(&ch1, 1, val);
if (ret == 0)
dram_info->num_channels++;
@@ -1206,12 +1204,10 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
- dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
- val_ch1,
- &ch0);
+ dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
- DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
- dev_priv->dram_info.symmetric_memory ? "" : "not ");
+ DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
+ yesno(dram_info->symmetric_memory));
return 0;
}
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 09/12] drm/i914: s/l_info/dimm_l/ etc.
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (7 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 08/12] drm/i915: Generalize intel_is_dram_symmetric() Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 10/12] drm/i915: Clean up intel_get_dram_info() a bit Ville Syrjala
` (6 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the dimm info structs for clarity.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 08914761303d..54b40c9ea1f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1130,24 +1130,24 @@ static int
skl_dram_get_channel_info(struct dram_channel_info *ch,
int channel, u32 val)
{
- skl_dram_get_dimm_info(&ch->l_info, channel, 'L', val & 0xffff);
- skl_dram_get_dimm_info(&ch->s_info, channel, 'S', val >> 16);
+ skl_dram_get_dimm_info(&ch->dimm_l, channel, 'L', val & 0xffff);
+ skl_dram_get_dimm_info(&ch->dimm_s, channel, 'S', val >> 16);
- if (ch->l_info.size == 0 && ch->s_info.size == 0) {
+ if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
DRM_DEBUG_KMS("CH%u not populated\n", channel);
return -EINVAL;
}
- if (ch->l_info.ranks == 2 || ch->s_info.ranks == 2)
+ if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
ch->ranks = 2;
- else if (ch->l_info.ranks == 1 && ch->s_info.ranks == 1)
+ else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
ch->ranks = 2;
else
ch->ranks = 1;
ch->is_16gb_dimm =
- skl_is_16gb_dimm(&ch->l_info) ||
- skl_is_16gb_dimm(&ch->s_info);
+ skl_is_16gb_dimm(&ch->dimm_l) ||
+ skl_is_16gb_dimm(&ch->dimm_s);
DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
channel, ch->ranks, yesno(ch->is_16gb_dimm));
@@ -1160,8 +1160,8 @@ intel_is_dram_symmetric(const struct dram_channel_info *ch0,
const struct dram_channel_info *ch1)
{
return !memcmp(ch0, ch1, sizeof(*ch0)) &&
- (ch0->s_info.size == 0 ||
- !memcmp(&ch0->l_info, &ch0->s_info, sizeof(ch0->l_info)));
+ (ch0->dimm_s.size == 0 ||
+ !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
}
static int
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84e3e3a0bd1e..41b7530b3d05 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2057,7 +2057,7 @@ struct dram_dimm_info {
};
struct dram_channel_info {
- struct dram_dimm_info l_info, s_info;
+ struct dram_dimm_info dimm_l, dimm_s;
u8 ranks;
bool is_16gb_dimm;
};
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 10/12] drm/i915: Clean up intel_get_dram_info() a bit
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (8 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 09/12] drm/i914: s/l_info/dimm_l/ etc Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 11/12] drm/i915: Extract DIMM info on cnl+ Ville Syrjala
` (5 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Remove the pointless zero initialization of bunch of things
(the thing is kzalloc()ed).
Also throw out the mostly useless on-stack string. I think
it'll be clear enough from the logs that 0 means unknown.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 54b40c9ea1f7..0d00f837ba7f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1363,14 +1363,8 @@ static void
intel_get_dram_info(struct drm_i915_private *dev_priv)
{
struct dram_info *dram_info = &dev_priv->dram_info;
- char bandwidth_str[32];
int ret;
- dram_info->valid = false;
- dram_info->ranks = 0;
- dram_info->bandwidth_kbps = 0;
- dram_info->num_channels = 0;
-
/*
* Assume 16Gb DIMMs are present until proven otherwise.
* This is only used for the level 0 watermark latency
@@ -1391,12 +1385,10 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
if (ret)
return;
- if (dram_info->bandwidth_kbps)
- sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
- else
- sprintf(bandwidth_str, "unknown");
- DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
- bandwidth_str, dram_info->num_channels);
+ DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
+ dram_info->bandwidth_kbps,
+ dram_info->num_channels);
+
DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
dram_info->ranks, yesno(dram_info->is_16gb_dimm));
}
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 11/12] drm/i915: Extract DIMM info on cnl+
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (9 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 10/12] drm/i915: Clean up intel_get_dram_info() a bit Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:35 ` [PATCH v2 12/12] drm/i915: Read out memory type Ville Syrjala
` (4 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We'll need information about the memory configuration on cnl+ too.
Extend the code to parse the slightly changed register layout.
v2: Document what cnl_get_dimm_size() returns (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 66 ++++++++++++++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++-
2 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0d00f837ba7f..611e15edcd66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1106,6 +1106,39 @@ static int skl_get_dimm_ranks(u16 val)
return val + 1;
}
+/* Returns total GB for the whole DIMM */
+static int cnl_get_dimm_size(u16 val)
+{
+ return (val & CNL_DRAM_SIZE_MASK) / 2;
+}
+
+static int cnl_get_dimm_width(u16 val)
+{
+ if (cnl_get_dimm_size(val) == 0)
+ return 0;
+
+ switch (val & CNL_DRAM_WIDTH_MASK) {
+ case CNL_DRAM_WIDTH_X8:
+ case CNL_DRAM_WIDTH_X16:
+ case CNL_DRAM_WIDTH_X32:
+ val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
+ return 8 << val;
+ default:
+ MISSING_CASE(val);
+ return 0;
+ }
+}
+
+static int cnl_get_dimm_ranks(u16 val)
+{
+ if (cnl_get_dimm_size(val) == 0)
+ return 0;
+
+ val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
+
+ return val + 1;
+}
+
static bool
skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
{
@@ -1114,12 +1147,19 @@ skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
}
static void
-skl_dram_get_dimm_info(struct dram_dimm_info *dimm,
+skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
+ struct dram_dimm_info *dimm,
int channel, char dimm_name, u16 val)
{
- dimm->size = skl_get_dimm_size(val);
- dimm->width = skl_get_dimm_width(val);
- dimm->ranks = skl_get_dimm_ranks(val);
+ if (INTEL_GEN(dev_priv) >= 10) {
+ dimm->size = cnl_get_dimm_size(val);
+ dimm->width = cnl_get_dimm_width(val);
+ dimm->ranks = cnl_get_dimm_ranks(val);
+ } else {
+ dimm->size = skl_get_dimm_size(val);
+ dimm->width = skl_get_dimm_width(val);
+ dimm->ranks = skl_get_dimm_ranks(val);
+ }
DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
@@ -1127,11 +1167,14 @@ skl_dram_get_dimm_info(struct dram_dimm_info *dimm,
}
static int
-skl_dram_get_channel_info(struct dram_channel_info *ch,
+skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
+ struct dram_channel_info *ch,
int channel, u32 val)
{
- skl_dram_get_dimm_info(&ch->dimm_l, channel, 'L', val & 0xffff);
- skl_dram_get_dimm_info(&ch->dimm_s, channel, 'S', val >> 16);
+ skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
+ channel, 'L', val & 0xffff);
+ skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
+ channel, 'S', val >> 16);
if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
DRM_DEBUG_KMS("CH%u not populated\n", channel);
@@ -1173,12 +1216,12 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
int ret;
val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch0, 0, val);
+ ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
if (ret == 0)
dram_info->num_channels++;
val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
- ret = skl_dram_get_channel_info(&ch1, 1, val);
+ ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
if (ret == 0)
dram_info->num_channels++;
@@ -1375,13 +1418,10 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) < 9)
return;
- /* Need to calculate bandwidth only for Gen9 */
if (IS_GEN9_LP(dev_priv))
ret = bxt_get_dram_info(dev_priv);
- else if (IS_GEN(dev_priv, 9))
- ret = skl_get_dram_info(dev_priv);
else
- ret = skl_dram_get_channels_info(dev_priv);
+ ret = skl_get_dram_info(dev_priv);
if (ret)
return;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75236b4f0daf..695eb3ec7187 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9877,8 +9877,21 @@ enum skl_power_gate {
#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
#define SKL_DRAM_RANK_MASK (0x1 << 10)
#define SKL_DRAM_RANK_SHIFT 10
-#define SKL_DRAM_RANK_SINGLE (0x0 << 10)
-#define SKL_DRAM_RANK_DUAL (0x1 << 10)
+#define SKL_DRAM_RANK_1 (0x0 << 10)
+#define SKL_DRAM_RANK_2 (0x1 << 10)
+#define SKL_DRAM_RANK_MASK (0x1 << 10)
+#define CNL_DRAM_SIZE_MASK 0x7F
+#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
+#define CNL_DRAM_WIDTH_SHIFT 7
+#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
+#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
+#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
+#define CNL_DRAM_RANK_MASK (0x3 << 9)
+#define CNL_DRAM_RANK_SHIFT 9
+#define CNL_DRAM_RANK_1 (0x0 << 9)
+#define CNL_DRAM_RANK_2 (0x1 << 9)
+#define CNL_DRAM_RANK_3 (0x2 << 9)
+#define CNL_DRAM_RANK_4 (0x3 << 9)
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using I915_WRITE. */
--
2.19.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 12/12] drm/i915: Read out memory type
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (10 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 11/12] drm/i915: Extract DIMM info on cnl+ Ville Syrjala
@ 2019-03-06 20:35 ` Ville Syrjala
2019-03-06 20:57 ` ✗ Fi.CI.CHECKPATCH: warning for Polish DRAM information readout code (rev6) Patchwork
` (3 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjala @ 2019-03-06 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We'll need to know the memory type in the system for some
bandwidth limitations and whatnot. Let's read that out on
gen9+.
v2: Rebase
v3: Fix the copy paste fail in the BXT bit definitions (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 84 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 13 +++++
3 files changed, 100 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 611e15edcd66..bcfc12dd9dda 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1068,6 +1068,26 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
intel_gvt_sanitize_options(dev_priv);
}
+#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
+
+static const char *intel_dram_type_str(enum intel_dram_type type)
+{
+ static const char * const str[] = {
+ DRAM_TYPE_STR(UNKNOWN),
+ DRAM_TYPE_STR(DDR3),
+ DRAM_TYPE_STR(DDR4),
+ DRAM_TYPE_STR(LPDDR3),
+ DRAM_TYPE_STR(LPDDR4),
+ };
+
+ if (type >= ARRAY_SIZE(str))
+ type = INTEL_DRAM_UNKNOWN;
+
+ return str[type];
+}
+
+#undef DRAM_TYPE_STR
+
static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
{
return dimm->ranks * 64 / (dimm->width ?: 1);
@@ -1254,6 +1274,28 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
return 0;
}
+static enum intel_dram_type
+skl_get_dram_type(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+
+ switch (val & SKL_DRAM_DDR_TYPE_MASK) {
+ case SKL_DRAM_DDR_TYPE_DDR3:
+ return INTEL_DRAM_DDR3;
+ case SKL_DRAM_DDR_TYPE_DDR4:
+ return INTEL_DRAM_DDR4;
+ case SKL_DRAM_DDR_TYPE_LPDDR3:
+ return INTEL_DRAM_LPDDR3;
+ case SKL_DRAM_DDR_TYPE_LPDDR4:
+ return INTEL_DRAM_LPDDR4;
+ default:
+ MISSING_CASE(val);
+ return INTEL_DRAM_UNKNOWN;
+ }
+}
+
static int
skl_get_dram_info(struct drm_i915_private *dev_priv)
{
@@ -1261,6 +1303,9 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
u32 mem_freq_khz, val;
int ret;
+ dram_info->type = skl_get_dram_type(dev_priv);
+ DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
+
ret = skl_dram_get_channels_info(dev_priv);
if (ret)
return ret;
@@ -1327,6 +1372,26 @@ static int bxt_get_dimm_ranks(u32 val)
}
}
+static enum intel_dram_type bxt_get_dimm_type(u32 val)
+{
+ if (!bxt_get_dimm_size(val))
+ return INTEL_DRAM_UNKNOWN;
+
+ switch (val & BXT_DRAM_TYPE_MASK) {
+ case BXT_DRAM_TYPE_DDR3:
+ return INTEL_DRAM_DDR3;
+ case BXT_DRAM_TYPE_LPDDR3:
+ return INTEL_DRAM_LPDDR3;
+ case BXT_DRAM_TYPE_DDR4:
+ return INTEL_DRAM_DDR4;
+ case BXT_DRAM_TYPE_LPDDR4:
+ return INTEL_DRAM_LPDDR4;
+ default:
+ MISSING_CASE(val);
+ return INTEL_DRAM_UNKNOWN;
+ }
+}
+
static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
u32 val)
{
@@ -1369,6 +1434,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
*/
for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
struct dram_dimm_info dimm;
+ enum intel_dram_type type;
val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
if (val == 0xFFFFFFFF)
@@ -1377,10 +1443,16 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
dram_info->num_channels++;
bxt_get_dimm_info(&dimm, val);
+ type = bxt_get_dimm_type(val);
+
+ WARN_ON(type != INTEL_DRAM_UNKNOWN &&
+ dram_info->type != INTEL_DRAM_UNKNOWN &&
+ dram_info->type != type);
- DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u\n",
+ DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
i - BXT_D_CR_DRP0_DUNIT_START,
- dimm.size, dimm.width, dimm.ranks);
+ dimm.size, dimm.width, dimm.ranks,
+ intel_dram_type_str(type));
/*
* If any of the channel is single rank channel,
@@ -1391,10 +1463,14 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
dram_info->ranks = dimm.ranks;
else if (dimm.ranks == 1)
dram_info->ranks = 1;
+
+ if (type != INTEL_DRAM_UNKNOWN)
+ dram_info->type = type;
}
- if (dram_info->ranks == 0) {
- DRM_INFO("couldn't get memory rank information\n");
+ if (dram_info->type == INTEL_DRAM_UNKNOWN ||
+ dram_info->ranks == 0) {
+ DRM_INFO("couldn't get memory information\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 41b7530b3d05..a5b314a0c415 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1829,6 +1829,13 @@ struct drm_i915_private {
u8 ranks;
u32 bandwidth_kbps;
bool symmetric_memory;
+ enum intel_dram_type {
+ INTEL_DRAM_UNKNOWN,
+ INTEL_DRAM_DDR3,
+ INTEL_DRAM_DDR4,
+ INTEL_DRAM_LPDDR3,
+ INTEL_DRAM_LPDDR4
+ } type;
} dram_info;
struct i915_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 695eb3ec7187..2665ffe1e2a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9861,11 +9861,24 @@ enum skl_power_gate {
#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
+#define BXT_DRAM_TYPE_MASK (0x7 << 22)
+#define BXT_DRAM_TYPE_SHIFT 22
+#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
+#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
+#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
+#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
#define SKL_REQ_DATA_MASK (0xF << 0)
+#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
+#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
+#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
+#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
+#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
+#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DRAM_S_SHIFT 16
--
2.19.2
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^ permalink raw reply related [flat|nested] 19+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Polish DRAM information readout code (rev6)
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (11 preceding siblings ...)
2019-03-06 20:35 ` [PATCH v2 12/12] drm/i915: Read out memory type Ville Syrjala
@ 2019-03-06 20:57 ` Patchwork
2019-03-06 21:02 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-06 20:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: Polish DRAM information readout code (rev6)
URL : https://patchwork.freedesktop.org/series/57213/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
79f39cc66d09 drm/i915: Store DIMM rank information as a number
574621760038 drm/i915: Extract functions to derive SKL+ DIMM info
29a5a84fc0bc drm/i915: Polish skl_is_16gb_dimm()
73fd5eb48602 drm/i915: Extract BXT DIMM helpers
c3765df44e64 drm/i915: Fix DRAM size reporting for BXT
71c1e40d02c4 drm/i915: Extract DIMM info on GLK too
c697cd312061 drm/i915: Use dram_dimm_info more
309b2b7535a4 drm/i915: Generalize intel_is_dram_symmetric()
9ca275a44663 drm/i914: s/l_info/dimm_l/ etc.
a29bb0ba5839 drm/i915: Clean up intel_get_dram_info() a bit
46998aeec480 drm/i915: Extract DIMM info on cnl+
a8f880385195 drm/i915: Read out memory type
-:27: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#27: FILE: drivers/gpu/drm/i915/i915_drv.c:1071:
+#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
total: 1 errors, 0 warnings, 0 checks, 167 lines checked
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^ permalink raw reply [flat|nested] 19+ messages in thread* ✗ Fi.CI.SPARSE: warning for Polish DRAM information readout code (rev6)
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (12 preceding siblings ...)
2019-03-06 20:57 ` ✗ Fi.CI.CHECKPATCH: warning for Polish DRAM information readout code (rev6) Patchwork
@ 2019-03-06 21:02 ` Patchwork
2019-03-06 21:21 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-06 23:51 ` ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-06 21:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: Polish DRAM information readout code (rev6)
URL : https://patchwork.freedesktop.org/series/57213/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Store DIMM rank information as a number
-O:drivers/gpu/drm/i915/i915_drv.c:1192:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/i915_drv.c:1192:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1187:36: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1187:36: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3543:16: warning: expression using sizeof(void)
Commit: drm/i915: Extract functions to derive SKL+ DIMM info
Okay!
Commit: drm/i915: Polish skl_is_16gb_dimm()
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3543:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3545:16: warning: expression using sizeof(void)
Commit: drm/i915: Extract BXT DIMM helpers
Okay!
Commit: drm/i915: Fix DRAM size reporting for BXT
Okay!
Commit: drm/i915: Extract DIMM info on GLK too
Okay!
Commit: drm/i915: Use dram_dimm_info more
Okay!
Commit: drm/i915: Generalize intel_is_dram_symmetric()
Okay!
Commit: drm/i914: s/l_info/dimm_l/ etc.
Okay!
Commit: drm/i915: Clean up intel_get_dram_info() a bit
Okay!
Commit: drm/i915: Extract DIMM info on cnl+
Okay!
Commit: drm/i915: Read out memory type
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3545:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3552:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ Fi.CI.BAT: success for Polish DRAM information readout code (rev6)
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (13 preceding siblings ...)
2019-03-06 21:02 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-03-06 21:21 ` Patchwork
2019-03-06 23:51 ` ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-06 21:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: Polish DRAM information readout code (rev6)
URL : https://patchwork.freedesktop.org/series/57213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5713 -> Patchwork_12398
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57213/revisions/6/mbox/
Known issues
------------
Here are the changes found in Patchwork_12398 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7560u: NOTRUN -> SKIP [fdo#109271] +17
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7560u: PASS -> FAIL [fdo#103375]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: INCOMPLETE -> PASS
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: WARN [fdo#109380] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: SKIP [fdo#109271] -> PASS +33
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: FAIL [fdo#104008] -> PASS
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
Participating hosts (44 -> 41)
------------------------------
Additional (1): fi-gdg-551
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_5713 -> Patchwork_12398
CI_DRM_5713: 29a41cf5dd10ee68873c16b67d6212b3bd470906 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4875: 91908d36d0d5c90eea86e29736d2748d5ec55335 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12398: a8f88038519591587c54a4eabe4b3c36233635b5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a8f880385195 drm/i915: Read out memory type
46998aeec480 drm/i915: Extract DIMM info on cnl+
a29bb0ba5839 drm/i915: Clean up intel_get_dram_info() a bit
9ca275a44663 drm/i914: s/l_info/dimm_l/ etc.
309b2b7535a4 drm/i915: Generalize intel_is_dram_symmetric()
c697cd312061 drm/i915: Use dram_dimm_info more
71c1e40d02c4 drm/i915: Extract DIMM info on GLK too
c3765df44e64 drm/i915: Fix DRAM size reporting for BXT
73fd5eb48602 drm/i915: Extract BXT DIMM helpers
29a5a84fc0bc drm/i915: Polish skl_is_16gb_dimm()
574621760038 drm/i915: Extract functions to derive SKL+ DIMM info
79f39cc66d09 drm/i915: Store DIMM rank information as a number
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12398/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ Fi.CI.IGT: success for Polish DRAM information readout code (rev6)
2019-03-06 20:35 [PATCH v2 00/12] Polish DRAM information readout code Ville Syrjala
` (14 preceding siblings ...)
2019-03-06 21:21 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-06 23:51 ` Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-06 23:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: Polish DRAM information readout code (rev6)
URL : https://patchwork.freedesktop.org/series/57213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5713_full -> Patchwork_12398_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12398_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vecs0-none:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +24
* igt@gem_ctx_isolation@vecs0-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_rpm@basic-pci-d3-state:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@i915_selftest@live_hangcheck:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@kms_busy@extended-modeset-hang-newfb-render-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@extended-pageflip-hang-newfb-render-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_chamelium@dp-hpd-fast:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +64
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: NOTRUN -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_flip_tiling@flip-to-yf-tiled:
- shard-skl: NOTRUN -> FAIL [fdo#107931]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +34
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-skl: NOTRUN -> FAIL [fdo#103166] / [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166] +1
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-glk: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_vblank@pipe-c-wait-busy:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@prime_nv_pcopy@test3_5:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +41
#### Possible fixes ####
* igt@kms_chv_cursor_fail@pipe-a-128x128-right-edge:
- shard-skl: FAIL [fdo#104671] -> PASS +1
* igt@kms_color@pipe-b-degamma:
- shard-skl: FAIL [fdo#104782] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_color@pipe-c-legacy-gamma:
- shard-glk: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-skl: FAIL [fdo#105682] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS +3
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +4
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 6)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5713 -> Patchwork_12398
CI_DRM_5713: 29a41cf5dd10ee68873c16b67d6212b3bd470906 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4875: 91908d36d0d5c90eea86e29736d2748d5ec55335 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12398: a8f88038519591587c54a4eabe4b3c36233635b5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12398/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread