From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable
Date: Fri, 22 Mar 2019 16:33:21 +0200 [thread overview]
Message-ID: <20190322143321.GA3888@intel.com> (raw)
In-Reply-To: <1553256832-15257-1-git-send-email-vandita.kulkarni@intel.com>
On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote:
> IO enable sequencing needs ddi clocks enabled.
> These clocks will be gated at a later point in
> the enable sequence.
>
> v2: Fix the commit header (uma)
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index beb30d9..6a5b9fa 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> +
> + val = I915_READ(DPCLKA_CFGCR0_ICL);
This read looks totally redundant.
> + for_each_dsi_port(port, intel_dsi->ports) {
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + }
> + I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> +
> POSTING_READ(DPCLKA_CFGCR0_ICL);
>
> mutex_unlock(&dev_priv->dpll_lock);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-03-22 14:33 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni
2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni
2019-03-22 14:32 ` Ville Syrjälä
2019-03-22 15:37 ` Kulkarni, Vandita
2019-03-22 15:56 ` Ville Syrjälä
2019-03-25 5:41 ` Kulkarni, Vandita
2019-03-22 13:45 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork
2019-03-22 14:33 ` Ville Syrjälä [this message]
2019-03-22 15:33 ` [v2 1/2] " Kulkarni, Vandita
2019-03-23 11:01 ` ✓ Fi.CI.IGT: success for series starting with [v2,1/2] " Patchwork
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