* [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable
@ 2019-03-22 12:13 Vandita Kulkarni
2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Vandita Kulkarni @ 2019-03-22 12:13 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at a later point in
the enable sequence.
v2: Fix the commit header (uma)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index beb30d9..6a5b9fa 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ }
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
POSTING_READ(DPCLKA_CFGCR0_ICL);
mutex_unlock(&dev_priv->dpll_lock);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi 2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni @ 2019-03-22 12:13 ` Vandita Kulkarni 2019-03-22 14:32 ` Ville Syrjälä 2019-03-22 13:45 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: Vandita Kulkarni @ 2019-03-22 12:13 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/icl_dsi.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 6a5b9fa..5caf41f 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1124,7 +1124,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) DRM_ERROR("DDI port:%c buffer not idle\n", port_name(port)); } - gen11_dsi_ungate_clocks(encoder); + gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 933df3a..17a03fa 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) return; } /* - * DSI ports should have their DDI clock ungated when disabled - * and gated when enabled. + * For MIPI DSI we unagate the clocks later as part of + * enable sequence. Keep them gated by default. */ - ddi_clk_needed = !encoder->base.crtc; + ddi_clk_needed = false; } val = I915_READ(DPCLKA_CFGCR0_ICL); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi 2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni @ 2019-03-22 14:32 ` Ville Syrjälä 2019-03-22 15:37 ` Kulkarni, Vandita 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2019-03-22 14:32 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: jani.nikula, intel-gfx On Fri, Mar 22, 2019 at 05:43:52PM +0530, Vandita Kulkarni wrote: > Re-enable clock gating of DDI clocks. > > v2: Fix the default ddi clk state for mipi-dsi (Imre) > > Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index 6a5b9fa..5caf41f 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -1124,7 +1124,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) > DRM_ERROR("DDI port:%c buffer not idle\n", > port_name(port)); > } > - gen11_dsi_ungate_clocks(encoder); > + gen11_dsi_gate_clocks(encoder); > } > > static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 933df3a..17a03fa 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) > return; > } > /* > - * DSI ports should have their DDI clock ungated when disabled > - * and gated when enabled. > + * For MIPI DSI we unagate the clocks later as part of > + * enable sequence. Keep them gated by default. > */ > - ddi_clk_needed = !encoder->base.crtc; > + ddi_clk_needed = false; Should that be true? > } > > val = I915_READ(DPCLKA_CFGCR0_ICL); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi 2019-03-22 14:32 ` Ville Syrjälä @ 2019-03-22 15:37 ` Kulkarni, Vandita 2019-03-22 15:56 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Kulkarni, Vandita @ 2019-03-22 15:37 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, March 22, 2019 8:02 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi- > dsi > > On Fri, Mar 22, 2019 at 05:43:52PM +0530, Vandita Kulkarni wrote: > > Re-enable clock gating of DDI clocks. > > > > v2: Fix the default ddi clk state for mipi-dsi (Imre) > > > > Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/icl_dsi.c | 2 +- > > drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- > > 2 files changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > b/drivers/gpu/drm/i915/icl_dsi.c index 6a5b9fa..5caf41f 100644 > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > @@ -1124,7 +1124,7 @@ static void gen11_dsi_disable_port(struct > intel_encoder *encoder) > > DRM_ERROR("DDI port:%c buffer not idle\n", > > port_name(port)); > > } > > - gen11_dsi_ungate_clocks(encoder); > > + gen11_dsi_gate_clocks(encoder); > > } > > > > static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 933df3a..17a03fa 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct > intel_encoder *encoder) > > return; > > } > > /* > > - * DSI ports should have their DDI clock ungated when disabled > > - * and gated when enabled. > > + * For MIPI DSI we unagate the clocks later as part of > > + * enable sequence. Keep them gated by default. > > */ > > - ddi_clk_needed = !encoder->base.crtc; > > + ddi_clk_needed = false; > > Should that be true? No. False. We are comparing ddi_clk_needed with clock ungated which is false for mipi dsi. So we do nothing in this function if it is already gated, and gate it if we have ungated = true. Regards, Vandita > > > } > > > > val = I915_READ(DPCLKA_CFGCR0_ICL); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi 2019-03-22 15:37 ` Kulkarni, Vandita @ 2019-03-22 15:56 ` Ville Syrjälä 2019-03-25 5:41 ` Kulkarni, Vandita 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2019-03-22 15:56 UTC (permalink / raw) To: Kulkarni, Vandita; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org On Fri, Mar 22, 2019 at 03:37:35PM +0000, Kulkarni, Vandita wrote: > > > > -----Original Message----- > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Sent: Friday, March 22, 2019 8:02 PM > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > > Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi- > > dsi > > > > On Fri, Mar 22, 2019 at 05:43:52PM +0530, Vandita Kulkarni wrote: > > > Re-enable clock gating of DDI clocks. > > > > > > v2: Fix the default ddi clk state for mipi-dsi (Imre) > > > > > > Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > > --- > > > drivers/gpu/drm/i915/icl_dsi.c | 2 +- > > > drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- > > > 2 files changed, 4 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > > b/drivers/gpu/drm/i915/icl_dsi.c index 6a5b9fa..5caf41f 100644 > > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > > @@ -1124,7 +1124,7 @@ static void gen11_dsi_disable_port(struct > > intel_encoder *encoder) > > > DRM_ERROR("DDI port:%c buffer not idle\n", > > > port_name(port)); > > > } > > > - gen11_dsi_ungate_clocks(encoder); > > > + gen11_dsi_gate_clocks(encoder); > > > } > > > > > > static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index 933df3a..17a03fa 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct > > intel_encoder *encoder) > > > return; > > > } > > > /* > > > - * DSI ports should have their DDI clock ungated when disabled > > > - * and gated when enabled. > > > + * For MIPI DSI we unagate the clocks later as part of > > > + * enable sequence. Keep them gated by default. > > > */ > > > - ddi_clk_needed = !encoder->base.crtc; > > > + ddi_clk_needed = false; > > > > Should that be true? > No. False. > We are comparing ddi_clk_needed with clock ungated which is false for mipi dsi. > So we do nothing in this function if it is already gated, and gate it if we have ungated = true. The comment is confusing me. Should it be something more like this? /* * With DSI the clocks are always gated * except during the enable/disable sequence. */ > > Regards, > Vandita > > > > > > } > > > > > > val = I915_READ(DPCLKA_CFGCR0_ICL); > > > -- > > > 1.9.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi 2019-03-22 15:56 ` Ville Syrjälä @ 2019-03-25 5:41 ` Kulkarni, Vandita 0 siblings, 0 replies; 10+ messages in thread From: Kulkarni, Vandita @ 2019-03-25 5:41 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, March 22, 2019 9:27 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi- > dsi > > On Fri, Mar 22, 2019 at 03:37:35PM +0000, Kulkarni, Vandita wrote: > > > > > > > -----Original Message----- > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Sent: Friday, March 22, 2019 8:02 PM > > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani > > > <jani.nikula@intel.com> > > > Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable > > > sequence for mipi- dsi > > > > > > On Fri, Mar 22, 2019 at 05:43:52PM +0530, Vandita Kulkarni wrote: > > > > Re-enable clock gating of DDI clocks. > > > > > > > > v2: Fix the default ddi clk state for mipi-dsi (Imre) > > > > > > > > Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/icl_dsi.c | 2 +- > > > > drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- > > > > 2 files changed, 4 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > > > b/drivers/gpu/drm/i915/icl_dsi.c index 6a5b9fa..5caf41f 100644 > > > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > > > @@ -1124,7 +1124,7 @@ static void gen11_dsi_disable_port(struct > > > intel_encoder *encoder) > > > > DRM_ERROR("DDI port:%c buffer not idle\n", > > > > port_name(port)); > > > > } > > > > - gen11_dsi_ungate_clocks(encoder); > > > > + gen11_dsi_gate_clocks(encoder); > > > > } > > > > > > > > static void gen11_dsi_disable_io_power(struct intel_encoder > > > > *encoder) diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > > index 933df3a..17a03fa 100644 > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > > @@ -2821,10 +2821,10 @@ void > > > > icl_sanitize_encoder_pll_mapping(struct > > > intel_encoder *encoder) > > > > return; > > > > } > > > > /* > > > > - * DSI ports should have their DDI clock ungated when disabled > > > > - * and gated when enabled. > > > > + * For MIPI DSI we unagate the clocks later as part of > > > > + * enable sequence. Keep them gated by default. > > > > */ > > > > - ddi_clk_needed = !encoder->base.crtc; > > > > + ddi_clk_needed = false; > > > > > > Should that be true? > > No. False. > > We are comparing ddi_clk_needed with clock ungated which is false for mipi > dsi. > > So we do nothing in this function if it is already gated, and gate it if we have > ungated = true. > > The comment is confusing me. Should it be something more like this? > > /* > * With DSI the clocks are always gated > * except during the enable/disable sequence. > */ > For DSI, we keep the DDI clocks gated, except during the enable/disable sequence. I will update the same. Thanks, Vandita > > > > Regards, > > Vandita > > > > > > > > > } > > > > > > > > val = I915_READ(DPCLKA_CFGCR0_ICL); > > > > -- > > > > 1.9.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Ville Syrjälä > > > Intel > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable 2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni 2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni @ 2019-03-22 13:45 ` Patchwork 2019-03-22 14:33 ` [v2 1/2] " Ville Syrjälä 2019-03-23 11:01 ` ✓ Fi.CI.IGT: success for series starting with [v2,1/2] " Patchwork 3 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-03-22 13:45 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable URL : https://patchwork.freedesktop.org/series/58408/ State : success == Summary == CI Bug Log - changes from CI_DRM_5794 -> Patchwork_12573 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58408/revisions/1/mbox/ Known issues ------------ Here are the changes found in Patchwork_12573 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@gtt-bsd: - fi-bwr-2160: NOTRUN -> SKIP [fdo#109271] +103 * igt@gem_exec_basic@gtt-bsd1: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@gem_exec_basic@gtt-bsd2: - fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9 * igt@gem_exec_basic@readonly-bsd: - fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-bwr-2160: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841] * igt@kms_chamelium@dp-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52 * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@runner@aborted: - fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841] #### Possible fixes #### * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 Participating hosts (32 -> 32) ------------------------------ Additional (7): fi-hsw-4770r fi-byt-j1900 fi-icl-u2 fi-bwr-2160 fi-kbl-7500u fi-bxt-j4205 fi-pnv-d510 Missing (7): fi-bsw-n3050 fi-hsw-4200u fi-ctg-p8600 fi-hsw-4770 fi-gdg-551 fi-byt-n2820 fi-skl-6700k2 Build changes ------------- * Linux: CI_DRM_5794 -> Patchwork_12573 CI_DRM_5794: 487d6c295c12d99c218b489ab39618831d7d31d6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4898: be2f88cd36fd4ba836d9f2453e90673c86649489 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12573: 2004974083969c5dd4765a27f5be3ea1f7c1c523 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 200497408396 drm/i915/icl: Fix port disable sequence for mipi-dsi 357d05936372 drm/i915/icl: Ungate ddi clocks before IO enable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12573/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable 2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni 2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni 2019-03-22 13:45 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork @ 2019-03-22 14:33 ` Ville Syrjälä 2019-03-22 15:33 ` Kulkarni, Vandita 2019-03-23 11:01 ` ✓ Fi.CI.IGT: success for series starting with [v2,1/2] " Patchwork 3 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2019-03-22 14:33 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: jani.nikula, intel-gfx On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote: > IO enable sequencing needs ddi clocks enabled. > These clocks will be gated at a later point in > the enable sequence. > > v2: Fix the commit header (uma) > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index beb30d9..6a5b9fa 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); > } > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > + val = I915_READ(DPCLKA_CFGCR0_ICL); This read looks totally redundant. > + for_each_dsi_port(port, intel_dsi->ports) { > + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > + } > + I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > POSTING_READ(DPCLKA_CFGCR0_ICL); > > mutex_unlock(&dev_priv->dpll_lock); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable 2019-03-22 14:33 ` [v2 1/2] " Ville Syrjälä @ 2019-03-22 15:33 ` Kulkarni, Vandita 0 siblings, 0 replies; 10+ messages in thread From: Kulkarni, Vandita @ 2019-03-22 15:33 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, March 22, 2019 8:03 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > Subject: Re: [Intel-gfx] [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable > > On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote: > > IO enable sequencing needs ddi clocks enabled. > > These clocks will be gated at a later point in the enable sequence. > > > > v2: Fix the commit header (uma) > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..6a5b9fa 100644 > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder > *encoder, > > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); > > } > > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > + > > + val = I915_READ(DPCLKA_CFGCR0_ICL); > > This read looks totally redundant. Yes, it should have written what is in val already. thanks for the review. Will remove it. Regards, Vandita > > > + for_each_dsi_port(port, intel_dsi->ports) { > > + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > > + } > > + I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > + > > POSTING_READ(DPCLKA_CFGCR0_ICL); > > > > mutex_unlock(&dev_priv->dpll_lock); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable 2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni ` (2 preceding siblings ...) 2019-03-22 14:33 ` [v2 1/2] " Ville Syrjälä @ 2019-03-23 11:01 ` Patchwork 3 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-03-23 11:01 UTC (permalink / raw) To: Kulkarni, Vandita; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable URL : https://patchwork.freedesktop.org/series/58408/ State : success == Summary == CI Bug Log - changes from CI_DRM_5794_full -> Patchwork_12573_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_12573_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_busy@busy-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +6 * igt@gem_ctx_param@invalid-param-get: - shard-skl: NOTRUN -> FAIL [fdo#109559] * igt@gem_ctx_param@invalid-param-set: - shard-snb: NOTRUN -> FAIL [fdo#109674] * igt@gem_ctx_sseu@invalid-args: - shard-skl: NOTRUN -> SKIP [fdo#109271] +79 * igt@gem_exec_parse@chained-batch: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-iclb: PASS -> INCOMPLETE [fdo#109801] * igt@gem_pwrite@stolen-normal: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait: - shard-snb: NOTRUN -> SKIP [fdo#109271] +137 * igt@i915_pm_rpm@universal-planes-dpms: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@3x-modeset-transitions-fencing: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +4 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_chamelium@hdmi-cmp-yv16: - shard-iclb: NOTRUN -> SKIP [fdo#109284] * igt@kms_color@pipe-a-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] * igt@kms_cursor_crc@cursor-64x21-random: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +4 * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_fbcon_fbt@fbc: - shard-iclb: PASS -> DMESG-WARN [fdo#109593] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_force_connector_basic@force-load-detect: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +6 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +14 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +17 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1 * igt@kms_frontbuffer_tracking@fbcpsr-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +17 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +4 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8 * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] * igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: - shard-glk: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_basic: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_psr@psr2_no_drrs: - shard-iclb: NOTRUN -> SKIP [fdo#109441] +1 * igt@kms_psr@sprite_plane_move: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +1 * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> FAIL [fdo#109016] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] * igt@prime_nv_pcopy@test2: - shard-iclb: NOTRUN -> SKIP [fdo#109291] +1 * igt@prime_vgem@sync-bsd1: - shard-glk: NOTRUN -> SKIP [fdo#109271] +17 * igt@runner@aborted: - shard-iclb: NOTRUN -> FAIL [fdo#109593] #### Possible fixes #### * igt@gem_exec_parallel@default-contexts: - shard-snb: INCOMPLETE [fdo#105411] -> PASS * igt@gem_partial_pwrite_pread@writes-after-reads-display: - shard-iclb: TIMEOUT [fdo#109673] -> PASS * igt@gem_tiled_fence_blits@normal: - shard-snb: FAIL -> PASS * igt@i915_pm_rpm@system-suspend: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107807] -> PASS * igt@i915_suspend@forcewake: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-snb: DMESG-WARN [fdo#110222] -> PASS * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: FAIL [fdo#103355] -> PASS * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-skl: FAIL [fdo#108472] -> PASS * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled: - shard-skl: FAIL [fdo#107791] -> PASS * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-glk: FAIL [fdo#103060] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: FAIL [fdo#103167] -> PASS +7 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-iclb: FAIL [fdo#109247] -> PASS +10 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu: - shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1 * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: SKIP [fdo#109441] -> PASS +3 * igt@kms_psr@sprite_mmap_cpu: - shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: DMESG-FAIL [fdo#105763] -> PASS * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: FAIL [fdo#109016] -> PASS {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682 [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683 [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472 [fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590 [fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597 [fdo#108739]: https://bugs.freedesktop.org/show_bug.cgi?id=108739 [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954 [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016 [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109288]: https://bugs.freedesktop.org/show_bug.cgi?id=109288 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559 [fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673 [fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674 [fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801 [fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215 [fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 9) ------------------------------ Missing (1): shard-hsw Build changes ------------- * Linux: CI_DRM_5794 -> Patchwork_12573 CI_DRM_5794: 487d6c295c12d99c218b489ab39618831d7d31d6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4898: be2f88cd36fd4ba836d9f2453e90673c86649489 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12573: 2004974083969c5dd4765a27f5be3ea1f7c1c523 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12573/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-03-25 5:41 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-03-22 12:13 [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni 2019-03-22 12:13 ` [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni 2019-03-22 14:32 ` Ville Syrjälä 2019-03-22 15:37 ` Kulkarni, Vandita 2019-03-22 15:56 ` Ville Syrjälä 2019-03-25 5:41 ` Kulkarni, Vandita 2019-03-22 13:45 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork 2019-03-22 14:33 ` [v2 1/2] " Ville Syrjälä 2019-03-22 15:33 ` Kulkarni, Vandita 2019-03-23 11:01 ` ✓ Fi.CI.IGT: success for series starting with [v2,1/2] " Patchwork
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