Re: [PATCH 2/2] drm/i915: Clean up DSC vs. not bpp handling

[Manasi Navare <manasi.d.navare@intel.com>]

On Tue, Mar 26, 2019 at 04:49:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No point in duplicating all this code when we can just
> use a variable top hold the output bpp (the only thing
> that differs between the two branches).
> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.comk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This clean up looks good, thank you for catching this and cleaning it up.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++---------------
>  1 file changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bbf678561509..b26007a32318 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2126,7 +2126,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  		to_intel_digital_connector_state(conn_state);
>  	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
>  					   DP_DPCD_QUIRK_CONSTANT_N);
> -	int ret;
> +	int ret, output_bpp;
>  
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
>  		pipe_config->has_pch_encoder = true;
> @@ -2190,25 +2190,22 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
>  	}
>  
> -	if (!pipe_config->dsc_params.compression_enable)
> -		intel_link_compute_m_n(pipe_config->pipe_bpp,
> -				       pipe_config->lane_count,
> -				       adjusted_mode->crtc_clock,
> -				       pipe_config->port_clock,
> -				       &pipe_config->dp_m_n,
> -				       constant_n);
> +	if (pipe_config->dsc_params.compression_enable)
> +		output_bpp = pipe_config->dsc_params.compressed_bpp;
>  	else
> -		intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
> -				       pipe_config->lane_count,
> -				       adjusted_mode->crtc_clock,
> -				       pipe_config->port_clock,
> -				       &pipe_config->dp_m_n,
> -				       constant_n);
> +		output_bpp = pipe_config->pipe_bpp;
> +
> +	intel_link_compute_m_n(output_bpp,
> +			       pipe_config->lane_count,
> +			       adjusted_mode->crtc_clock,
> +			       pipe_config->port_clock,
> +			       &pipe_config->dp_m_n,
> +			       constant_n);
>  
>  	if (intel_connector->panel.downclock_mode != NULL &&
>  		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
>  			pipe_config->has_drrs = true;
> -			intel_link_compute_m_n(pipe_config->pipe_bpp,
> +			intel_link_compute_m_n(output_bpp,
>  					       pipe_config->lane_count,
>  					       intel_connector->panel.downclock_mode->clock,
>  					       pipe_config->port_clock,
> -- 
> 2.19.2
> 
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