Re: [PATCH 1/3] drm/i915/icl: fix step numbers in icl_display_core_init()

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Apr 04, 2019 at 04:04:24PM -0700, Lucas De Marchi wrote:
> At some point the spec was changed and we never updated the numbers to
> match it. Let's try once more to keep them in sync.

or maybe we just copied the numers from CNL ones?

Anyway let's keep in sync with spec:


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 40ddfbb97acb..25053dfc3a12 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3832,11 +3832,11 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	/* 1. Enable PCH reset handshake. */
>  	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>  
> -	/* 2-3. */
> +	/* 2. Initialize all combo phys */
>  	icl_combo_phys_init(dev_priv);
>  
>  	/*
> -	 * 4. Enable Power Well 1 (PG1).
> +	 * 3. Enable Power Well 1 (PG1).
>  	 *    The AUX IO power wells will be enabled on demand.
>  	 */
>  	mutex_lock(&power_domains->lock);
> @@ -3844,13 +3844,13 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	intel_power_well_enable(dev_priv, well);
>  	mutex_unlock(&power_domains->lock);
>  
> -	/* 5. Enable CDCLK. */
> +	/* 4. Enable CDCLK. */
>  	icl_init_cdclk(dev_priv);
>  
> -	/* 6. Enable DBUF. */
> +	/* 5. Enable DBUF. */
>  	icl_dbuf_enable(dev_priv);
>  
> -	/* 7. Setup MBUS. */
> +	/* 6. Setup MBUS. */
>  	icl_mbus_init(dev_priv);
>  
>  	if (resume && dev_priv->csr.dmc_payload)
> -- 
> 2.21.0
> 
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