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From: Dongwon Kim <dongwon.kim@intel.com>
To: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk
Cc: Dongwon Kim <dongwon.kim@intel.com>
Subject: [PATCH v3] drm/i915/gen11: enable support for headerless msgs
Date: Wed, 24 Apr 2019 14:02:39 -0700	[thread overview]
Message-ID: <20190424210239.31902-1-dongwon.kim@intel.com> (raw)
In-Reply-To: <20190423190503.32583-1-dongwon.kim@intel.com>

Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of message
- headerless and w/ header supported at the same time. It also complies with
the new recommendation for the default bit value for the next gen.

v2: rewrote commit message to include more information
v3: setting the bit in icl_ctx_workarounds_init()

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..b45042f71c0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8862,6 +8862,7 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
 
 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+#define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	(1 << 5)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b3cbed1ee1c9..58ddb60772b3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -575,6 +575,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
 	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+
+	/* allow headerless messages for preemptable GPGPU context */
+	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
+			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 }
 
 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
-- 
2.17.1

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  parent reply	other threads:[~2019-04-24 21:06 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-23 19:05 [PATCH] drm/i915/gen11: enable support for headerless msgs Dongwon Kim
2019-04-23 19:32 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-04-23 19:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-23 19:59 ` [PATCH] " Chris Wilson
2019-04-23 22:55 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-04-24 20:38 ` [PATCH] " Dongwon Kim
2019-04-24 20:43   ` Chris Wilson
2019-04-24 21:02 ` Dongwon Kim [this message]
2019-04-25  5:50   ` Chris Wilson
2019-05-24  8:03     ` Mika Kuoppala
2019-05-24  9:07       ` Chris Wilson
2019-04-25  7:31 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen11: enable support for headerless msgs (rev4) Patchwork
2019-04-25  7:54 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-05-06 20:27   ` Dongwon Kim
2019-05-08  6:41     ` Peres, Martin
2019-05-23 21:13       ` Dongwon Kim

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