* [PATCH 0/4] Refactor to expand subslice mask
@ 2019-04-19 0:00 Stuart Summers
2019-04-19 0:00 ` [PATCH 1/4] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw)
To: intel-gfx
This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
slice * subslice stride + subslice index / 8
Stuart Summers (4):
drm/i915: Use local variable for SSEU info in GETPARAM ioctl
drm/i915: Add macro for SSEU stride calculation
drm/i915: Move calculation of subslices per slice to new function
drm/i915: Expand subslice mask
drivers/gpu/drm/i915/i915_debugfs.c | 46 ++++---
drivers/gpu/drm/i915/i915_drv.c | 15 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 15 +--
drivers/gpu/drm/i915/intel_device_info.c | 154 +++++++++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 52 ++++++--
drivers/gpu/drm/i915/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/intel_engine_types.h | 32 ++---
drivers/gpu/drm/i915/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
10 files changed, 203 insertions(+), 127 deletions(-)
--
2.21.0.5.gaeb582a983
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/4] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
@ 2019-04-19 0:00 ` Stuart Summers
2019-04-19 0:00 ` [PATCH 2/4] drm/i915: Add macro for SSEU stride calculation Stuart Summers
` (7 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw)
To: intel-gfx
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ad88e6d7c04..83339beb9e80 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -319,6 +319,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -372,12 +373,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -394,7 +395,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(&dev_priv->huc);
@@ -444,12 +445,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] drm/i915: Add macro for SSEU stride calculation
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
2019-04-19 0:00 ` [PATCH 1/4] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
@ 2019-04-19 0:00 ` Stuart Summers
2019-04-19 0:00 ` [PATCH 3/4] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
` (6 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw)
To: intel-gfx
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_query.c | 17 ++++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length + eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(&topo, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0e579f158016..5d90639881d8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -141,6 +141,7 @@ enum intel_ppgtt_type {
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
struct sseu_dev_info {
u8 slice_mask;
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/4] drm/i915: Move calculation of subslices per slice to new function
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
2019-04-19 0:00 ` [PATCH 1/4] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
2019-04-19 0:00 ` [PATCH 2/4] drm/i915: Add macro for SSEU stride calculation Stuart Summers
@ 2019-04-19 0:00 ` Stuart Summers
2019-04-19 0:00 ` [PATCH 4/4] drm/i915: Expand subslice mask Stuart Summers
` (5 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h | 6 ++++++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..19746249d57b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4191,7 +4191,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 5d90639881d8..987e0ca6f9cc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -252,6 +252,12 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
int slice, int subslice)
{
--
2.21.0.5.gaeb582a983
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/4] drm/i915: Expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (2 preceding siblings ...)
2019-04-19 0:00 ` [PATCH 3/4] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
@ 2019-04-19 0:00 ` Stuart Summers
2019-04-19 0:07 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand " Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 44 ++++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 150 +++++++++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 47 +++++--
drivers/gpu/drm/i915/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/intel_engine_types.h | 32 ++---
drivers/gpu/drm/i915/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
10 files changed, 187 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 19746249d57b..28a5fbd405ad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1250,6 +1250,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1265,11 +1266,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
@@ -4072,7 +4073,9 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -4123,18 +4126,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4151,25 +4158,24 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
- }
+ sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4216,6 +4222,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -4223,14 +4230,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ sseu.max_slices = info->sseu.max_slices;
+ sseu.max_subslices = info->sseu.max_subslices;
+ sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
with_intel_runtime_pm(dev_priv, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 83339beb9e80..82731961f485 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
- int value;
+ int value = 0;
switch (param->param) {
case I915_PARAM_IRQ_ACTIVE:
@@ -450,7 +450,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = sseu->subslice_mask[0];
+ /* Only copy bits from the first subslice */
+ memcpy(&value, sseu->subslice_mask,
+ min(sseu->ss_stride, (u8)sizeof(value)));
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index f51ff683dd2e..9da4118ad43a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -405,6 +405,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -420,12 +421,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7c1708c22811..000dcb145ce0 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,8 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,8 +48,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,9 +67,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 559cf0d0628e..af3a547a6716 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -84,17 +84,42 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
#undef PRINT_FLAG
}
+#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
+
+static u8 *
+subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i;
+ u8 ss_offset = slice * sseu->ss_stride;
+
+ GEM_BUG_ON(slice >= sseu->max_slices);
+
+ memset(buf, 0, SS_STR_MAX_SIZE);
+
+ /*
+ * Print subslice information in reverse order to match
+ * userspace expectations.
+ */
+ for (i = 0; i < sseu->ss_stride; i++)
+ sprintf(&buf[i * 2], "%02x",
+ sseu->subslice_mask[ss_offset + sseu->ss_stride -
+ (i + 1)]);
+
+ return buf;
+}
+
static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
+ u8 buf[SS_STR_MAX_SIZE];
drm_printf(p, "slice total: %u, mask=%04x\n",
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%s\n",
s, sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
int s, ss;
+ u8 buf[SS_STR_MAX_SIZE];
if (sseu->max_slices == 0) {
drm_printf(p, "Unavailable\n");
@@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
s, sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -148,6 +174,17 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
+static void set_sseu_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+}
+
static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
@@ -156,15 +193,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ set_sseu_info(sseu, 1, 4, 8);
+ else
+ set_sseu_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -177,9 +209,11 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+ sseu->subslice_mask[s * sseu->ss_stride] =
+ (ss_en >> ss_idx) & ss_en_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ if (sseu->subslice_mask[s * sseu->ss_stride] &
+ BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
}
}
@@ -201,23 +235,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ set_sseu_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
-
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
@@ -242,14 +263,22 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ sseu_set_subslices(sseu, s, s == 0 ? subslice_mask :
+ subslice_mask & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -274,13 +303,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask;
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -289,7 +317,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -300,10 +328,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ sseu_set_subslices(sseu, 0, subslice_mask);
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -335,9 +365,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -356,14 +385,16 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
int eu_per_ss;
u8 eu_disabled_mask;
+ u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!(sseu->subslice_mask[ss_idx] &
+ BIT(ss % BITS_PER_BYTE)))
/* skip disabled subslice */
continue;
@@ -435,9 +466,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -464,18 +493,21 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
+ u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!(sseu->subslice_mask[ss_idx] &
+ BIT(ss % BITS_PER_BYTE)))
/* skip disabled subslice */
continue;
eu_disabled_mask =
- eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
+ eu_disable[s] >>
+ (ss * sseu->max_eus_per_subslice);
sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
@@ -514,6 +546,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
int s, ss;
+ u32 subslice_mask;
/*
* There isn't a register to tell us how many slices/subslices. We
@@ -525,22 +558,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -557,9 +586,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ set_sseu_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(subslice_mask),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ sseu_set_subslices(sseu, s, subslice_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 987e0ca6f9cc..1cf622031aa7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -142,10 +142,11 @@ enum intel_ppgtt_type {
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -160,6 +161,9 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+ u8 eu_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
@@ -255,17 +259,40 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ unsigned int i, total = 0;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ total += hweight8(sseu->subslice_mask[slice * sseu->ss_stride +
+ i]);
+
+ return total;
+}
+
+static inline void sseu_copy_subslices(const struct sseu_dev_info *sseu,
+ int slice, u8 *to_mask,
+ const u8 *from_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride);
+}
+
+static inline void sseu_set_subslices(struct sseu_dev_info *sseu,
+ int slice, u32 ss_mask)
+{
+ int i, offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
int slice, int subslice)
{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
- return slice * slice_stride + subslice * subslice_stride;
+ return slice * slice_stride + subslice * sseu->eu_stride;
}
static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
@@ -274,11 +301,9 @@ static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
- for (i = 0;
- i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ for (i = 0; i < sseu->eu_stride; i++)
eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
- }
return eu_mask;
}
@@ -288,11 +313,9 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
{
int i, offset = sseu_eu_idx(sseu, slice, subslice);
- for (i = 0;
- i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ for (i = 0; i < sseu->eu_stride; i++)
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
}
const char *intel_platform_name(enum intel_platform platform);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index eea9bec04f1b..6e0efb61ee41 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -886,7 +886,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -962,6 +962,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -979,7 +980,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+ subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h
index 1f970c76b6a6..02150d2f301e 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -527,20 +527,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv__, sseu__, slice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->slice_mask) & \
+ BIT(slice__)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 3d51ed1428d4..8d9504f083a6 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -50,6 +50,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b3cbed1ee1c9..e8ddd56905db 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -771,7 +771,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
u32 slice = fls(sseu->slice_mask);
u32 fuse3 =
intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
- u8 ss_mask = sseu->subslice_mask[slice];
+ u8 ss_mask = sseu->subslice_mask[slice * sseu->ss_stride];
u8 enabled_mask = (ss_mask | ss_mask >>
GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (3 preceding siblings ...)
2019-04-19 0:00 ` [PATCH 4/4] drm/i915: Expand subslice mask Stuart Summers
@ 2019-04-19 0:07 ` Patchwork
2019-04-19 0:09 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-04-19 0:07 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c768f68e461e drm/i915: Use local variable for SSEU info in GETPARAM ioctl
d85bb21514db drm/i915: Add macro for SSEU stride calculation
55c847acc9c8 drm/i915: Move calculation of subslices per slice to new function
79c37be2a181 drm/i915: Expand subslice mask
-:300: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#300: FILE: drivers/gpu/drm/i915/intel_device_info.c:178:
+static void set_sseu_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
-:714: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu__' - possible side-effects?
#714: FILE: drivers/gpu/drm/i915/intel_engine_types.h:535:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
-:714: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slice__' may be better as '(slice__)' to avoid precedence issues
#714: FILE: drivers/gpu/drm/i915/intel_engine_types.h:535:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
-:714: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#714: FILE: drivers/gpu/drm/i915/intel_engine_types.h:535:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
-:714: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'subslice__' may be better as '(subslice__)' to avoid precedence issues
#714: FILE: drivers/gpu/drm/i915/intel_engine_types.h:535:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
-:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#720: FILE: drivers/gpu/drm/i915/intel_engine_types.h:541:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
-:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#720: FILE: drivers/gpu/drm/i915/intel_engine_types.h:541:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
-:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#720: FILE: drivers/gpu/drm/i915/intel_engine_types.h:541:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
-:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#720: FILE: drivers/gpu/drm/i915/intel_engine_types.h:541:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
total: 0 errors, 0 warnings, 9 checks, 662 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (4 preceding siblings ...)
2019-04-19 0:07 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand " Patchwork
@ 2019-04-19 0:09 ` Patchwork
2019-04-19 0:28 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-04-19 0:09 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl
Okay!
Commit: drm/i915: Add macro for SSEU stride calculation
Okay!
Commit: drm/i915: Move calculation of subslices per slice to new function
Okay!
Commit: drm/i915: Expand subslice mask
+drivers/gpu/drm/i915/i915_drv.c:455:24: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (5 preceding siblings ...)
2019-04-19 0:09 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-04-19 0:28 ` Patchwork
2019-04-19 3:44 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-04-19 0:28 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask
URL : https://patchwork.freedesktop.org/series/59742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5954 -> Patchwork_12839
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59742/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12839 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@readonly-bsd1:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +3
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770: PASS -> SKIP [fdo#109271] +2
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@force-edid:
- fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-glk-dsi: NOTRUN -> FAIL [fdo#103167]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@gem_exec_basic@readonly-bsd:
- fi-icl-u2: INCOMPLETE [fdo#107713] -> PASS
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (48 -> 39)
------------------------------
Additional (1): fi-bxt-j4205
Missing (10): fi-ilk-m540 fi-hsw-peppy fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-gdg-551 fi-icl-y fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5954 -> Patchwork_12839
CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12839: 79c37be2a1819f13c21dba67ae2a61706c84e146 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
79c37be2a181 drm/i915: Expand subslice mask
55c847acc9c8 drm/i915: Move calculation of subslices per slice to new function
d85bb21514db drm/i915: Add macro for SSEU stride calculation
c768f68e461e drm/i915: Use local variable for SSEU info in GETPARAM ioctl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12839/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (6 preceding siblings ...)
2019-04-19 0:28 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-19 3:44 ` Patchwork
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-04-19 3:44 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask
URL : https://patchwork.freedesktop.org/series/59742/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12839_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12839_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12839_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12839_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_sseu@full-enable:
- shard-apl: PASS -> FAIL
- shard-kbl: PASS -> FAIL
- shard-glk: PASS -> FAIL
- shard-skl: PASS -> FAIL
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity-after-suspend}:
- shard-glk: TIMEOUT -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12839_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_workarounds@suspend-resume:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#108566]
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +2
* igt@i915_pm_rpm@i2c:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#107807]
* igt@kms_atomic_transition@5x-modeset-transitions:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7
* igt@kms_busy@basic-flip-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#106509] / [fdo#107409]
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: PASS -> SKIP [fdo#109349]
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-skl: NOTRUN -> FAIL [fdo#103184]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363] +1
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-skl: NOTRUN -> FAIL [fdo#108228] / [fdo#108303]
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +19
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-iclb: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +76
* igt@kms_lease@setcrtc_implicit_plane:
- shard-snb: NOTRUN -> FAIL [fdo#110281]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] / [fdo#110403]
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@suspend:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107773]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +97
* igt@perf_pmu@rc6:
- shard-kbl: PASS -> SKIP [fdo#109271]
#### Possible fixes ####
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +3
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: FAIL [fdo#100368] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> PASS +8
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: SKIP [fdo#109441] -> PASS +3
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5954 -> Patchwork_12839
CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12839: 79c37be2a1819f13c21dba67ae2a61706c84e146 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12839/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
` (7 preceding siblings ...)
2019-04-19 3:44 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-04-25 16:28 ` Stuart Summers
2019-04-25 16:29 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
` (4 more replies)
8 siblings, 5 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:28 UTC (permalink / raw)
To: intel-gfx
This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
slice * subslice stride + subslice index / 8
v2: fix i915_pm_sseu test failure
Stuart Summers (5):
drm/i915: Use local variable for SSEU info in GETPARAM ioctl
drm/i915: Add macro for SSEU stride calculation
drm/i915: Move calculation of subslices per slice to new function
drm/i915: Move sseu helper functions to intel_sseu.h
drm/i915: Expand subslice mask
drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++---
drivers/gpu/drm/i915/i915_drv.c | 15 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 15 +--
drivers/gpu/drm/i915/intel_device_info.c | 143 +++++++++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 47 -------
drivers/gpu/drm/i915/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/intel_engine_types.h | 32 ++---
drivers/gpu/drm/i915/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/intel_sseu.h | 96 ++++++++++++++-
drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
11 files changed, 245 insertions(+), 164 deletions(-)
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
@ 2019-04-25 16:29 ` Stuart Summers
2019-04-25 16:29 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:29 UTC (permalink / raw)
To: intel-gfx
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6354c68c94b3..27021a7546a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -319,6 +319,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -372,12 +373,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -394,7 +395,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(&dev_priv->huc);
@@ -444,12 +445,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
2019-04-25 16:29 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
@ 2019-04-25 16:29 ` Stuart Summers
2019-04-25 16:29 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
` (2 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:29 UTC (permalink / raw)
To: intel-gfx
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_query.c | 17 ++++++++---------
drivers/gpu/drm/i915/intel_sseu.h | 1 +
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length + eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(&topo, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/intel_sseu.h
index 73bc824094e8..2cbf0981b44f 100644
--- a/drivers/gpu/drm/i915/intel_sseu.h
+++ b/drivers/gpu/drm/i915/intel_sseu.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
struct sseu_dev_info {
u8 slice_mask;
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
2019-04-25 16:29 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
2019-04-25 16:29 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers
@ 2019-04-25 16:29 ` Stuart Summers
2019-04-25 16:29 ` [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h Stuart Summers
2019-04-25 16:29 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers
4 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:29 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
drivers/gpu/drm/i915/intel_sseu.h | 6 ++++++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..19746249d57b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4191,7 +4191,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/intel_sseu.h
index 2cbf0981b44f..b553d7280f35 100644
--- a/drivers/gpu/drm/i915/intel_sseu.h
+++ b/drivers/gpu/drm/i915/intel_sseu.h
@@ -62,6 +62,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
` (2 preceding siblings ...)
2019-04-25 16:29 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
@ 2019-04-25 16:29 ` Stuart Summers
2019-04-25 16:29 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers
4 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:29 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.h | 47 ------------------------
drivers/gpu/drm/i915/intel_sseu.h | 47 ++++++++++++++++++++++++
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 1598c7079ffd..4862770136a5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -216,53 +216,6 @@ struct intel_driver_caps {
bool has_logical_contexts:1;
};
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
- i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
- i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/intel_sseu.h
index b553d7280f35..0dfbed547da5 100644
--- a/drivers/gpu/drm/i915/intel_sseu.h
+++ b/drivers/gpu/drm/i915/intel_sseu.h
@@ -62,12 +62,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
return hweight8(sseu->subslice_mask[slice]);
}
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+ i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+ int slice, int subslice, u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+ i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
--
2.21.0.5.gaeb582a983
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/5] drm/i915: Expand subslice mask
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
` (3 preceding siblings ...)
2019-04-25 16:29 ` [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h Stuart Summers
@ 2019-04-25 16:29 ` Stuart Summers
4 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 16:29 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 139 +++++++++++++---------
drivers/gpu/drm/i915/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/intel_engine_types.h | 32 ++---
drivers/gpu/drm/i915/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/intel_sseu.h | 44 ++++++-
drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
10 files changed, 182 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 19746249d57b..9bd304b83de3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1250,6 +1250,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1265,11 +1266,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
@@ -4072,7 +4073,9 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -4123,18 +4126,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4151,25 +4158,24 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
- }
+ sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask,
+ info->sseu.subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4216,6 +4222,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -4223,14 +4230,12 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ set_sseu_info(&sseu, info->sseu.max_slices, info->sseu.max_subslices,
+ info->sseu.max_eus_per_subslice);
with_intel_runtime_pm(dev_priv, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 27021a7546a2..a4525cb5fd28 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
- int value;
+ int value = 0;
switch (param->param) {
case I915_PARAM_IRQ_ACTIVE:
@@ -450,7 +450,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = sseu->subslice_mask[0];
+ /* Only copy bits from the first subslice */
+ memcpy(&value, sseu->subslice_mask,
+ min(sseu->ss_stride, (u8)sizeof(value)));
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index f51ff683dd2e..9da4118ad43a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -405,6 +405,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -420,12 +421,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7c1708c22811..000dcb145ce0 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,8 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,8 +48,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,9 +67,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 559cf0d0628e..1cc72beb86ee 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -84,17 +84,42 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
#undef PRINT_FLAG
}
+#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
+
+static u8 *
+subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i;
+ u8 ss_offset = slice * sseu->ss_stride;
+
+ GEM_BUG_ON(slice >= sseu->max_slices);
+
+ memset(buf, 0, SS_STR_MAX_SIZE);
+
+ /*
+ * Print subslice information in reverse order to match
+ * userspace expectations.
+ */
+ for (i = 0; i < sseu->ss_stride; i++)
+ sprintf(&buf[i * 2], "%02x",
+ sseu->subslice_mask[ss_offset + sseu->ss_stride -
+ (i + 1)]);
+
+ return buf;
+}
+
static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
+ u8 buf[SS_STR_MAX_SIZE];
drm_printf(p, "slice total: %u, mask=%04x\n",
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%s\n",
s, sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
int s, ss;
+ u8 buf[SS_STR_MAX_SIZE];
if (sseu->max_slices == 0) {
drm_printf(p, "Unavailable\n");
@@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
s, sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ set_sseu_info(sseu, 1, 4, 8);
+ else
+ set_sseu_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+ sseu->subslice_mask[s * sseu->ss_stride] =
+ (ss_en >> ss_idx) & ss_en_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ if (sseu->subslice_mask[s * sseu->ss_stride] &
+ BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
}
}
@@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ set_sseu_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
-
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
@@ -242,14 +252,22 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ sseu_set_subslices(sseu, s, s == 0 ? subslice_mask :
+ subslice_mask & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -274,13 +292,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask;
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -289,7 +306,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -300,10 +317,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ sseu_set_subslices(sseu, 0, subslice_mask);
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -335,9 +354,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -356,14 +374,16 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
int eu_per_ss;
u8 eu_disabled_mask;
+ u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!(sseu->subslice_mask[ss_idx] &
+ BIT(ss % BITS_PER_BYTE)))
/* skip disabled subslice */
continue;
@@ -435,9 +455,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ set_sseu_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -464,18 +482,21 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
+ u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!(sseu->subslice_mask[ss_idx] &
+ BIT(ss % BITS_PER_BYTE)))
/* skip disabled subslice */
continue;
eu_disabled_mask =
- eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
+ eu_disable[s] >>
+ (ss * sseu->max_eus_per_subslice);
sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
@@ -514,6 +535,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
int s, ss;
+ u32 subslice_mask;
/*
* There isn't a register to tell us how many slices/subslices. We
@@ -525,22 +547,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -557,9 +575,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ set_sseu_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(subslice_mask),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ sseu_set_subslices(sseu, s, subslice_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 202b4b7a24f1..22c9787c9422 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -890,7 +890,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -966,6 +966,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -983,7 +984,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+ subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h
index d07a01b3ed0b..e48cfec80699 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -530,20 +530,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
+ BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+ BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 3d51ed1428d4..8d9504f083a6 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -50,6 +50,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/intel_sseu.h
index 0dfbed547da5..a659a827f640 100644
--- a/drivers/gpu/drm/i915/intel_sseu.h
+++ b/drivers/gpu/drm/i915/intel_sseu.h
@@ -14,10 +14,11 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -32,6 +33,9 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+ u8 eu_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
@@ -62,6 +66,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline void set_sseu_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+}
+
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
@@ -75,7 +90,32 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ unsigned int i, total = 0;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ total += hweight8(sseu->subslice_mask[slice * sseu->ss_stride +
+ i]);
+
+ return total;
+}
+
+static inline void sseu_copy_subslices(const struct sseu_dev_info *sseu,
+ int slice, u8 *to_mask,
+ const u8 *from_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride);
+}
+
+static inline void sseu_set_subslices(struct sseu_dev_info *sseu,
+ int slice, u32 ss_mask)
+{
+ int i, offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b3cbed1ee1c9..e8ddd56905db 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -771,7 +771,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
u32 slice = fls(sseu->slice_mask);
u32 fuse3 =
intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
- u8 ss_mask = sseu->subslice_mask[slice];
+ u8 ss_mask = sseu->subslice_mask[slice * sseu->ss_stride];
u8 enabled_mask = (ss_mask | ss_mask >>
GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-04-25 22:24 [PATCH 0/5] Refactor to expand " Stuart Summers
@ 2019-04-25 22:24 ` Stuart Summers
0 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-25 22:24 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
drivers/gpu/drm/i915/intel_sseu.h | 6 ++++++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..19746249d57b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4191,7 +4191,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/intel_sseu.h
index 2cbf0981b44f..b553d7280f35 100644
--- a/drivers/gpu/drm/i915/intel_sseu.h
+++ b/drivers/gpu/drm/i915/intel_sseu.h
@@ -62,6 +62,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-04-26 20:24 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
@ 2019-04-26 20:24 ` Stuart Summers
0 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-26 20:24 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++++++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2cbf0981b44f..b553d7280f35 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -62,6 +62,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ffbf5d920429..0ecf006d26b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-04-29 15:51 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
@ 2019-04-29 15:51 ` Stuart Summers
0 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-04-29 15:51 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++++++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index c0b16b248d4c..f5ff6b7a756a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ffbf5d920429..0ecf006d26b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
@ 2019-05-03 21:30 ` Stuart Summers
0 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
v3: add intel_* prefix to sseu_subslices_per_slice
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++++++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index d20b7f96907d..9618dff46d83 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 14cd83e9ea8b..dceb32a16c5c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4187,7 +4187,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, intel_sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..9d6b9c45bc5e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, intel_sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, intel_sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
2019-05-13 20:56 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
@ 2019-05-13 20:56 ` Stuart Summers
0 siblings, 0 replies; 20+ messages in thread
From: Stuart Summers @ 2019-05-13 20:56 UTC (permalink / raw)
To: intel-gfx
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
v3: add intel_* prefix to sseu_subslices_per_slice
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++++++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index d20b7f96907d..9618dff46d83 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 072464a18050..9b000ee3f982 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4191,7 +4191,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, intel_sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..9d6b9c45bc5e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, intel_sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, intel_sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-05-13 20:56 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-19 0:00 [PATCH 0/4] Refactor to expand subslice mask Stuart Summers
2019-04-19 0:00 ` [PATCH 1/4] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
2019-04-19 0:00 ` [PATCH 2/4] drm/i915: Add macro for SSEU stride calculation Stuart Summers
2019-04-19 0:00 ` [PATCH 3/4] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-04-19 0:00 ` [PATCH 4/4] drm/i915: Expand subslice mask Stuart Summers
2019-04-19 0:07 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand " Patchwork
2019-04-19 0:09 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-19 0:28 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-19 3:44 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
2019-04-25 16:29 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers
2019-04-25 16:29 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers
2019-04-25 16:29 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-04-25 16:29 ` [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h Stuart Summers
2019-04-25 16:29 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers
-- strict thread matches above, loose matches on Subject: below --
2019-04-25 22:24 [PATCH 0/5] Refactor to expand " Stuart Summers
2019-04-25 22:24 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-04-26 20:24 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
2019-04-26 20:24 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-04-29 15:51 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
2019-04-29 15:51 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
2019-05-03 21:30 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
2019-05-13 20:56 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers
2019-05-13 20:56 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers
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