[PATCH 1/2] drm/i915: Replace intel_ddi_pll_init()

[PATCH 1/2] drm/i915: Replace intel_ddi_pll_init()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_ddi_pll_init() is an anachronism. Rename it to
hsw_assert_cdclk() and move it to the power domain init code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c   | 25 -------------------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++++++++-
 2 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index bb81f3506222..bf5e2541c35e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1881,27 +1881,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
 	.get_hw_state = bxt_ddi_pll_get_hw_state,
 };
 
-static void intel_ddi_pll_init(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = to_i915(dev);
-
-	if (INTEL_GEN(dev_priv) < 9) {
-		u32 val = I915_READ(LCPLL_CTL);
-
-		/*
-		 * The LCPLL register should be turned on by the BIOS. For now
-		 * let's just check its state and print errors in case
-		 * something is wrong.  Don't even try to turn it on.
-		 */
-
-		if (val & LCPLL_CD_SOURCE_FCLK)
-			DRM_ERROR("CDCLK source is not LCPLL\n");
-
-		if (val & LCPLL_PLL_DISABLE)
-			DRM_ERROR("LCPLL is disabled\n");
-	}
-}
-
 struct intel_dpll_mgr {
 	const struct dpll_info *dpll_info;
 
@@ -3305,10 +3284,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	mutex_init(&dev_priv->dpll_lock);
 
 	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
-
-	/* FIXME: Move this to a more suitable place */
-	if (HAS_DDI(dev_priv))
-		intel_ddi_pll_init(dev);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1b7ea6bab613..b1fd2ae99199 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
+{
+	u32 val = I915_READ(LCPLL_CTL);
+
+	/*
+	 * The LCPLL register should be turned on by the BIOS. For now
+	 * let's just check its state and print errors in case
+	 * something is wrong.  Don't even try to turn it on.
+	 */
+
+	if (val & LCPLL_CD_SOURCE_FCLK)
+		DRM_ERROR("CDCLK source is not LCPLL\n");
+
+	if (val & LCPLL_PLL_DISABLE)
+		DRM_ERROR("LCPLL is disabled\n");
+}
+
 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
 				      bool enable)
 {
@@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 		mutex_unlock(&power_domains->lock);
 		assert_ved_power_gated(i915);
 		assert_isp_power_gated(i915);
-	} else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) {
+	} else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
+		hsw_assert_cdclk(i915);
+		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
+	} else if (IS_IVYBRIDGE(i915)) {
 		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
 	}
 
-- 
2.21.0

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[PATCH 2/2] drm/i915: Move the hsw/bdw pc8 code to intel_runtime_pm.c

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

hsw_enable_pc8()/hsw_disable_pc8() are more less equivalent to
the display core init/unit functions of later platforms. Relocate
the hsw/bdw code into intel_runtime_pm.c so that it sits next to
its cousins.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    | 222 +----------------------
 drivers/gpu/drm/i915/intel_display.h    |   4 +
 drivers/gpu/drm/i915/intel_drv.h        |   2 -
 drivers/gpu/drm/i915/intel_runtime_pm.c | 223 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.h |   2 +
 5 files changed, 230 insertions(+), 223 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d81ec80e34f6..a351c8e219ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8725,7 +8725,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
 }
 
 /* Sequence to disable CLKOUT_DP */
-static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
+void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
 {
 	u32 reg, tmp;
 
@@ -9482,226 +9482,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 
 	return ret;
 }
-
-static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = &dev_priv->drm;
-	struct intel_crtc *crtc;
-
-	for_each_intel_crtc(dev, crtc)
-		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
-		     pipe_name(crtc->pipe));
-
-	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
-			"Display power well on\n");
-	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
-	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
-	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
-	I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
-	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
-	     "CPU PWM1 enabled\n");
-	if (IS_HASWELL(dev_priv))
-		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
-		     "CPU PWM2 enabled\n");
-	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
-	     "PCH PWM1 enabled\n");
-	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
-	     "Utility pin enabled\n");
-	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
-
-	/*
-	 * In theory we can still leave IRQs enabled, as long as only the HPD
-	 * interrupts remain enabled. We used to check for that, but since it's
-	 * gen-specific and since we only disable LCPLL after we fully disable
-	 * the interrupts, the check below should be enough.
-	 */
-	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
-}
-
-static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
-{
-	if (IS_HASWELL(dev_priv))
-		return I915_READ(D_COMP_HSW);
-	else
-		return I915_READ(D_COMP_BDW);
-}
-
-static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
-{
-	if (IS_HASWELL(dev_priv)) {
-		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
-					    val))
-			DRM_DEBUG_KMS("Failed to write to D_COMP\n");
-	} else {
-		I915_WRITE(D_COMP_BDW, val);
-		POSTING_READ(D_COMP_BDW);
-	}
-}
-
-/*
- * This function implements pieces of two sequences from BSpec:
- * - Sequence for display software to disable LCPLL
- * - Sequence for display software to allow package C8+
- * The steps implemented here are just the steps that actually touch the LCPLL
- * register. Callers should take care of disabling all the display engine
- * functions, doing the mode unset, fixing interrupts, etc.
- */
-static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
-			      bool switch_to_fclk, bool allow_power_down)
-{
-	u32 val;
-
-	assert_can_disable_lcpll(dev_priv);
-
-	val = I915_READ(LCPLL_CTL);
-
-	if (switch_to_fclk) {
-		val |= LCPLL_CD_SOURCE_FCLK;
-		I915_WRITE(LCPLL_CTL, val);
-
-		if (wait_for_us(I915_READ(LCPLL_CTL) &
-				LCPLL_CD_SOURCE_FCLK_DONE, 1))
-			DRM_ERROR("Switching to FCLK failed\n");
-
-		val = I915_READ(LCPLL_CTL);
-	}
-
-	val |= LCPLL_PLL_DISABLE;
-	I915_WRITE(LCPLL_CTL, val);
-	POSTING_READ(LCPLL_CTL);
-
-	if (intel_wait_for_register(&dev_priv->uncore,
-				    LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
-		DRM_ERROR("LCPLL still locked\n");
-
-	val = hsw_read_dcomp(dev_priv);
-	val |= D_COMP_COMP_DISABLE;
-	hsw_write_dcomp(dev_priv, val);
-	ndelay(100);
-
-	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
-		     1))
-		DRM_ERROR("D_COMP RCOMP still in progress\n");
-
-	if (allow_power_down) {
-		val = I915_READ(LCPLL_CTL);
-		val |= LCPLL_POWER_DOWN_ALLOW;
-		I915_WRITE(LCPLL_CTL, val);
-		POSTING_READ(LCPLL_CTL);
-	}
-}
-
-/*
- * Fully restores LCPLL, disallowing power down and switching back to LCPLL
- * source.
- */
-static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	val = I915_READ(LCPLL_CTL);
-
-	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
-		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
-		return;
-
-	/*
-	 * Make sure we're not on PC8 state before disabling PC8, otherwise
-	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
-	 */
-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
-
-	if (val & LCPLL_POWER_DOWN_ALLOW) {
-		val &= ~LCPLL_POWER_DOWN_ALLOW;
-		I915_WRITE(LCPLL_CTL, val);
-		POSTING_READ(LCPLL_CTL);
-	}
-
-	val = hsw_read_dcomp(dev_priv);
-	val |= D_COMP_COMP_FORCE;
-	val &= ~D_COMP_COMP_DISABLE;
-	hsw_write_dcomp(dev_priv, val);
-
-	val = I915_READ(LCPLL_CTL);
-	val &= ~LCPLL_PLL_DISABLE;
-	I915_WRITE(LCPLL_CTL, val);
-
-	if (intel_wait_for_register(&dev_priv->uncore,
-				    LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
-				    5))
-		DRM_ERROR("LCPLL not locked yet\n");
-
-	if (val & LCPLL_CD_SOURCE_FCLK) {
-		val = I915_READ(LCPLL_CTL);
-		val &= ~LCPLL_CD_SOURCE_FCLK;
-		I915_WRITE(LCPLL_CTL, val);
-
-		if (wait_for_us((I915_READ(LCPLL_CTL) &
-				 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
-			DRM_ERROR("Switching back to LCPLL failed\n");
-	}
-
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
-
-	intel_update_cdclk(dev_priv);
-	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
-}
-
-/*
- * Package states C8 and deeper are really deep PC states that can only be
- * reached when all the devices on the system allow it, so even if the graphics
- * device allows PC8+, it doesn't mean the system will actually get to these
- * states. Our driver only allows PC8+ when going into runtime PM.
- *
- * The requirements for PC8+ are that all the outputs are disabled, the power
- * well is disabled and most interrupts are disabled, and these are also
- * requirements for runtime PM. When these conditions are met, we manually do
- * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
- * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
- * hang the machine.
- *
- * When we really reach PC8 or deeper states (not just when we allow it) we lose
- * the state of some registers, so when we come back from PC8+ we need to
- * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
- * need to take care of the registers kept by RC6. Notice that this happens even
- * if we don't put the device in PCI D3 state (which is what currently happens
- * because of the runtime PM support).
- *
- * For more, read "Display Sequences for Package C8" on the hardware
- * documentation.
- */
-void hsw_enable_pc8(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	DRM_DEBUG_KMS("Enabling package C8+\n");
-
-	if (HAS_PCH_LPT_LP(dev_priv)) {
-		val = I915_READ(SOUTH_DSPCLK_GATE_D);
-		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
-		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
-	}
-
-	lpt_disable_clkout_dp(dev_priv);
-	hsw_disable_lcpll(dev_priv, true, true);
-}
-
-void hsw_disable_pc8(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	DRM_DEBUG_KMS("Disabling package C8+\n");
-
-	hsw_restore_lcpll(dev_priv);
-	lpt_init_pch_refclk(dev_priv);
-
-	if (HAS_PCH_LPT_LP(dev_priv)) {
-		val = I915_READ(SOUTH_DSPCLK_GATE_D);
-		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
-		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
-	}
-}
-
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 2220588e86ac..1b6f5a71184d 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -28,6 +28,8 @@
 #include <drm/drm_util.h>
 #include <drm/i915_drm.h>
 
+struct drm_i915_private;
+
 enum i915_gpio {
 	GPIOA,
 	GPIOB,
@@ -432,4 +434,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    struct intel_link_m_n *m_n,
 			    bool constant_n);
 bool is_ccs_modifier(u64 modifier);
+void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4049e03d2c0d..247893ed1543 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1571,8 +1571,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 void intel_prepare_reset(struct drm_i915_private *dev_priv);
 void intel_finish_reset(struct drm_i915_private *dev_priv);
-void hsw_enable_pc8(struct drm_i915_private *dev_priv);
-void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b1fd2ae99199..b8fadd1b685c 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3642,6 +3642,229 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
 		DRM_ERROR("LCPLL is disabled\n");
 }
 
+static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = &dev_priv->drm;
+	struct intel_crtc *crtc;
+
+	for_each_intel_crtc(dev, crtc)
+		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
+				pipe_name(crtc->pipe));
+
+	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
+			"Display power well on\n");
+	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE,
+			"SPLL enabled\n");
+	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
+			"WRPLL1 enabled\n");
+	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
+			"WRPLL2 enabled\n");
+	I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON,
+			"Panel power on\n");
+	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
+			"CPU PWM1 enabled\n");
+	if (IS_HASWELL(dev_priv))
+		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
+				"CPU PWM2 enabled\n");
+	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
+			"PCH PWM1 enabled\n");
+	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
+			"Utility pin enabled\n");
+	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE,
+			"PCH GTC enabled\n");
+
+	/*
+	 * In theory we can still leave IRQs enabled, as long as only the HPD
+	 * interrupts remain enabled. We used to check for that, but since it's
+	 * gen-specific and since we only disable LCPLL after we fully disable
+	 * the interrupts, the check below should be enough.
+	 */
+	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
+}
+
+static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
+{
+	if (IS_HASWELL(dev_priv))
+		return I915_READ(D_COMP_HSW);
+	else
+		return I915_READ(D_COMP_BDW);
+}
+
+static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
+{
+	if (IS_HASWELL(dev_priv)) {
+		if (sandybridge_pcode_write(dev_priv,
+					    GEN6_PCODE_WRITE_D_COMP, val))
+			DRM_DEBUG_KMS("Failed to write to D_COMP\n");
+	} else {
+		I915_WRITE(D_COMP_BDW, val);
+		POSTING_READ(D_COMP_BDW);
+	}
+}
+
+/*
+ * This function implements pieces of two sequences from BSpec:
+ * - Sequence for display software to disable LCPLL
+ * - Sequence for display software to allow package C8+
+ * The steps implemented here are just the steps that actually touch the LCPLL
+ * register. Callers should take care of disabling all the display engine
+ * functions, doing the mode unset, fixing interrupts, etc.
+ */
+static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
+			      bool switch_to_fclk, bool allow_power_down)
+{
+	u32 val;
+
+	assert_can_disable_lcpll(dev_priv);
+
+	val = I915_READ(LCPLL_CTL);
+
+	if (switch_to_fclk) {
+		val |= LCPLL_CD_SOURCE_FCLK;
+		I915_WRITE(LCPLL_CTL, val);
+
+		if (wait_for_us(I915_READ(LCPLL_CTL) &
+				LCPLL_CD_SOURCE_FCLK_DONE, 1))
+			DRM_ERROR("Switching to FCLK failed\n");
+
+		val = I915_READ(LCPLL_CTL);
+	}
+
+	val |= LCPLL_PLL_DISABLE;
+	I915_WRITE(LCPLL_CTL, val);
+	POSTING_READ(LCPLL_CTL);
+
+	if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
+				    LCPLL_PLL_LOCK, 0, 1))
+		DRM_ERROR("LCPLL still locked\n");
+
+	val = hsw_read_dcomp(dev_priv);
+	val |= D_COMP_COMP_DISABLE;
+	hsw_write_dcomp(dev_priv, val);
+	ndelay(100);
+
+	if (wait_for((hsw_read_dcomp(dev_priv) &
+		      D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
+		DRM_ERROR("D_COMP RCOMP still in progress\n");
+
+	if (allow_power_down) {
+		val = I915_READ(LCPLL_CTL);
+		val |= LCPLL_POWER_DOWN_ALLOW;
+		I915_WRITE(LCPLL_CTL, val);
+		POSTING_READ(LCPLL_CTL);
+	}
+}
+
+/*
+ * Fully restores LCPLL, disallowing power down and switching back to LCPLL
+ * source.
+ */
+static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(LCPLL_CTL);
+
+	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
+		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
+		return;
+
+	/*
+	 * Make sure we're not on PC8 state before disabling PC8, otherwise
+	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
+	 */
+	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+
+	if (val & LCPLL_POWER_DOWN_ALLOW) {
+		val &= ~LCPLL_POWER_DOWN_ALLOW;
+		I915_WRITE(LCPLL_CTL, val);
+		POSTING_READ(LCPLL_CTL);
+	}
+
+	val = hsw_read_dcomp(dev_priv);
+	val |= D_COMP_COMP_FORCE;
+	val &= ~D_COMP_COMP_DISABLE;
+	hsw_write_dcomp(dev_priv, val);
+
+	val = I915_READ(LCPLL_CTL);
+	val &= ~LCPLL_PLL_DISABLE;
+	I915_WRITE(LCPLL_CTL, val);
+
+	if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
+				    LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 5))
+		DRM_ERROR("LCPLL not locked yet\n");
+
+	if (val & LCPLL_CD_SOURCE_FCLK) {
+		val = I915_READ(LCPLL_CTL);
+		val &= ~LCPLL_CD_SOURCE_FCLK;
+		I915_WRITE(LCPLL_CTL, val);
+
+		if (wait_for_us((I915_READ(LCPLL_CTL) &
+				 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
+			DRM_ERROR("Switching back to LCPLL failed\n");
+	}
+
+	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+
+	intel_update_cdclk(dev_priv);
+	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+}
+
+/*
+ * Package states C8 and deeper are really deep PC states that can only be
+ * reached when all the devices on the system allow it, so even if the graphics
+ * device allows PC8+, it doesn't mean the system will actually get to these
+ * states. Our driver only allows PC8+ when going into runtime PM.
+ *
+ * The requirements for PC8+ are that all the outputs are disabled, the power
+ * well is disabled and most interrupts are disabled, and these are also
+ * requirements for runtime PM. When these conditions are met, we manually do
+ * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
+ * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
+ * hang the machine.
+ *
+ * When we really reach PC8 or deeper states (not just when we allow it) we lose
+ * the state of some registers, so when we come back from PC8+ we need to
+ * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
+ * need to take care of the registers kept by RC6. Notice that this happens even
+ * if we don't put the device in PCI D3 state (which is what currently happens
+ * because of the runtime PM support).
+ *
+ * For more, read "Display Sequences for Package C8" on the hardware
+ * documentation.
+ */
+void hsw_enable_pc8(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	DRM_DEBUG_KMS("Enabling package C8+\n");
+
+	if (HAS_PCH_LPT_LP(dev_priv)) {
+		val = I915_READ(SOUTH_DSPCLK_GATE_D);
+		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
+		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+	}
+
+	lpt_disable_clkout_dp(dev_priv);
+	hsw_disable_lcpll(dev_priv, true, true);
+}
+
+void hsw_disable_pc8(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	DRM_DEBUG_KMS("Disabling package C8+\n");
+
+	hsw_restore_lcpll(dev_priv);
+	intel_init_pch_refclk(dev_priv);
+
+	if (HAS_PCH_LPT_LP(dev_priv)) {
+		val = I915_READ(SOUTH_DSPCLK_GATE_D);
+		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
+		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+	}
+}
+
 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
 				      bool enable)
 {
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index 69227756de3e..e30b38632bd2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -37,6 +37,8 @@ void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
 				 enum i915_drm_suspend_mode);
 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
+void hsw_enable_pc8(struct drm_i915_private *dev_priv);
+void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/2] drm/i915: Move the hsw/bdw pc8 code to intel_runtime_pm.c

[Imre Deak]

On Fri, May 03, 2019 at 10:31:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> hsw_enable_pc8()/hsw_disable_pc8() are more less equivalent to
> the display core init/unit functions of later platforms. Relocate
> the hsw/bdw code into intel_runtime_pm.c so that it sits next to
> its cousins.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c    | 222 +----------------------
>  drivers/gpu/drm/i915/intel_display.h    |   4 +
>  drivers/gpu/drm/i915/intel_drv.h        |   2 -
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 223 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.h |   2 +
>  5 files changed, 230 insertions(+), 223 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d81ec80e34f6..a351c8e219ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8725,7 +8725,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
>  }
>  
>  /* Sequence to disable CLKOUT_DP */
> -static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
>  {
>  	u32 reg, tmp;
>  
> @@ -9482,226 +9482,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  
>  	return ret;
>  }
> -
> -static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = &dev_priv->drm;
> -	struct intel_crtc *crtc;
> -
> -	for_each_intel_crtc(dev, crtc)
> -		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
> -		     pipe_name(crtc->pipe));
> -
> -	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
> -			"Display power well on\n");
> -	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> -	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> -	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> -	I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
> -	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> -	     "CPU PWM1 enabled\n");
> -	if (IS_HASWELL(dev_priv))
> -		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
> -		     "CPU PWM2 enabled\n");
> -	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
> -	     "PCH PWM1 enabled\n");
> -	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
> -	     "Utility pin enabled\n");
> -	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
> -
> -	/*
> -	 * In theory we can still leave IRQs enabled, as long as only the HPD
> -	 * interrupts remain enabled. We used to check for that, but since it's
> -	 * gen-specific and since we only disable LCPLL after we fully disable
> -	 * the interrupts, the check below should be enough.
> -	 */
> -	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
> -}
> -
> -static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> -{
> -	if (IS_HASWELL(dev_priv))
> -		return I915_READ(D_COMP_HSW);
> -	else
> -		return I915_READ(D_COMP_BDW);
> -}
> -
> -static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
> -{
> -	if (IS_HASWELL(dev_priv)) {
> -		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
> -					    val))
> -			DRM_DEBUG_KMS("Failed to write to D_COMP\n");
> -	} else {
> -		I915_WRITE(D_COMP_BDW, val);
> -		POSTING_READ(D_COMP_BDW);
> -	}
> -}
> -
> -/*
> - * This function implements pieces of two sequences from BSpec:
> - * - Sequence for display software to disable LCPLL
> - * - Sequence for display software to allow package C8+
> - * The steps implemented here are just the steps that actually touch the LCPLL
> - * register. Callers should take care of disabling all the display engine
> - * functions, doing the mode unset, fixing interrupts, etc.
> - */
> -static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> -			      bool switch_to_fclk, bool allow_power_down)
> -{
> -	u32 val;
> -
> -	assert_can_disable_lcpll(dev_priv);
> -
> -	val = I915_READ(LCPLL_CTL);
> -
> -	if (switch_to_fclk) {
> -		val |= LCPLL_CD_SOURCE_FCLK;
> -		I915_WRITE(LCPLL_CTL, val);
> -
> -		if (wait_for_us(I915_READ(LCPLL_CTL) &
> -				LCPLL_CD_SOURCE_FCLK_DONE, 1))
> -			DRM_ERROR("Switching to FCLK failed\n");
> -
> -		val = I915_READ(LCPLL_CTL);
> -	}
> -
> -	val |= LCPLL_PLL_DISABLE;
> -	I915_WRITE(LCPLL_CTL, val);
> -	POSTING_READ(LCPLL_CTL);
> -
> -	if (intel_wait_for_register(&dev_priv->uncore,
> -				    LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
> -		DRM_ERROR("LCPLL still locked\n");
> -
> -	val = hsw_read_dcomp(dev_priv);
> -	val |= D_COMP_COMP_DISABLE;
> -	hsw_write_dcomp(dev_priv, val);
> -	ndelay(100);
> -
> -	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
> -		     1))
> -		DRM_ERROR("D_COMP RCOMP still in progress\n");
> -
> -	if (allow_power_down) {
> -		val = I915_READ(LCPLL_CTL);
> -		val |= LCPLL_POWER_DOWN_ALLOW;
> -		I915_WRITE(LCPLL_CTL, val);
> -		POSTING_READ(LCPLL_CTL);
> -	}
> -}
> -
> -/*
> - * Fully restores LCPLL, disallowing power down and switching back to LCPLL
> - * source.
> - */
> -static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -
> -	val = I915_READ(LCPLL_CTL);
> -
> -	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
> -		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
> -		return;
> -
> -	/*
> -	 * Make sure we're not on PC8 state before disabling PC8, otherwise
> -	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> -	 */
> -	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> -
> -	if (val & LCPLL_POWER_DOWN_ALLOW) {
> -		val &= ~LCPLL_POWER_DOWN_ALLOW;
> -		I915_WRITE(LCPLL_CTL, val);
> -		POSTING_READ(LCPLL_CTL);
> -	}
> -
> -	val = hsw_read_dcomp(dev_priv);
> -	val |= D_COMP_COMP_FORCE;
> -	val &= ~D_COMP_COMP_DISABLE;
> -	hsw_write_dcomp(dev_priv, val);
> -
> -	val = I915_READ(LCPLL_CTL);
> -	val &= ~LCPLL_PLL_DISABLE;
> -	I915_WRITE(LCPLL_CTL, val);
> -
> -	if (intel_wait_for_register(&dev_priv->uncore,
> -				    LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
> -				    5))
> -		DRM_ERROR("LCPLL not locked yet\n");
> -
> -	if (val & LCPLL_CD_SOURCE_FCLK) {
> -		val = I915_READ(LCPLL_CTL);
> -		val &= ~LCPLL_CD_SOURCE_FCLK;
> -		I915_WRITE(LCPLL_CTL, val);
> -
> -		if (wait_for_us((I915_READ(LCPLL_CTL) &
> -				 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> -			DRM_ERROR("Switching back to LCPLL failed\n");
> -	}
> -
> -	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> -
> -	intel_update_cdclk(dev_priv);
> -	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> -}
> -
> -/*
> - * Package states C8 and deeper are really deep PC states that can only be
> - * reached when all the devices on the system allow it, so even if the graphics
> - * device allows PC8+, it doesn't mean the system will actually get to these
> - * states. Our driver only allows PC8+ when going into runtime PM.
> - *
> - * The requirements for PC8+ are that all the outputs are disabled, the power
> - * well is disabled and most interrupts are disabled, and these are also
> - * requirements for runtime PM. When these conditions are met, we manually do
> - * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
> - * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
> - * hang the machine.
> - *
> - * When we really reach PC8 or deeper states (not just when we allow it) we lose
> - * the state of some registers, so when we come back from PC8+ we need to
> - * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
> - * need to take care of the registers kept by RC6. Notice that this happens even
> - * if we don't put the device in PCI D3 state (which is what currently happens
> - * because of the runtime PM support).
> - *
> - * For more, read "Display Sequences for Package C8" on the hardware
> - * documentation.
> - */
> -void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -
> -	DRM_DEBUG_KMS("Enabling package C8+\n");
> -
> -	if (HAS_PCH_LPT_LP(dev_priv)) {
> -		val = I915_READ(SOUTH_DSPCLK_GATE_D);
> -		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> -		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> -	}
> -
> -	lpt_disable_clkout_dp(dev_priv);
> -	hsw_disable_lcpll(dev_priv, true, true);
> -}
> -
> -void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -
> -	DRM_DEBUG_KMS("Disabling package C8+\n");
> -
> -	hsw_restore_lcpll(dev_priv);
> -	lpt_init_pch_refclk(dev_priv);
> -
> -	if (HAS_PCH_LPT_LP(dev_priv)) {
> -		val = I915_READ(SOUTH_DSPCLK_GATE_D);
> -		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> -		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> -	}
> -}
> -
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  				      struct intel_crtc_state *crtc_state)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 2220588e86ac..1b6f5a71184d 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -28,6 +28,8 @@
>  #include <drm/drm_util.h>
>  #include <drm/i915_drm.h>
>  
> +struct drm_i915_private;
> +
>  enum i915_gpio {
>  	GPIOA,
>  	GPIOB,
> @@ -432,4 +434,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
>  			    struct intel_link_m_n *m_n,
>  			    bool constant_n);
>  bool is_ccs_modifier(u64 modifier);
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> +
>  #endif
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4049e03d2c0d..247893ed1543 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1571,8 +1571,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
>  #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>  void intel_prepare_reset(struct drm_i915_private *dev_priv);
>  void intel_finish_reset(struct drm_i915_private *dev_priv);
> -void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> -void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b1fd2ae99199..b8fadd1b685c 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3642,6 +3642,229 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
>  		DRM_ERROR("LCPLL is disabled\n");
>  }
>  
> +static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = &dev_priv->drm;
> +	struct intel_crtc *crtc;
> +
> +	for_each_intel_crtc(dev, crtc)
> +		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
> +				pipe_name(crtc->pipe));
> +
> +	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
> +			"Display power well on\n");
> +	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE,
> +			"SPLL enabled\n");
> +	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
> +			"WRPLL1 enabled\n");
> +	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
> +			"WRPLL2 enabled\n");
> +	I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON,
> +			"Panel power on\n");
> +	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> +			"CPU PWM1 enabled\n");
> +	if (IS_HASWELL(dev_priv))
> +		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
> +				"CPU PWM2 enabled\n");
> +	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
> +			"PCH PWM1 enabled\n");
> +	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
> +			"Utility pin enabled\n");
> +	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE,
> +			"PCH GTC enabled\n");
> +
> +	/*
> +	 * In theory we can still leave IRQs enabled, as long as only the HPD
> +	 * interrupts remain enabled. We used to check for that, but since it's
> +	 * gen-specific and since we only disable LCPLL after we fully disable
> +	 * the interrupts, the check below should be enough.
> +	 */
> +	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
> +}
> +
> +static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> +{
> +	if (IS_HASWELL(dev_priv))
> +		return I915_READ(D_COMP_HSW);
> +	else
> +		return I915_READ(D_COMP_BDW);
> +}
> +
> +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
> +{
> +	if (IS_HASWELL(dev_priv)) {
> +		if (sandybridge_pcode_write(dev_priv,
> +					    GEN6_PCODE_WRITE_D_COMP, val))
> +			DRM_DEBUG_KMS("Failed to write to D_COMP\n");
> +	} else {
> +		I915_WRITE(D_COMP_BDW, val);
> +		POSTING_READ(D_COMP_BDW);
> +	}
> +}
> +
> +/*
> + * This function implements pieces of two sequences from BSpec:
> + * - Sequence for display software to disable LCPLL
> + * - Sequence for display software to allow package C8+
> + * The steps implemented here are just the steps that actually touch the LCPLL
> + * register. Callers should take care of disabling all the display engine
> + * functions, doing the mode unset, fixing interrupts, etc.
> + */
> +static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> +			      bool switch_to_fclk, bool allow_power_down)
> +{
> +	u32 val;
> +
> +	assert_can_disable_lcpll(dev_priv);
> +
> +	val = I915_READ(LCPLL_CTL);
> +
> +	if (switch_to_fclk) {
> +		val |= LCPLL_CD_SOURCE_FCLK;
> +		I915_WRITE(LCPLL_CTL, val);
> +
> +		if (wait_for_us(I915_READ(LCPLL_CTL) &
> +				LCPLL_CD_SOURCE_FCLK_DONE, 1))
> +			DRM_ERROR("Switching to FCLK failed\n");
> +
> +		val = I915_READ(LCPLL_CTL);
> +	}
> +
> +	val |= LCPLL_PLL_DISABLE;
> +	I915_WRITE(LCPLL_CTL, val);
> +	POSTING_READ(LCPLL_CTL);
> +
> +	if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
> +				    LCPLL_PLL_LOCK, 0, 1))
> +		DRM_ERROR("LCPLL still locked\n");
> +
> +	val = hsw_read_dcomp(dev_priv);
> +	val |= D_COMP_COMP_DISABLE;
> +	hsw_write_dcomp(dev_priv, val);
> +	ndelay(100);
> +
> +	if (wait_for((hsw_read_dcomp(dev_priv) &
> +		      D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
> +		DRM_ERROR("D_COMP RCOMP still in progress\n");
> +
> +	if (allow_power_down) {
> +		val = I915_READ(LCPLL_CTL);
> +		val |= LCPLL_POWER_DOWN_ALLOW;
> +		I915_WRITE(LCPLL_CTL, val);
> +		POSTING_READ(LCPLL_CTL);
> +	}
> +}
> +
> +/*
> + * Fully restores LCPLL, disallowing power down and switching back to LCPLL
> + * source.
> + */
> +static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> +{
> +	u32 val;
> +
> +	val = I915_READ(LCPLL_CTL);
> +
> +	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
> +		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
> +		return;
> +
> +	/*
> +	 * Make sure we're not on PC8 state before disabling PC8, otherwise
> +	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> +	 */
> +	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> +
> +	if (val & LCPLL_POWER_DOWN_ALLOW) {
> +		val &= ~LCPLL_POWER_DOWN_ALLOW;
> +		I915_WRITE(LCPLL_CTL, val);
> +		POSTING_READ(LCPLL_CTL);
> +	}
> +
> +	val = hsw_read_dcomp(dev_priv);
> +	val |= D_COMP_COMP_FORCE;
> +	val &= ~D_COMP_COMP_DISABLE;
> +	hsw_write_dcomp(dev_priv, val);
> +
> +	val = I915_READ(LCPLL_CTL);
> +	val &= ~LCPLL_PLL_DISABLE;
> +	I915_WRITE(LCPLL_CTL, val);
> +
> +	if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
> +				    LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 5))
> +		DRM_ERROR("LCPLL not locked yet\n");
> +
> +	if (val & LCPLL_CD_SOURCE_FCLK) {
> +		val = I915_READ(LCPLL_CTL);
> +		val &= ~LCPLL_CD_SOURCE_FCLK;
> +		I915_WRITE(LCPLL_CTL, val);
> +
> +		if (wait_for_us((I915_READ(LCPLL_CTL) &
> +				 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> +			DRM_ERROR("Switching back to LCPLL failed\n");
> +	}
> +
> +	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +
> +	intel_update_cdclk(dev_priv);
> +	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +}
> +
> +/*
> + * Package states C8 and deeper are really deep PC states that can only be
> + * reached when all the devices on the system allow it, so even if the graphics
> + * device allows PC8+, it doesn't mean the system will actually get to these
> + * states. Our driver only allows PC8+ when going into runtime PM.
> + *
> + * The requirements for PC8+ are that all the outputs are disabled, the power
> + * well is disabled and most interrupts are disabled, and these are also
> + * requirements for runtime PM. When these conditions are met, we manually do
> + * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
> + * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
> + * hang the machine.
> + *
> + * When we really reach PC8 or deeper states (not just when we allow it) we lose
> + * the state of some registers, so when we come back from PC8+ we need to
> + * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
> + * need to take care of the registers kept by RC6. Notice that this happens even
> + * if we don't put the device in PCI D3 state (which is what currently happens
> + * because of the runtime PM support).
> + *
> + * For more, read "Display Sequences for Package C8" on the hardware
> + * documentation.
> + */
> +void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> +{
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("Enabling package C8+\n");
> +
> +	if (HAS_PCH_LPT_LP(dev_priv)) {
> +		val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> +		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +	}
> +
> +	lpt_disable_clkout_dp(dev_priv);
> +	hsw_disable_lcpll(dev_priv, true, true);
> +}
> +
> +void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> +{
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("Disabling package C8+\n");
> +
> +	hsw_restore_lcpll(dev_priv);
> +	intel_init_pch_refclk(dev_priv);
> +
> +	if (HAS_PCH_LPT_LP(dev_priv)) {
> +		val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> +		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +	}
> +}
> +
>  static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
>  				      bool enable)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
> index 69227756de3e..e30b38632bd2 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.h
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
> @@ -37,6 +37,8 @@ void intel_power_domains_disable(struct drm_i915_private *dev_priv);
>  void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
>  				 enum i915_drm_suspend_mode);
>  void intel_power_domains_resume(struct drm_i915_private *dev_priv);
> +void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> +void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
>  void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Replace intel_ddi_pll_init()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Replace intel_ddi_pll_init()
URL   : https://patchwork.freedesktop.org/series/60272/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6041 -> Patchwork_12963
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/

Known issues
------------

  Here are the changes found in Patchwork_12963 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       [PASS][1] -> [INCOMPLETE][2] ([fdo#107718] / [fdo#110581])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/fi-blb-e6850/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/fi-blb-e6850/igt@i915_module_load@reload.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       [INCOMPLETE][3] ([fdo#108602] / [fdo#108744] / [fdo#110581]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][5] ([fdo#109485]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - {fi-icl-u2}:        [DMESG-WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581
  [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595


Participating hosts (51 -> 46)
------------------------------

  Additional (2): fi-bsw-n3050 fi-pnv-d510 
  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6041 -> Patchwork_12963

  CI_DRM_6041: 014903e8b7de5d69a17de628345ed31db1600b73 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12963: 91cf56f6d70db058eda922fce0a7265b7561f045 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

91cf56f6d70d drm/i915: Move the hsw/bdw pc8 code to intel_runtime_pm.c
65a6f208116e drm/i915: Replace intel_ddi_pll_init()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Replace intel_ddi_pll_init()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Replace intel_ddi_pll_init()
URL   : https://patchwork.freedesktop.org/series/60272/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6041_full -> Patchwork_12963_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12963_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107807] / [fdo#110581]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-apl3/igt@kms_cursor_crc@cursor-128x128-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-apl1/igt@kms_cursor_crc@cursor-128x128-suspend.html

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#110581])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl10/igt@kms_cursor_crc@cursor-64x64-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl1/igt@kms_cursor_crc@cursor-64x64-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          [PASS][7] -> [INCOMPLETE][8] ([fdo#103359] / [fdo#110581] / [k.org#198133])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-glk5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([fdo#103060]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-glk6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@busy-flip:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#110581])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb1/igt@kms_flip@busy-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb1/igt@kms_flip@busy-flip.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          [PASS][13] -> [DMESG-WARN][14] ([fdo#102365])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-snb4/igt@kms_flip@flip-vs-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-snb6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103166])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109642])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb8/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-apl7/igt@kms_setmode@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-apl8/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([fdo#99912])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-kbl2/igt@kms_setmode@basic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-kbl2/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries_display_off:
    - shard-skl:          [INCOMPLETE][29] ([fdo#104108] / [fdo#110581]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl5/igt@debugfs_test@read_all_entries_display_off.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl1/igt@debugfs_test@read_all_entries_display_off.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-snb:          [DMESG-WARN][31] ([fdo#108686]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-snb6/igt@gem_tiled_swapping@non-threaded.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-snb4/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +5 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-apl8/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         [FAIL][35] ([fdo#104097]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb6/igt@i915_pm_rpm@i2c.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb7/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-skl:          [INCOMPLETE][37] ([fdo#107807] / [fdo#110581]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl6/igt@i915_pm_rpm@pm-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl8/igt@i915_pm_rpm@pm-tiling.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][39] ([fdo#107773] / [fdo#109507] / [fdo#110581]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl5/igt@kms_flip@flip-vs-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl8/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][43] ([fdo#108145]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-skl:          [SKIP][47] ([fdo#109271]) -> [INCOMPLETE][48] ([fdo#107807] / [fdo#110581])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6041/shard-skl8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/shard-skl4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  
  [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6041 -> Patchwork_12963

  CI_DRM_6041: 014903e8b7de5d69a17de628345ed31db1600b73 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12963: 91cf56f6d70db058eda922fce0a7265b7561f045 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12963/
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Re: [PATCH 1/2] drm/i915: Replace intel_ddi_pll_init()

[Imre Deak]

On Fri, May 03, 2019 at 10:31:42PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_ddi_pll_init() is an anachronism. Rename it to
> hsw_assert_cdclk() and move it to the power domain init code.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Ok, makes sense to check this during system resume too:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   | 25 -------------------------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++++++++-
>  2 files changed, 21 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index bb81f3506222..bf5e2541c35e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1881,27 +1881,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
>  	.get_hw_state = bxt_ddi_pll_get_hw_state,
>  };
>  
> -static void intel_ddi_pll_init(struct drm_device *dev)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -
> -	if (INTEL_GEN(dev_priv) < 9) {
> -		u32 val = I915_READ(LCPLL_CTL);
> -
> -		/*
> -		 * The LCPLL register should be turned on by the BIOS. For now
> -		 * let's just check its state and print errors in case
> -		 * something is wrong.  Don't even try to turn it on.
> -		 */
> -
> -		if (val & LCPLL_CD_SOURCE_FCLK)
> -			DRM_ERROR("CDCLK source is not LCPLL\n");
> -
> -		if (val & LCPLL_PLL_DISABLE)
> -			DRM_ERROR("LCPLL is disabled\n");
> -	}
> -}
> -
>  struct intel_dpll_mgr {
>  	const struct dpll_info *dpll_info;
>  
> @@ -3305,10 +3284,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  	mutex_init(&dev_priv->dpll_lock);
>  
>  	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
> -
> -	/* FIXME: Move this to a more suitable place */
> -	if (HAS_DDI(dev_priv))
> -		intel_ddi_pll_init(dev);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1b7ea6bab613..b1fd2ae99199 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  	I915_WRITE(MBUS_ABOX_CTL, val);
>  }
>  
> +static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	u32 val = I915_READ(LCPLL_CTL);
> +
> +	/*
> +	 * The LCPLL register should be turned on by the BIOS. For now
> +	 * let's just check its state and print errors in case
> +	 * something is wrong.  Don't even try to turn it on.
> +	 */
> +
> +	if (val & LCPLL_CD_SOURCE_FCLK)
> +		DRM_ERROR("CDCLK source is not LCPLL\n");
> +
> +	if (val & LCPLL_PLL_DISABLE)
> +		DRM_ERROR("LCPLL is disabled\n");
> +}
> +
>  static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
>  				      bool enable)
>  {
> @@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>  		mutex_unlock(&power_domains->lock);
>  		assert_ved_power_gated(i915);
>  		assert_isp_power_gated(i915);
> -	} else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) {
> +	} else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
> +		hsw_assert_cdclk(i915);
> +		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
> +	} else if (IS_IVYBRIDGE(i915)) {
>  		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
>  	}
>  
> -- 
> 2.21.0
> 
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> Intel-gfx@lists.freedesktop.org
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