* [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL
@ 2019-05-08 19:35 Shashank Sharma
2019-05-08 19:35 ` [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32 Shashank Sharma
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Shashank Sharma @ 2019-05-08 19:35 UTC (permalink / raw)
To: intel-gfx
This patch series enables programming of Multi-segmented-gamma
palette for ICL.
Shashank Sharma (3):
drm/i915: Change gamma/degamma_lut_size data type to u32
drm/i915: Rename ivb_load_lut_10_max
drm/i915/icl: Add Multi-segmented gamma support
Uma Shankar (1):
drm/i915/icl: Add register definitions for Multi Segmented gamma
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 19 ++-
drivers/gpu/drm/i915/intel_color.c | 140 +++++++++++++++++++++--
drivers/gpu/drm/i915/intel_device_info.h | 4 +-
4 files changed, 150 insertions(+), 15 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma @ 2019-05-08 19:35 ` Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma Shashank Sharma ` (4 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Shashank Sharma @ 2019-05-08 19:35 UTC (permalink / raw) To: intel-gfx Currently, data type of gamma_lut_size & degamma_lut_size elements in intel_device_info is u16, which means it can accommodate maximum 64k values. In case of ICL multisegmented gamma, the size of gamma LUT is 256K. This patch changes the data type of both of these elements to u32. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> V4: Added Uma's r-b. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> --- drivers/gpu/drm/i915/intel_device_info.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 5a2e17d6146b..67677c356716 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -179,8 +179,8 @@ struct intel_device_info { int cursor_offsets[I915_MAX_PIPES]; struct color_luts { - u16 degamma_lut_size; - u16 gamma_lut_size; + u32 degamma_lut_size; + u32 gamma_lut_size; u32 degamma_lut_tests; u32 gamma_lut_tests; } color; -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32 Shashank Sharma @ 2019-05-08 19:35 ` Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 3/4] drm/i915: Rename ivb_load_lut_10_max Shashank Sharma ` (3 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Shashank Sharma @ 2019-05-08 19:35 UTC (permalink / raw) To: intel-gfx From: Uma Shankar <uma.shankar@intel.com> Add macros to define multi segmented gamma registers V2: Addressed Ville's comments: Add gen-lable before bit definition Addressed Jani's comment - Use REG_GENMASK() and REG_BIT() V3: Addressed Ville's comments: - Put comments at the end of line. - Change the comment at start of ICL multisegmented gamma registers. Added Ville's r-b Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e97c47fca645..8b77c067e26b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7198,7 +7198,8 @@ enum { #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0) #define GAMMA_MODE_MODE_12BIT (2 << 0) -#define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ +#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) @@ -10145,6 +10146,22 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) +/* ICL Multi segmented gamma */ +#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 +#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 +#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) +#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) + +#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C +#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C + +#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_INDEX_A, \ + _PAL_PREC_MULTI_SEG_INDEX_B) +#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_DATA_A, \ + _PAL_PREC_MULTI_SEG_DATA_B) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 3/4] drm/i915: Rename ivb_load_lut_10_max 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32 Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma Shashank Sharma @ 2019-05-08 19:35 ` Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support Shashank Sharma ` (2 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Shashank Sharma @ 2019-05-08 19:35 UTC (permalink / raw) To: intel-gfx This patch renames function ivb_load_lut_10_max to ivb_load_lut_ext_max. V3: Added Vill'es r-b. Cc: Uma Shankar <uma.shankar@intel.com> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> --- drivers/gpu/drm/i915/intel_color.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 962db1236970..6c341bea514c 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -607,7 +607,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc, I915_WRITE(PREC_PAL_INDEX(pipe), 0); } -static void ivb_load_lut_10_max(struct intel_crtc *crtc) +static void ivb_load_lut_ext_max(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; @@ -640,7 +640,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); } else { @@ -648,7 +648,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) ivb_load_lut_10(crtc, blob, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); } } @@ -663,7 +663,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state) } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); } else { @@ -671,7 +671,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state) bdw_load_lut_10(crtc, blob, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); } } @@ -763,7 +763,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) i9xx_load_luts(crtc_state); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); } } @@ -780,7 +780,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) i9xx_load_luts(crtc_state); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_10_max(crtc); + ivb_load_lut_ext_max(crtc); } } -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma ` (2 preceding siblings ...) 2019-05-08 19:35 ` [PATCH v4 3/4] drm/i915: Rename ivb_load_lut_10_max Shashank Sharma @ 2019-05-08 19:35 ` Shashank Sharma 2019-05-09 13:40 ` Ville Syrjälä 2019-05-08 20:20 ` ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL (rev3) Patchwork 2019-05-08 23:16 ` ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 1 reply; 8+ messages in thread From: Shashank Sharma @ 2019-05-08 19:35 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter ICL introduces a new gamma correction mode in display engine, called multi-segmented-gamma mode. This mode allows users to program the darker region of the gamma curve with sueprfine precision. An example use case for this is HDR curves (like PQ ST-2084). If we plot a gamma correction curve from value range between 0.0 to 1.0, ICL's multi-segment has 3 different sections: - superfine segment: 9 values, ranges between 0 - 1/(128 * 256) - fine segment: 257 values, ranges between 0 - 1/(128) - corase segment: 257 values, ranges between 0 - 1 This patch: - Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256), so that userspace can program with highest precision supported. - Changes default gamma mode (non-legacy) to multi-segmented-gamma mode. - Adds functions to program/detect multi-segment gamma. V2: Addressed review comments from Ville - separate function for superfine and fine segments. - remove enum for segments. - reuse last entry of the LUT as gc_max value. - replace if() ....cond with switch...case in icl_load_luts. - add an entry variable, instead of 'word' V3: Addressed review comments from Ville - extra newline - s/entry/color/ - remove LUT size checks - program ilk_lut_12p4_ldw value before ilk_lut_12p4_udw - Change the comments in description of fine and coarse segments, and try to make more sense. - use 8 * 128 instead of 1024 - add 1 entry in LUT for GCMAX V4: Addressed review comments from Ville - Remove unused macro - missing shift entry in blue - pick correct entry for GCMAX - Added Ville's R-B Note: Tested and confirmed the programming sequence of odd/even registers in the HW. The correct sequence should be: ilk_lut_12p4_udw ilk_lut_12p4_ldw Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_color.c | 126 ++++++++++++++++++++++++++++- 2 files changed, 123 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d7c07a947497..24305238b4ea 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -747,7 +747,7 @@ static const struct intel_device_info intel_cannonlake_info = { GEN(11), \ .ddb_size = 2048, \ .has_logical_ring_elsq = 1, \ - .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } static const struct intel_device_info intel_icelake_11_info = { GEN11_FEATURES, diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 6c341bea514c..22ccbeacbee2 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -41,6 +41,7 @@ #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) #define LEGACY_LUT_LENGTH 256 + /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the @@ -767,6 +768,116 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) } } +/* ilk+ "12.4" interpolated format (high 10 bits) */ +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) +{ + return (color->red >> 6) << 20 | (color->green >> 6) << 10 | + (color->blue >> 6); +} + +/* ilk+ "12.4" interpolated format (low 6 bits) */ +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) +{ + return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | + (color->blue & 0x3f << 4); +} + +static void +icl_load_gcmax(const struct intel_crtc_state *crtc_state, + const struct drm_color_lut *color) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */ + I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red); + I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green); + I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue); +} + +static void +icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_property_blob *blob = crtc_state->base.gamma_lut; + const struct drm_color_lut *lut = blob->data; + enum pipe pipe = crtc->pipe; + u32 i; + + /* + * Every entry in the multi-segment LUT is corresponding to a superfine + * segment step which is 1/(8 * 128 * 256). + * + * Superfine segment has 9 entries, corresponding to values + * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256). + */ + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < 9; i++) { + const struct drm_color_lut *entry = &lut[i]; + + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), + ilk_lut_12p4_udw(entry)); + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), + ilk_lut_12p4_ldw(entry)); + } +} + +static void +icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_property_blob *blob = crtc_state->base.gamma_lut; + const struct drm_color_lut *lut = blob->data; + const struct drm_color_lut *entry; + enum pipe pipe = crtc->pipe; + u32 i; + + /* + * + * Program Fine segment (let's call it seg2)... + * + * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256) + * ... 256/(128*256). So in order to program fine segment of LUT we + * need to pick every 8'th entry in LUT, and program 256 indexes. + * + * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], + * with seg2[0] being unused by the hardware. + */ + I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); + for (i = 1; i < 257; i++) { + entry = &lut[i * 8]; + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); + } + + /* + * Program Coarse segment (let's call it seg3)... + * + * Coarse segment's starts from index 0 and it's step is 1/256 ie 0, + * 1/256, 2/256 ...256/256. As per the description of each entry in LUT + * above, we need to pick every (8 * 128)th entry in LUT, and + * program 256 of those. + * + * Spec is not very clear about if entries seg3[0] and seg3[1] are + * being used or not, but we still need to program these to advance + * the index. + */ + for (i = 0; i < 256; i++) { + entry = &lut[i * 8 * 128]; + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); + } + + /* The last entry in the LUT is to be programmed in GCMAX */ + entry = &lut[256 * 8 * 128]; + icl_load_gcmax(crtc_state, entry); + ivb_load_lut_ext_max(crtc); +} + static void icl_load_luts(const struct intel_crtc_state *crtc_state) { const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; @@ -775,10 +886,17 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) if (crtc_state->base.degamma_lut) glk_load_degamma_lut(crtc_state); - if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == - GAMMA_MODE_MODE_8BIT) { + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: i9xx_load_luts(crtc_state); - } else { + break; + + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + icl_program_gamma_superfine_segment(crtc_state); + icl_program_gamma_multi_segment(crtc_state); + break; + + default: bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc); } @@ -1209,7 +1327,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) crtc_state_is_legacy_gamma(crtc_state)) gamma_mode |= GAMMA_MODE_MODE_8BIT; else - gamma_mode |= GAMMA_MODE_MODE_10BIT; + gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; return gamma_mode; } -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support 2019-05-08 19:35 ` [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support Shashank Sharma @ 2019-05-09 13:40 ` Ville Syrjälä 0 siblings, 0 replies; 8+ messages in thread From: Ville Syrjälä @ 2019-05-09 13:40 UTC (permalink / raw) To: Shashank Sharma; +Cc: Daniel Vetter, intel-gfx On Thu, May 09, 2019 at 01:05:26AM +0530, Shashank Sharma wrote: > ICL introduces a new gamma correction mode in display engine, called > multi-segmented-gamma mode. This mode allows users to program the > darker region of the gamma curve with sueprfine precision. An > example use case for this is HDR curves (like PQ ST-2084). > > If we plot a gamma correction curve from value range between 0.0 to 1.0, > ICL's multi-segment has 3 different sections: > - superfine segment: 9 values, ranges between 0 - 1/(128 * 256) > - fine segment: 257 values, ranges between 0 - 1/(128) > - corase segment: 257 values, ranges between 0 - 1 > > This patch: > - Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256), > so that userspace can program with highest precision supported. > - Changes default gamma mode (non-legacy) to multi-segmented-gamma mode. > - Adds functions to program/detect multi-segment gamma. > > V2: Addressed review comments from Ville > - separate function for superfine and fine segments. > - remove enum for segments. > - reuse last entry of the LUT as gc_max value. > - replace if() ....cond with switch...case in icl_load_luts. > - add an entry variable, instead of 'word' > > V3: Addressed review comments from Ville > - extra newline > - s/entry/color/ > - remove LUT size checks > - program ilk_lut_12p4_ldw value before ilk_lut_12p4_udw > - Change the comments in description of fine and coarse segments, > and try to make more sense. > - use 8 * 128 instead of 1024 > - add 1 entry in LUT for GCMAX > > V4: Addressed review comments from Ville > - Remove unused macro > - missing shift entry in blue > - pick correct entry for GCMAX > - Added Ville's R-B > Note: Tested and confirmed the programming sequence of odd/even > registers in the HW. The correct sequence should be: > ilk_lut_12p4_udw > ilk_lut_12p4_ldw > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 2 +- > drivers/gpu/drm/i915/intel_color.c | 126 ++++++++++++++++++++++++++++- > 2 files changed, 123 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index d7c07a947497..24305238b4ea 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -747,7 +747,7 @@ static const struct intel_device_info intel_cannonlake_info = { > GEN(11), \ > .ddb_size = 2048, \ > .has_logical_ring_elsq = 1, \ > - .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } > + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } > > static const struct intel_device_info intel_icelake_11_info = { > GEN11_FEATURES, > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 6c341bea514c..22ccbeacbee2 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -41,6 +41,7 @@ > #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) > > #define LEGACY_LUT_LENGTH 256 > + > /* > * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point > * format). This macro takes the coefficient we want transformed and the > @@ -767,6 +768,116 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) > } > } > > +/* ilk+ "12.4" interpolated format (high 10 bits) */ > +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) > +{ > + return (color->red >> 6) << 20 | (color->green >> 6) << 10 | > + (color->blue >> 6); > +} > + > +/* ilk+ "12.4" interpolated format (low 6 bits) */ > +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) > +{ > + return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | > + (color->blue & 0x3f << 4); Wrong placement of the closing paren. > +} > + > +static void > +icl_load_gcmax(const struct intel_crtc_state *crtc_state, > + const struct drm_color_lut *color) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + enum pipe pipe = crtc->pipe; > + > + /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */ > + I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red); > + I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green); > + I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue); > +} > + > +static void > +icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + const struct drm_property_blob *blob = crtc_state->base.gamma_lut; > + const struct drm_color_lut *lut = blob->data; > + enum pipe pipe = crtc->pipe; > + u32 i; > + > + /* > + * Every entry in the multi-segment LUT is corresponding to a superfine > + * segment step which is 1/(8 * 128 * 256). > + * > + * Superfine segment has 9 entries, corresponding to values > + * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256). > + */ > + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); > + > + for (i = 0; i < 9; i++) { > + const struct drm_color_lut *entry = &lut[i]; > + > + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), > + ilk_lut_12p4_udw(entry)); > + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), > + ilk_lut_12p4_ldw(entry)); If this is correct then the functions are named wrong. > + } > +} > + > +static void > +icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + const struct drm_property_blob *blob = crtc_state->base.gamma_lut; > + const struct drm_color_lut *lut = blob->data; > + const struct drm_color_lut *entry; > + enum pipe pipe = crtc->pipe; > + u32 i; > + > + /* > + * > + * Program Fine segment (let's call it seg2)... > + * > + * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256) > + * ... 256/(128*256). So in order to program fine segment of LUT we > + * need to pick every 8'th entry in LUT, and program 256 indexes. > + * > + * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], > + * with seg2[0] being unused by the hardware. > + */ > + I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); > + for (i = 1; i < 257; i++) { > + entry = &lut[i * 8]; > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); > + } > + > + /* > + * Program Coarse segment (let's call it seg3)... > + * > + * Coarse segment's starts from index 0 and it's step is 1/256 ie 0, > + * 1/256, 2/256 ...256/256. As per the description of each entry in LUT > + * above, we need to pick every (8 * 128)th entry in LUT, and > + * program 256 of those. > + * > + * Spec is not very clear about if entries seg3[0] and seg3[1] are > + * being used or not, but we still need to program these to advance > + * the index. > + */ > + for (i = 0; i < 256; i++) { > + entry = &lut[i * 8 * 128]; > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); > + } > + > + /* The last entry in the LUT is to be programmed in GCMAX */ > + entry = &lut[256 * 8 * 128]; > + icl_load_gcmax(crtc_state, entry); > + ivb_load_lut_ext_max(crtc); > +} > + > static void icl_load_luts(const struct intel_crtc_state *crtc_state) > { > const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; > @@ -775,10 +886,17 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) > if (crtc_state->base.degamma_lut) > glk_load_degamma_lut(crtc_state); > > - if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == > - GAMMA_MODE_MODE_8BIT) { > + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { > + case GAMMA_MODE_MODE_8BIT: > i9xx_load_luts(crtc_state); > - } else { > + break; > + > + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > + icl_program_gamma_superfine_segment(crtc_state); > + icl_program_gamma_multi_segment(crtc_state); > + break; > + > + default: > bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); > ivb_load_lut_ext_max(crtc); > } > @@ -1209,7 +1327,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) > crtc_state_is_legacy_gamma(crtc_state)) > gamma_mode |= GAMMA_MODE_MODE_8BIT; > else > - gamma_mode |= GAMMA_MODE_MODE_10BIT; > + gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; > > return gamma_mode; > } > -- > 2.17.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL (rev3) 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma ` (3 preceding siblings ...) 2019-05-08 19:35 ` [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support Shashank Sharma @ 2019-05-08 20:20 ` Patchwork 2019-05-08 23:16 ` ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-05-08 20:20 UTC (permalink / raw) To: Sharma, Shashank; +Cc: intel-gfx == Series Details == Series: Enable Multi-segmented-gamma for ICL (rev3) URL : https://patchwork.freedesktop.org/series/60126/ State : success == Summary == CI Bug Log - changes from CI_DRM_6065 -> Patchwork_12989 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/ Known issues ------------ Here are the changes found in Patchwork_12989 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html * igt@i915_selftest@live_evict: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([fdo#107709]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-bsw-kefka/igt@i915_selftest@live_evict.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-bsw-kefka/igt@i915_selftest@live_evict.html * igt@kms_busy@basic-flip-c: - fi-skl-6770hq: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html #### Possible fixes #### * igt@i915_selftest@live_hangcheck: - {fi-icl-y}: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-icl-y/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-icl-y/igt@i915_selftest@live_hangcheck.html #### Warnings #### * igt@i915_selftest@live_hangcheck: - fi-apl-guc: [INCOMPLETE][11] ([fdo#103927] / [fdo#110624]) -> [DMESG-FAIL][12] ([fdo#110620]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-apl-guc/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-apl-guc/igt@i915_selftest@live_hangcheck.html * igt@runner@aborted: - fi-apl-guc: [FAIL][13] ([fdo#110624]) -> [FAIL][14] ([fdo#110622]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-apl-guc/igt@runner@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-apl-guc/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620 [fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622 [fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624 Participating hosts (53 -> 45) ------------------------------ Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6065 -> Patchwork_12989 CI_DRM_6065: 4ce82224f3c40ee55f11a505b57247f8f540990a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4973: 3e3ff0e48989abd25fce4916e85e8fef20a3c63a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12989: 4020491ef16ee377ff619d71ad828cf682db3ecd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4020491ef16e drm/i915/icl: Add Multi-segmented gamma support ec51ec6a38e3 drm/i915: Rename ivb_load_lut_10_max 904edca45871 drm/i915/icl: Add register definitions for Multi Segmented gamma 1f1169d2b4ac drm/i915: Change gamma/degamma_lut_size data type to u32 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.IGT: failure for Enable Multi-segmented-gamma for ICL (rev3) 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma ` (4 preceding siblings ...) 2019-05-08 20:20 ` ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL (rev3) Patchwork @ 2019-05-08 23:16 ` Patchwork 5 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-05-08 23:16 UTC (permalink / raw) To: Sharma, Shashank; +Cc: intel-gfx == Series Details == Series: Enable Multi-segmented-gamma for ICL (rev3) URL : https://patchwork.freedesktop.org/series/60126/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6065_full -> Patchwork_12989_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_12989_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12989_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_12989_full: ### IGT changes ### #### Possible regressions #### * igt@kms_color@pipe-b-ctm-0-25: - shard-iclb: [PASS][1] -> [FAIL][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb2/igt@kms_color@pipe-b-ctm-0-25.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb2/igt@kms_color@pipe-b-ctm-0-25.html Known issues ------------ Here are the changes found in Patchwork_12989_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#104097]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb4/igt@i915_pm_rpm@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb6/igt@i915_pm_rpm@i2c.html * igt@i915_pm_rpm@legacy-planes-dpms: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl7/igt@i915_pm_rpm@legacy-planes-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl1/igt@i915_pm_rpm@legacy-planes-dpms.html * igt@kms_color@pipe-b-gamma: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#104782]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb1/igt@kms_color@pipe-b-gamma.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb7/igt@kms_color@pipe-b-gamma.html * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108] / [fdo#107773]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl4/igt@kms_cursor_crc@cursor-256x256-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl10/igt@kms_cursor_crc@cursor-256x256-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#102887] / [fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-x-tiled: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#108303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb8/igt@kms_flip_tiling@flip-x-tiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb8/igt@kms_flip_tiling@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk9/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-glk1/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb2/igt@kms_psr@psr2_primary_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb7/igt@kms_psr@psr2_primary_render.html * igt@kms_setmode@basic: - shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl6/igt@kms_setmode@basic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-apl3/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-c-accuracy-idle: - shard-glk: [PASS][27] -> [FAIL][28] ([fdo#102583]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk3/igt@kms_vblank@pipe-c-accuracy-idle.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-glk2/igt@kms_vblank@pipe-c-accuracy-idle.html #### Possible fixes #### * igt@i915_pm_rpm@dpms-lpsp: - shard-skl: [INCOMPLETE][29] ([fdo#107807]) -> [PASS][30] +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl1/igt@i915_pm_rpm@dpms-lpsp.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl4/igt@i915_pm_rpm@dpms-lpsp.html * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-kbl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-kbl4/igt@kms_cursor_crc@cursor-64x64-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-kbl7/igt@kms_cursor_crc@cursor-64x64-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [INCOMPLETE][33] ([fdo#109507]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible.html - shard-hsw: [INCOMPLETE][35] ([fdo#103540]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-hsw5/igt@kms_flip@flip-vs-suspend-interruptible.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip_tiling@flip-to-y-tiled: - shard-skl: [FAIL][37] ([fdo#107931] / [fdo#108134]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl10/igt@kms_flip_tiling@flip-to-y-tiled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl10/igt@kms_flip_tiling@flip-to-y-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +7 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][41] ([fdo#108145]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [FAIL][43] ([fdo#103166]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +4 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html #### Warnings #### * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-skl: [FAIL][49] ([fdo#108040]) -> [FAIL][50] ([fdo#103167]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [fdo#102583]: https://bugs.freedesktop.org/show_bug.cgi?id=102583 [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931 [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040 [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_6065 -> Patchwork_12989 CI_DRM_6065: 4ce82224f3c40ee55f11a505b57247f8f540990a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4973: 3e3ff0e48989abd25fce4916e85e8fef20a3c63a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12989: 4020491ef16ee377ff619d71ad828cf682db3ecd @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-05-09 13:40 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-05-08 19:35 [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32 Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 3/4] drm/i915: Rename ivb_load_lut_10_max Shashank Sharma 2019-05-08 19:35 ` [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support Shashank Sharma 2019-05-09 13:40 ` Ville Syrjälä 2019-05-08 20:20 ` ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL (rev3) Patchwork 2019-05-08 23:16 ` ✗ Fi.CI.IGT: failure " Patchwork
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