[PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08

[PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

  commit c5d3e39caa456b1e061644b739131f2b54c84c08
  Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
  Date:   Wed May 22 10:00:54 2019 +0100

      drm/i915: Engine discovery query

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/drm-uapi/i915_drm.h | 42 +++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index de7be1bc6b04..761517f15368 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1982,6 +1982,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -2080,6 +2081,47 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class and instance. */
+	struct i915_engine_class_instance engine;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

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[PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test the new engine discovery query.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 247 insertions(+)

diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 7d0c0e3a061c..ecbec3ae141d 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid)
 	free(topo_info);
 }
 
+static bool query_engine_info_supported(int fd)
+{
+	struct drm_i915_query_item item = {
+		.query_id = DRM_I915_QUERY_ENGINE_INFO,
+	};
+
+	return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
+}
+
+static void engines_invalid(int fd)
+{
+	struct drm_i915_query_engine_info *engines;
+	struct drm_i915_query_item item;
+	unsigned int len;
+
+	/* Flags is MBZ. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.flags = 1;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	/* Length not zero and not greater or equal required size. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = 1;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	/* Query correct length. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	i915_query_items(fd, &item, 1);
+	igt_assert(item.length >= 0);
+	len = item.length;
+
+	engines = malloc(len);
+	igt_assert(engines);
+
+	/* Ivalid pointer. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+
+	/* All fields in engines query are MBZ and only filled by the kernel. */
+
+	memset(engines, 0, len);
+	engines->num_engines = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[0] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[1] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[2] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	free(engines);
+
+	igt_assert(len <= 4096);
+	engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON,
+		       -1, 0);
+	igt_assert(engines != MAP_FAILED);
+
+	/* PROT_NONE is similar to unmapped area. */
+	memset(engines, 0, len);
+	igt_assert_eq(mprotect(engines, len, PROT_NONE), 0);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+	igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0);
+
+	/* Read-only so kernel cannot fill the data back. */
+	memset(engines, 0, len);
+	igt_assert_eq(mprotect(engines, len, PROT_READ), 0);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+
+	munmap(engines, 4096);
+}
+
+static bool
+has_engine(struct drm_i915_query_engine_info *engines,
+	   unsigned class, unsigned instance)
+{
+	unsigned int i;
+
+	for (i = 0; i < engines->num_engines; i++) {
+		struct drm_i915_engine_info *engine =
+			(struct drm_i915_engine_info *)&engines->engines[i];
+
+		if (engine->engine.engine_class == class &&
+		    engine->engine.engine_instance == instance)
+			return true;
+	}
+
+	return false;
+}
+
+static void engines(int fd)
+{
+	struct drm_i915_query_engine_info *engines;
+	struct drm_i915_query_item item;
+	unsigned int len, i;
+
+	engines = malloc(4096);
+	igt_assert(engines);
+
+	/* Query required buffer length. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert(item.length >= 0);
+	igt_assert(item.length <= 4096);
+	len = item.length;
+
+	/* Check length larger than required works and reports same length. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = 4096;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, len);
+
+	/* Actual query. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, len);
+
+	/* Every GPU has at least one engine. */
+	igt_assert(engines->num_engines > 0);
+
+	/* MBZ fields. */
+	igt_assert_eq(engines->rsvd[0], 0);
+	igt_assert_eq(engines->rsvd[1], 0);
+	igt_assert_eq(engines->rsvd[2], 0);
+
+	/* Check results match the legacy GET_PARAM (where we can). */
+	for (i = 0; i < engines->num_engines; i++) {
+		struct drm_i915_engine_info *engine =
+			(struct drm_i915_engine_info *)&engines->engines[i];
+
+		igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n",
+			  i,
+			  engine->engine.engine_class,
+			  engine->engine.engine_instance,
+			  engine->flags,
+			  engine->capabilities);
+
+		/* MBZ fields. */
+		igt_assert_eq(engine->rsvd0, 0);
+		igt_assert_eq(engine->rsvd1[0], 0);
+		igt_assert_eq(engine->rsvd1[1], 0);
+
+		switch (engine->engine.engine_class) {
+		case I915_ENGINE_CLASS_RENDER:
+			/* Will be tested later. */
+			break;
+		case I915_ENGINE_CLASS_COPY:
+			igt_assert(gem_has_blt(fd));
+			break;
+		case I915_ENGINE_CLASS_VIDEO:
+			switch (engine->engine.engine_instance) {
+			case 0:
+				igt_assert(gem_has_bsd(fd));
+				break;
+			case 1:
+				igt_assert(gem_has_bsd2(fd));
+				break;
+			}
+			break;
+		case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+			igt_assert(gem_has_vebox(fd));
+			break;
+		default:
+			igt_assert(0);
+		}
+	}
+
+	/* Reverse check to the above - all GET_PARAM engines are present. */
+	igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
+	if (gem_has_blt(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
+	if (gem_has_bsd(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
+	if (gem_has_bsd2(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
+	if (gem_has_vebox(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE,
+				       0));
+
+	free(engines);
+}
+
 igt_main
 {
 	int fd = -1;
@@ -530,6 +765,18 @@ igt_main
 		test_query_topology_known_pci_ids(fd, devid);
 	}
 
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(query_engine_info_supported(fd));
+		}
+
+		igt_subtest("engine-info-invalid")
+			engines_invalid(fd);
+
+		igt_subtest("engine-info")
+			engines(fd);
+	}
+
 	igt_fixture {
 		close(fd);
 	}
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-05-22 14:32:39)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
>   commit c5d3e39caa456b1e061644b739131f2b54c84c08
>   Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>   Date:   Wed May 22 10:00:54 2019 +0100
> 
>       drm/i915: Engine discovery query
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08

[Andi Shyti]

Hi Tvrtko,

On Wed, May 22, 2019 at 02:32:39PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
>   commit c5d3e39caa456b1e061644b739131f2b54c84c08
>   Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>   Date:   Wed May 22 10:00:54 2019 +0100
> 
>       drm/i915: Engine discovery query
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Acked-by: Andi Shyti <andi.shyti@intel.com>

Thanks,
Andi
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[PATCH i-g-t 0/2] Engine discovery tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

As usual, second patch is the only one to be looked at.

Tvrtko Ursulin (2):
  headers: bump
  tests/i915_query: Engine discovery tests

 include/drm-uapi/amdgpu_drm.h   |  52 ++++++-
 include/drm-uapi/drm.h          |  36 +++++
 include/drm-uapi/drm_mode.h     |   4 +-
 include/drm-uapi/i915_drm.h     |  42 ++++++
 include/drm-uapi/lima_drm.h     | 169 ++++++++++++++++++++++
 include/drm-uapi/msm_drm.h      |  14 ++
 include/drm-uapi/nouveau_drm.h  |  51 +++++++
 include/drm-uapi/panfrost_drm.h | 142 ++++++++++++++++++
 include/drm-uapi/v3d_drm.h      |  28 ++++
 tests/i915/i915_query.c         | 247 ++++++++++++++++++++++++++++++++
 10 files changed, 782 insertions(+), 3 deletions(-)
 create mode 100644 include/drm-uapi/lima_drm.h
 create mode 100644 include/drm-uapi/panfrost_drm.h

-- 
2.19.1

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[PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test the new engine discovery query.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 247 insertions(+)

diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 7d0c0e3a061c..ecbec3ae141d 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid)
 	free(topo_info);
 }
 
+static bool query_engine_info_supported(int fd)
+{
+	struct drm_i915_query_item item = {
+		.query_id = DRM_I915_QUERY_ENGINE_INFO,
+	};
+
+	return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
+}
+
+static void engines_invalid(int fd)
+{
+	struct drm_i915_query_engine_info *engines;
+	struct drm_i915_query_item item;
+	unsigned int len;
+
+	/* Flags is MBZ. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.flags = 1;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	/* Length not zero and not greater or equal required size. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = 1;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	/* Query correct length. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	i915_query_items(fd, &item, 1);
+	igt_assert(item.length >= 0);
+	len = item.length;
+
+	engines = malloc(len);
+	igt_assert(engines);
+
+	/* Ivalid pointer. */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+
+	/* All fields in engines query are MBZ and only filled by the kernel. */
+
+	memset(engines, 0, len);
+	engines->num_engines = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[0] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[1] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	memset(engines, 0, len);
+	engines->rsvd[2] = 1;
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EINVAL);
+
+	free(engines);
+
+	igt_assert(len <= 4096);
+	engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON,
+		       -1, 0);
+	igt_assert(engines != MAP_FAILED);
+
+	/* PROT_NONE is similar to unmapped area. */
+	memset(engines, 0, len);
+	igt_assert_eq(mprotect(engines, len, PROT_NONE), 0);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+	igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0);
+
+	/* Read-only so kernel cannot fill the data back. */
+	memset(engines, 0, len);
+	igt_assert_eq(mprotect(engines, len, PROT_READ), 0);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -EFAULT);
+
+	munmap(engines, 4096);
+}
+
+static bool
+has_engine(struct drm_i915_query_engine_info *engines,
+	   unsigned class, unsigned instance)
+{
+	unsigned int i;
+
+	for (i = 0; i < engines->num_engines; i++) {
+		struct drm_i915_engine_info *engine =
+			(struct drm_i915_engine_info *)&engines->engines[i];
+
+		if (engine->engine.engine_class == class &&
+		    engine->engine.engine_instance == instance)
+			return true;
+	}
+
+	return false;
+}
+
+static void engines(int fd)
+{
+	struct drm_i915_query_engine_info *engines;
+	struct drm_i915_query_item item;
+	unsigned int len, i;
+
+	engines = malloc(4096);
+	igt_assert(engines);
+
+	/* Query required buffer length. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert(item.length >= 0);
+	igt_assert(item.length <= 4096);
+	len = item.length;
+
+	/* Check length larger than required works and reports same length. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = 4096;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, len);
+
+	/* Actual query. */
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = len;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, len);
+
+	/* Every GPU has at least one engine. */
+	igt_assert(engines->num_engines > 0);
+
+	/* MBZ fields. */
+	igt_assert_eq(engines->rsvd[0], 0);
+	igt_assert_eq(engines->rsvd[1], 0);
+	igt_assert_eq(engines->rsvd[2], 0);
+
+	/* Check results match the legacy GET_PARAM (where we can). */
+	for (i = 0; i < engines->num_engines; i++) {
+		struct drm_i915_engine_info *engine =
+			(struct drm_i915_engine_info *)&engines->engines[i];
+
+		igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n",
+			  i,
+			  engine->engine.engine_class,
+			  engine->engine.engine_instance,
+			  engine->flags,
+			  engine->capabilities);
+
+		/* MBZ fields. */
+		igt_assert_eq(engine->rsvd0, 0);
+		igt_assert_eq(engine->rsvd1[0], 0);
+		igt_assert_eq(engine->rsvd1[1], 0);
+
+		switch (engine->engine.engine_class) {
+		case I915_ENGINE_CLASS_RENDER:
+			/* Will be tested later. */
+			break;
+		case I915_ENGINE_CLASS_COPY:
+			igt_assert(gem_has_blt(fd));
+			break;
+		case I915_ENGINE_CLASS_VIDEO:
+			switch (engine->engine.engine_instance) {
+			case 0:
+				igt_assert(gem_has_bsd(fd));
+				break;
+			case 1:
+				igt_assert(gem_has_bsd2(fd));
+				break;
+			}
+			break;
+		case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+			igt_assert(gem_has_vebox(fd));
+			break;
+		default:
+			igt_assert(0);
+		}
+	}
+
+	/* Reverse check to the above - all GET_PARAM engines are present. */
+	igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
+	if (gem_has_blt(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
+	if (gem_has_bsd(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
+	if (gem_has_bsd2(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
+	if (gem_has_vebox(fd))
+		igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE,
+				       0));
+
+	free(engines);
+}
+
 igt_main
 {
 	int fd = -1;
@@ -530,6 +765,18 @@ igt_main
 		test_query_topology_known_pci_ids(fd, devid);
 	}
 
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(query_engine_info_supported(fd));
+		}
+
+		igt_subtest("engine-info-invalid")
+			engines_invalid(fd);
+
+		igt_subtest("engine-info")
+			engines(fd);
+	}
+
 	igt_fixture {
 		close(fd);
 	}
-- 
2.19.1

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Re: [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-05-01 12:42:59)
> +               switch (engine->engine.engine_class) {
> +               case I915_ENGINE_CLASS_RENDER:
> +                       /* Will be tested later. */
> +                       break;
> +               case I915_ENGINE_CLASS_COPY:
> +                       igt_assert(gem_has_blt(fd));
> +                       break;
> +               case I915_ENGINE_CLASS_VIDEO:
> +                       switch (engine->engine.engine_instance) {
> +                       case 0:
> +                               igt_assert(gem_has_bsd(fd));
> +                               break;
> +                       case 1:
> +                               igt_assert(gem_has_bsd2(fd));
> +                               break;


Is that relationship a given?

One could argue that gem_has_blt() means that I915_EXEC_BLT works, but
without !gem_has_blt() we could still access CLASS_COPY:0 via
ctx->engines[].

> +                       }
> +                       break;
> +               case I915_ENGINE_CLASS_VIDEO_ENHANCE:
> +                       igt_assert(gem_has_vebox(fd));
> +                       break;
> +               default:
> +                       igt_assert(0);
> +               }
> +       }
> +
> +       /* Reverse check to the above - all GET_PARAM engines are present. */
> +       igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
> +       if (gem_has_blt(fd))
> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
> +       if (gem_has_bsd(fd))
> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
> +       if (gem_has_bsd2(fd))
> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
> +       if (gem_has_vebox(fd))
> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE,
> +                                      0));

Whereas this should always make sense, given the legacy interface and
the modern interface, the modern interface should be a superset of the
legacy.

Just thinking aloud.
-Chris
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Re: [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests

[Tvrtko Ursulin]

On 01/05/2019 12:52, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-05-01 12:42:59)
>> +               switch (engine->engine.engine_class) {
>> +               case I915_ENGINE_CLASS_RENDER:
>> +                       /* Will be tested later. */
>> +                       break;
>> +               case I915_ENGINE_CLASS_COPY:
>> +                       igt_assert(gem_has_blt(fd));
>> +                       break;
>> +               case I915_ENGINE_CLASS_VIDEO:
>> +                       switch (engine->engine.engine_instance) {
>> +                       case 0:
>> +                               igt_assert(gem_has_bsd(fd));
>> +                               break;
>> +                       case 1:
>> +                               igt_assert(gem_has_bsd2(fd));
>> +                               break;
> 
> 
> Is that relationship a given?
> 
> One could argue that gem_has_blt() means that I915_EXEC_BLT works, but
> without !gem_has_blt() we could still access CLASS_COPY:0 via
> ctx->engines[].

"without !gem_has_blt()".. hmmm what do you mean? If you mean 
gem_has_blt() is false but bcs:0 is still accessible via ctx->engines[] 
then how?

>> +                       }
>> +                       break;
>> +               case I915_ENGINE_CLASS_VIDEO_ENHANCE:
>> +                       igt_assert(gem_has_vebox(fd));
>> +                       break;
>> +               default:
>> +                       igt_assert(0);
>> +               }
>> +       }
>> +
>> +       /* Reverse check to the above - all GET_PARAM engines are present. */
>> +       igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
>> +       if (gem_has_blt(fd))
>> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
>> +       if (gem_has_bsd(fd))
>> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
>> +       if (gem_has_bsd2(fd))
>> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
>> +       if (gem_has_vebox(fd))
>> +               igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE,
>> +                                      0));
> 
> Whereas this should always make sense, given the legacy interface and
> the modern interface, the modern interface should be a superset of the
> legacy.
> 
> Just thinking aloud.

Sure, no harm in looking at it again. The test was written long time ago.

Regards,

Tvrtko
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