[PATCH v4 0/3] drm/i915: CTS fixes

[PATCH v4 0/3] drm/i915: CTS fixes

[Lionel Landwerlin]

Hi,

Adding a selftest fix for read only registers.

Cheers,

Lionel Landwerlin (3):
  drm/i915: fix whitelist selftests with readonly registers
  drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
  drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

 drivers/gpu/drm/i915/gt/intel_workarounds.c    | 16 +++++++++++++++-
 drivers/gpu/drm/i915/gt/selftest_workarounds.c |  3 +++
 2 files changed, 18 insertions(+), 1 deletion(-)

--
2.21.0.392.gf8f6787159e
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[PATCH v4 1/3] drm/i915: fix whitelist selftests with readonly registers

[Lionel Landwerlin]

When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :

   KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f12cb20fe785..801a94516bae 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -926,6 +926,9 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
 
 	err = 0;
 	for (i = 0; i < engine->whitelist.count; i++) {
+		if (engine->whitelist.list[i].reg & RING_FORCE_TO_NONPRIV_RD)
+			continue;
+
 		if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
 			err = -EINVAL;
 	}
-- 
2.21.0.392.gf8f6787159e

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[PATCH v4 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

[Lionel Landwerlin]

CFL:C0+ changed the status of those registers which are now
blacklisted by default.

This is breaking a number of CTS tests on GL & Vulkan :

  KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)

  dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 993804d09517..da7d48ac4ee7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1092,10 +1092,18 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
 
 static void cfl_whitelist_build(struct intel_engine_cs *engine)
 {
+	struct i915_wa_list *w = &engine->whitelist;
+
 	if (engine->class != RENDER_CLASS)
 		return;
 
-	gen9_whitelist_build(&engine->whitelist);
+	gen9_whitelist_build(w);
+
+	/* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml */
+	whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_DEPTH_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_INVOCATION_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
 }
 
 static void cnl_whitelist_build(struct intel_engine_cs *engine)
-- 
2.21.0.392.gf8f6787159e

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[PATCH v4 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

[Lionel Landwerlin]

The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index da7d48ac4ee7..9a19980cceb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1131,6 +1131,12 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 
 		/* WaEnableStateCacheRedirectToCS:icl */
 		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+
+		/* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl */
+		whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_DEPTH_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
 		break;
 
 	case VIDEO_DECODE_CLASS:
-- 
2.21.0.392.gf8f6787159e

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✗ Fi.CI.BAT: failure for drm/i915: CTS fixes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: CTS fixes (rev4)
URL   : https://patchwork.freedesktop.org/series/62437/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  AR      drivers/gpu/drm/i915/built-in.a
  CC [M]  drivers/gpu/drm/i915/header_test_i915_active_types.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_debugfs.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_drv.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_gem_gtt.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_irq.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_params.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_priolist_types.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_reg.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_scheduler_types.o
  CC [M]  drivers/gpu/drm/i915/header_test_i915_utils.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_csr.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_drv.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_pm.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_runtime_pm.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_sideband.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_uncore.o
  CC [M]  drivers/gpu/drm/i915/header_test_intel_wakeref.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_workarounds.o
In file included from drivers/gpu/drm/i915/gt/intel_workarounds.c:1489:0:
drivers/gpu/drm/i915/gt/selftest_workarounds.c: In function ‘check_whitelisted_registers’:
drivers/gpu/drm/i915/gt/selftest_workarounds.c:929:37: error: invalid operands to binary & (have ‘i915_reg_t {aka struct <anonymous>}’ and ‘int’)
   if (engine->whitelist.list[i].reg & RING_FORCE_TO_NONPRIV_RD)
       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^
scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/gt/intel_workarounds.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_workarounds.o] Error 1
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1071: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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