* [PATCH v2 1/6] drm/i915: Pass intel_crtc_state to needs_modeset()
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 2/6] drm/i915: Convert most of atomic commit to take more intel state Maarten Lankhorst
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
In i915 we should use intel_crtc_state as much as possible, pass
intel_crtc_state to needs_modeset, before we clean up all other uses
of drm_crtc_state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 68 ++++++++++----------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e55bd75528c1..90701d86fbeb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -515,9 +515,9 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
}
static bool
-needs_modeset(const struct drm_crtc_state *state)
+needs_modeset(const struct intel_crtc_state *state)
{
- return drm_atomic_crtc_needs_modeset(state);
+ return drm_atomic_crtc_needs_modeset(&state->base);
}
/*
@@ -5796,7 +5796,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
if (!old_crtc_state->ips_enabled)
return false;
- if (needs_modeset(&new_crtc_state->base))
+ if (needs_modeset(new_crtc_state))
return true;
/*
@@ -5823,7 +5823,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
if (!new_crtc_state->ips_enabled)
return false;
- if (needs_modeset(&new_crtc_state->base))
+ if (needs_modeset(new_crtc_state))
return true;
/*
@@ -5900,7 +5900,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
intel_fbc_post_update(crtc);
if (new_primary_state->visible &&
- (needs_modeset(&pipe_config->base) ||
+ (needs_modeset(pipe_config) ||
!old_primary_state->visible))
intel_post_enable_primary(&crtc->base, pipe_config);
}
@@ -5924,7 +5924,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_primary_state =
drm_atomic_get_old_plane_state(old_state, primary);
- bool modeset = needs_modeset(&pipe_config->base);
+ bool modeset = needs_modeset(pipe_config);
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
@@ -5984,7 +5984,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* If we're doing a modeset, we're done. No need to do any pre-vblank
* watermark programming here.
*/
- if (needs_modeset(&pipe_config->base))
+ if (needs_modeset(pipe_config))
return;
/*
@@ -11339,7 +11339,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
struct intel_plane *plane = to_intel_plane(plane_state->plane);
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = needs_modeset(pipe_config);
bool was_crtc_enabled = old_crtc_state->base.active;
bool is_crtc_enabled = crtc_state->active;
bool turn_off, turn_on, visible, was_visible;
@@ -11608,7 +11608,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc_state);
int ret;
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = needs_modeset(pipe_config);
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
mode_changed && !crtc_state->active)
@@ -13088,7 +13088,7 @@ intel_modeset_verify_crtc(struct drm_crtc *crtc,
struct drm_crtc_state *old_state,
struct drm_crtc_state *new_state)
{
- if (!needs_modeset(new_state) &&
+ if (!needs_modeset(to_intel_crtc_state(new_state)) &&
!to_intel_crtc_state(new_state)->update_pipe)
return;
@@ -13180,7 +13180,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
struct intel_shared_dpll *old_dpll =
old_crtc_state->shared_dpll;
- if (!needs_modeset(&new_crtc_state->base))
+ if (!needs_modeset(new_crtc_state))
continue;
new_crtc_state->shared_dpll = NULL;
@@ -13210,7 +13210,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
/* look at all crtc's that are going to be enabled in during modeset */
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->base.active ||
- !needs_modeset(&crtc_state->base))
+ !needs_modeset(crtc_state))
continue;
if (first_crtc_state) {
@@ -13235,7 +13235,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
if (!crtc_state->base.active ||
- needs_modeset(&crtc_state->base))
+ needs_modeset(crtc_state))
continue;
/* 2 or more enabled crtcs means no need for w/a */
@@ -13285,7 +13285,7 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
- if (!crtc_state->active || needs_modeset(crtc_state))
+ if (!crtc_state->active || needs_modeset(to_intel_crtc_state(crtc_state)))
continue;
crtc_state->mode_changed = true;
@@ -13362,12 +13362,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
}
if (is_power_of_2(state->active_crtcs)) {
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
pipe = ilog2(state->active_crtcs);
- crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
- crtc_state = drm_atomic_get_new_crtc_state(&state->base, crtc);
+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
if (crtc_state && needs_modeset(crtc_state))
pipe = INVALID_PIPE;
} else {
@@ -13478,7 +13478,7 @@ static int intel_atomic_check(struct drm_device *dev,
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(&new_crtc_state->base))
+ if (!needs_modeset(new_crtc_state))
continue;
if (!new_crtc_state->base.enable) {
@@ -13492,7 +13492,7 @@ static int intel_atomic_check(struct drm_device *dev,
intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
- if (needs_modeset(&new_crtc_state->base))
+ if (needs_modeset(new_crtc_state))
any_ms = true;
}
@@ -13527,12 +13527,12 @@ static int intel_atomic_check(struct drm_device *dev,
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(&new_crtc_state->base) &&
+ if (!needs_modeset(new_crtc_state) &&
!new_crtc_state->update_pipe)
continue;
intel_dump_pipe_config(new_crtc_state, state,
- needs_modeset(&new_crtc_state->base) ?
+ needs_modeset(new_crtc_state) ?
"[modeset]" : "[fastset]");
}
@@ -13579,7 +13579,7 @@ static void intel_update_crtc(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
- bool modeset = needs_modeset(new_crtc_state);
+ bool modeset = needs_modeset(pipe_config);
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
to_intel_plane(crtc->primary));
@@ -13788,15 +13788,15 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
intel_crtc = to_intel_crtc(crtc);
- if (needs_modeset(new_crtc_state) ||
- to_intel_crtc_state(new_crtc_state)->update_pipe) {
+ if (needs_modeset(new_intel_crtc_state) ||
+ new_intel_crtc_state->update_pipe) {
put_domains[intel_crtc->pipe] =
modeset_get_crtc_power_domains(crtc,
new_intel_crtc_state);
}
- if (!needs_modeset(new_crtc_state))
+ if (!needs_modeset(new_intel_crtc_state))
continue;
intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
@@ -13855,7 +13855,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
/* Complete the events for pipes that have now been disabled */
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
- bool modeset = needs_modeset(new_crtc_state);
+ bool modeset = needs_modeset(to_intel_crtc_state(new_crtc_state));
/* Complete events for now disable pipes here. */
if (modeset && !new_crtc_state->active && new_crtc_state->event) {
@@ -13891,7 +13891,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
if (new_crtc_state->active &&
- !needs_modeset(new_crtc_state) &&
+ !needs_modeset(to_intel_crtc_state(new_crtc_state)) &&
(new_intel_crtc_state->base.color_mgmt_changed ||
new_intel_crtc_state->update_pipe))
intel_color_load_luts(new_intel_crtc_state);
@@ -14238,9 +14238,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
int ret;
if (old_obj) {
- struct drm_crtc_state *crtc_state =
- drm_atomic_get_new_crtc_state(new_state->state,
- plane->state->crtc);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(intel_state,
+ to_intel_crtc(plane->state->crtc));
/* Big Hammer, we also need to ensure that any pending
* MI_WAIT_FOR_EVENT inside a user batch buffer on the
@@ -14401,7 +14401,7 @@ static void intel_begin_crtc_commit(struct intel_atomic_state *state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- bool modeset = needs_modeset(&new_crtc_state->base);
+ bool modeset = needs_modeset(new_crtc_state);
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(new_crtc_state);
@@ -14454,7 +14454,7 @@ static void intel_finish_crtc_commit(struct intel_atomic_state *state,
intel_pipe_update_end(new_crtc_state);
if (new_crtc_state->update_pipe &&
- !needs_modeset(&new_crtc_state->base) &&
+ !needs_modeset(new_crtc_state) &&
old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
@@ -14568,7 +14568,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
* When crtc is inactive or there is a modeset pending,
* wait for it to complete in the slowpath
*/
- if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
+ if (!crtc_state->base.active || needs_modeset(crtc_state) ||
crtc_state->update_pipe)
goto slow;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/6] drm/i915: Convert most of atomic commit to take more intel state
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 1/6] drm/i915: Pass intel_crtc_state to needs_modeset() Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 3/6] drm/i915: Convert hw state verifier to take more intel state, v2 Maarten Lankhorst
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
Instead of passing along drm_crtc_state and drm_atomic_state, pass
along more intel_atomic_state and intel_crtc_state. This will
make the code more readable by not casting between drm state
and intel state all the time.
While at it, rename old_state to state, with the get_new/old helpers
there is no point in distinguishing between state before and after
swapping state any more. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 429 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 11 +-
drivers/gpu/drm/i915/intel_pm.h | 4 +-
4 files changed, 209 insertions(+), 241 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 90701d86fbeb..f411f57bcacb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5877,13 +5877,13 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *old_state = old_crtc_state->base.state;
+ struct drm_atomic_state *state = old_crtc_state->base.state;
struct intel_crtc_state *pipe_config =
- intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
+ intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
crtc);
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_primary_state =
- drm_atomic_get_old_plane_state(old_state, primary);
+ drm_atomic_get_old_plane_state(state, primary);
intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
@@ -5895,7 +5895,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
if (old_primary_state) {
struct drm_plane_state *new_primary_state =
- drm_atomic_get_new_plane_state(old_state, primary);
+ drm_atomic_get_new_plane_state(state, primary);
intel_fbc_post_update(crtc);
@@ -5920,20 +5920,20 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *old_state = old_crtc_state->base.state;
+ struct drm_atomic_state *state = old_crtc_state->base.state;
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_primary_state =
- drm_atomic_get_old_plane_state(old_state, primary);
+ drm_atomic_get_old_plane_state(state, primary);
bool modeset = needs_modeset(pipe_config);
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_state);
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
hsw_disable_ips(old_crtc_state);
if (old_primary_state) {
struct intel_plane_state *new_primary_state =
- intel_atomic_get_new_plane_state(old_intel_state,
+ intel_atomic_get_new_plane_state(intel_state,
to_intel_plane(primary));
intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
@@ -6002,7 +6002,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* us to.
*/
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(old_intel_state,
+ dev_priv->display.initial_watermarks(intel_state,
pipe_config);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
@@ -6036,19 +6036,19 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, fb_bits);
}
-static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
+static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
- for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(conn_state->best_encoder);
- if (conn_state->crtc != crtc)
+ if (conn_state->crtc != &crtc->base)
continue;
if (encoder->pre_pll_enable)
@@ -6056,19 +6056,19 @@ static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_pre_enable(struct drm_crtc *crtc,
+static void intel_encoders_pre_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
- for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(conn_state->best_encoder);
- if (conn_state->crtc != crtc)
+ if (conn_state->crtc != &crtc->base)
continue;
if (encoder->pre_enable)
@@ -6076,19 +6076,19 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_enable(struct drm_crtc *crtc,
+static void intel_encoders_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
- for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(conn_state->best_encoder);
- if (conn_state->crtc != crtc)
+ if (conn_state->crtc != &crtc->base)
continue;
if (encoder->enable)
@@ -6097,19 +6097,19 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_disable(struct drm_crtc *crtc,
+static void intel_encoders_disable(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
- for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
+ for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(old_conn_state->best_encoder);
- if (old_conn_state->crtc != crtc)
+ if (old_conn_state->crtc != &crtc->base)
continue;
intel_opregion_notify_encoder(encoder, false);
@@ -6118,19 +6118,19 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_post_disable(struct drm_crtc *crtc,
+static void intel_encoders_post_disable(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
- for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
+ for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(old_conn_state->best_encoder);
- if (old_conn_state->crtc != crtc)
+ if (old_conn_state->crtc != &crtc->base)
continue;
if (encoder->post_disable)
@@ -6138,19 +6138,19 @@ static void intel_encoders_post_disable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
+static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
- for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
+ for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(old_conn_state->best_encoder);
- if (old_conn_state->crtc != crtc)
+ if (old_conn_state->crtc != &crtc->base)
continue;
if (encoder->post_pll_disable)
@@ -6158,19 +6158,19 @@ static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
}
}
-static void intel_encoders_update_pipe(struct drm_crtc *crtc,
+static void intel_encoders_update_pipe(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
- for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(conn_state->best_encoder);
- if (conn_state->crtc != crtc)
+ if (conn_state->crtc != &crtc->base)
continue;
if (encoder->update_pipe)
@@ -6187,15 +6187,13 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
}
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_state);
if (WARN_ON(intel_crtc->active))
return;
@@ -6231,7 +6229,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- intel_encoders_pre_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_enable(intel_crtc, pipe_config, state);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6255,16 +6253,16 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
+ dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
- ironlake_pch_enable(old_intel_state, pipe_config);
+ ironlake_pch_enable(state, pipe_config);
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(crtc, pipe_config, old_state);
+ intel_encoders_enable(intel_crtc, pipe_config, state);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6317,26 +6315,24 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
}
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_state);
bool psl_clkgate_wa;
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_enable(intel_crtc, pipe_config, state);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6394,7 +6390,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
+ dev_priv->display.initial_watermarks(state, pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc);
@@ -6404,7 +6400,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
- lpt_pch_enable(old_intel_state, pipe_config);
+ lpt_pch_enable(state, pipe_config);
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(pipe_config, true);
@@ -6412,7 +6408,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(crtc, pipe_config, old_state);
+ intel_encoders_enable(intel_crtc, pipe_config, state);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6444,7 +6440,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_device *dev = crtc->dev;
@@ -6460,7 +6456,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_disable(intel_crtc, old_crtc_state, state);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6472,7 +6468,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (old_crtc_state->has_pch_encoder)
ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6503,14 +6499,14 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
}
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_disable(intel_crtc, old_crtc_state, state);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6532,9 +6528,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
- intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -6633,14 +6629,13 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
}
}
-static u64 get_crtc_power_domains(struct drm_crtc *crtc,
+static u64 get_crtc_power_domains(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_encoder *encoder;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum pipe pipe = crtc->pipe;
u64 mask;
enum transcoder transcoder = crtc_state->cpu_transcoder;
@@ -6669,16 +6664,15 @@ static u64 get_crtc_power_domains(struct drm_crtc *crtc,
}
static u64
-modeset_get_crtc_power_domains(struct drm_crtc *crtc,
+modeset_get_crtc_power_domains(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain domain;
u64 domains, new_domains, old_domains;
- old_domains = intel_crtc->enabled_power_domains;
- intel_crtc->enabled_power_domains = new_domains =
+ old_domains = crtc->enabled_power_domains;
+ crtc->enabled_power_domains = new_domains =
get_crtc_power_domains(crtc, crtc_state);
domains = new_domains & ~old_domains;
@@ -6699,10 +6693,8 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
}
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_state);
struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -6729,7 +6721,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, pipe_config);
@@ -6739,7 +6731,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
vlv_enable_pll(intel_crtc, pipe_config);
}
- intel_encoders_pre_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_enable(intel_crtc, pipe_config, state);
i9xx_pfit_enable(pipe_config);
@@ -6748,14 +6740,13 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(old_intel_state,
- pipe_config);
+ dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(crtc, pipe_config, old_state);
+ intel_encoders_enable(intel_crtc, pipe_config, state);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -6768,10 +6759,8 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
}
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_state);
struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -6796,7 +6785,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(crtc, pipe_config, old_state);
+ intel_encoders_pre_enable(intel_crtc, pipe_config, state);
i9xx_enable_pll(intel_crtc, pipe_config);
@@ -6808,7 +6797,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(old_intel_state,
+ dev_priv->display.initial_watermarks(state,
pipe_config);
else
intel_update_watermarks(intel_crtc);
@@ -6817,7 +6806,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(crtc, pipe_config, old_state);
+ intel_encoders_enable(intel_crtc, pipe_config, state);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -6836,7 +6825,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state)
+ struct intel_atomic_state *state)
{
struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_device *dev = crtc->dev;
@@ -6851,7 +6840,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_disable(intel_crtc, old_crtc_state, state);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6860,7 +6849,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -6871,7 +6860,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
+ intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -6925,7 +6914,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
WARN_ON(IS_ERR(crtc_state) || ret);
- dev_priv->display.crtc_disable(crtc_state, state);
+ dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
drm_atomic_state_put(state);
@@ -12931,15 +12920,15 @@ verify_crtc_state(struct drm_crtc *crtc,
struct intel_encoder *encoder;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *pipe_config, *sw_config;
- struct drm_atomic_state *old_state;
+ struct drm_atomic_state *state;
bool active;
- old_state = old_crtc_state->state;
+ state = old_crtc_state->state;
__drm_atomic_helper_crtc_destroy_state(old_crtc_state);
pipe_config = to_intel_crtc_state(old_crtc_state);
memset(pipe_config, 0, sizeof(*pipe_config));
pipe_config->base.crtc = crtc;
- pipe_config->base.state = old_state;
+ pipe_config->base.state = state;
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
@@ -13083,19 +13072,18 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
}
static void
-intel_modeset_verify_crtc(struct drm_crtc *crtc,
- struct drm_atomic_state *state,
- struct drm_crtc_state *old_state,
- struct drm_crtc_state *new_state)
+intel_modeset_verify_crtc(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_state,
+ struct intel_crtc_state *new_state)
{
- if (!needs_modeset(to_intel_crtc_state(new_state)) &&
- !to_intel_crtc_state(new_state)->update_pipe)
+ if (!needs_modeset(new_state) && !new_state->update_pipe)
return;
- verify_wm_state(crtc, new_state);
- verify_connector_state(crtc->dev, state, crtc);
- verify_crtc_state(crtc, old_state, new_state);
- verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
+ verify_wm_state(&crtc->base, &new_state->base);
+ verify_connector_state(crtc->base.dev, &state->base, &crtc->base);
+ verify_crtc_state(&crtc->base, &old_state->base, &new_state->base);
+ verify_shared_dpll_state(crtc->base.dev, &crtc->base, &old_state->base, &new_state->base);
}
static void
@@ -13110,10 +13098,10 @@ verify_disabled_dpll_state(struct drm_device *dev)
static void
intel_modeset_verify_disabled(struct drm_device *dev,
- struct drm_atomic_state *state)
+ struct intel_atomic_state *state)
{
- verify_encoder_state(dev, state);
- verify_connector_state(dev, state, NULL);
+ verify_encoder_state(dev, &state->base);
+ verify_connector_state(dev, &state->base, NULL);
verify_disabled_dpll_state(dev);
}
@@ -13570,57 +13558,54 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
return crtc->base.funcs->get_vblank_counter(&crtc->base);
}
-static void intel_update_crtc(struct drm_crtc *crtc,
- struct drm_atomic_state *state,
- struct drm_crtc_state *old_crtc_state,
- struct drm_crtc_state *new_crtc_state)
+static void intel_update_crtc(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
- bool modeset = needs_modeset(pipe_config);
+ bool modeset = needs_modeset(new_crtc_state);
struct intel_plane_state *new_plane_state =
- intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
- to_intel_plane(crtc->primary));
+ intel_atomic_get_new_plane_state(state,
+ to_intel_plane(crtc->base.primary));
if (modeset) {
- update_scanline_offset(pipe_config);
- dev_priv->display.crtc_enable(pipe_config, state);
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
/* vblanks work again, re-enable pipe CRC. */
- intel_crtc_enable_pipe_crc(intel_crtc);
+ intel_crtc_enable_pipe_crc(crtc);
} else {
- intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
- pipe_config);
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (pipe_config->update_pipe)
- intel_encoders_update_pipe(crtc, pipe_config, state);
+ if (new_crtc_state->update_pipe)
+ intel_encoders_update_pipe(crtc, new_crtc_state, state);
}
- if (pipe_config->update_pipe && !pipe_config->enable_fbc)
- intel_fbc_disable(intel_crtc);
+ if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
+ intel_fbc_disable(crtc);
else if (new_plane_state)
- intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+ intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
- intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc);
+ intel_begin_crtc_commit(state, crtc);
if (INTEL_GEN(dev_priv) >= 9)
- skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
+ skl_update_planes_on_crtc(state, crtc);
else
- i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
+ i9xx_update_planes_on_crtc(state, crtc);
- intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc);
+ intel_finish_crtc_commit(state, crtc);
}
-static void intel_update_crtcs(struct drm_atomic_state *state)
+static void intel_update_crtcs(struct intel_atomic_state *state)
{
- struct drm_crtc *crtc;
- struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
int i;
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
- if (!new_crtc_state->active)
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (!new_crtc_state->base.active)
continue;
intel_update_crtc(crtc, state, old_crtc_state,
@@ -13628,26 +13613,23 @@ static void intel_update_crtcs(struct drm_atomic_state *state)
}
}
-static void skl_update_crtcs(struct drm_atomic_state *state)
+static void skl_update_crtcs(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->dev);
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct drm_crtc *crtc;
- struct intel_crtc *intel_crtc;
- struct drm_crtc_state *old_crtc_state, *new_crtc_state;
- struct intel_crtc_state *cstate;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
unsigned int updated = 0;
bool progress;
enum pipe pipe;
int i;
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
+ u8 required_slices = state->wm_results.ddb.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
/* ignore allocations for crtc's that have been turned off. */
- if (new_crtc_state->active)
- entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
+ if (new_crtc_state->base.active)
+ entries[i] = old_crtc_state->wm.skl.ddb;
/* If 2nd DBuf slice required, enable it here */
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
@@ -13662,24 +13644,22 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
do {
progress = false;
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
bool vbl_wait = false;
- unsigned int cmask = drm_crtc_mask(crtc);
+ unsigned int cmask = drm_crtc_mask(&crtc->base);
- intel_crtc = to_intel_crtc(crtc);
- cstate = to_intel_crtc_state(new_crtc_state);
- pipe = intel_crtc->pipe;
+ pipe = crtc->pipe;
- if (updated & cmask || !cstate->base.active)
+ if (updated & cmask || !new_crtc_state->base.active)
continue;
- if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
+ if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
entries,
INTEL_INFO(dev_priv)->num_pipes, i))
continue;
updated |= cmask;
- entries[i] = cstate->wm.skl.ddb;
+ entries[i] = new_crtc_state->wm.skl.ddb;
/*
* If this is an already active pipe, it's DDB changed,
@@ -13687,10 +13667,10 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
- &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
- !new_crtc_state->active_changed &&
- intel_state->wm_results.dirty_pipes != updated)
+ if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
+ &old_crtc_state->wm.skl.ddb) &&
+ !new_crtc_state->base.active_changed &&
+ state->wm_results.dirty_pipes != updated)
vbl_wait = true;
intel_update_crtc(crtc, state, old_crtc_state,
@@ -13763,57 +13743,50 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
-static void intel_atomic_commit_tail(struct drm_atomic_state *state)
+static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
- struct drm_device *dev = state->dev;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_crtc_state *old_crtc_state, *new_crtc_state;
- struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
- struct drm_crtc *crtc;
- struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
u64 put_domains[I915_MAX_PIPES] = {};
intel_wakeref_t wakeref = 0;
int i;
- intel_atomic_commit_fence_wait(intel_state);
+ intel_atomic_commit_fence_wait(state);
- drm_atomic_helper_wait_for_dependencies(state);
+ drm_atomic_helper_wait_for_dependencies(&state->base);
- if (intel_state->modeset)
+ if (state->modeset)
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
- old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
- new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
- intel_crtc = to_intel_crtc(crtc);
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (needs_modeset(new_crtc_state) ||
+ new_crtc_state->update_pipe) {
- if (needs_modeset(new_intel_crtc_state) ||
- new_intel_crtc_state->update_pipe) {
-
- put_domains[intel_crtc->pipe] =
+ put_domains[crtc->pipe] =
modeset_get_crtc_power_domains(crtc,
- new_intel_crtc_state);
+ new_crtc_state);
}
- if (!needs_modeset(new_intel_crtc_state))
+ if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->active) {
- intel_crtc_disable_planes(intel_state, intel_crtc);
+ if (old_crtc_state->base.active) {
+ intel_crtc_disable_planes(state, crtc);
/*
* We need to disable pipe CRC before disabling the pipe,
* or we race against vblank off.
*/
- intel_crtc_disable_pipe_crc(intel_crtc);
+ intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(old_intel_crtc_state, state);
- intel_crtc->active = false;
- intel_fbc_disable(intel_crtc);
- intel_disable_shared_dpll(old_intel_crtc_state);
+ dev_priv->display.crtc_disable(old_crtc_state, state);
+ crtc->active = false;
+ intel_fbc_disable(crtc);
+ intel_disable_shared_dpll(old_crtc_state);
/*
* Underruns don't always raise
@@ -13823,25 +13796,25 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
intel_check_pch_fifo_underruns(dev_priv);
/* FIXME unify this for all platforms */
- if (!new_crtc_state->active &&
+ if (!new_crtc_state->base.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(intel_state,
- new_intel_crtc_state);
+ dev_priv->display.initial_watermarks(state,
+ new_crtc_state);
}
}
- /* FIXME: Eventually get rid of our intel_crtc->config pointer */
- for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
- to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
+ /* FIXME: Eventually get rid of our crtc->config pointer */
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+ crtc->config = new_crtc_state;
- if (intel_state->modeset) {
- drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
+ if (state->modeset) {
+ drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
intel_set_cdclk_pre_plane_update(dev_priv,
- &intel_state->cdclk.actual,
+ &state->cdclk.actual,
&dev_priv->cdclk.actual,
- intel_state->cdclk.pipe);
+ state->cdclk.pipe);
/*
* SKL workaround: bspec recommends we disable the SAGV when we
@@ -13854,27 +13827,27 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
}
/* Complete the events for pipes that have now been disabled */
- for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
- bool modeset = needs_modeset(to_intel_crtc_state(new_crtc_state));
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ bool modeset = needs_modeset(new_crtc_state);
/* Complete events for now disable pipes here. */
- if (modeset && !new_crtc_state->active && new_crtc_state->event) {
+ if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
spin_lock_irq(&dev->event_lock);
- drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
+ drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
spin_unlock_irq(&dev->event_lock);
- new_crtc_state->event = NULL;
+ new_crtc_state->base.event = NULL;
}
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.update_crtcs(state);
- if (intel_state->modeset)
+ if (state->modeset)
intel_set_cdclk_post_plane_update(dev_priv,
- &intel_state->cdclk.actual,
+ &state->cdclk.actual,
&dev_priv->cdclk.actual,
- intel_state->cdclk.pipe);
+ state->cdclk.pipe);
/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
* already, but still need the state for the delayed optimization. To
@@ -13885,16 +13858,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
* - switch over to the vblank wait helper in the core after that since
* we don't need out special handling any more.
*/
- drm_atomic_helper_wait_for_flip_done(dev, state);
+ drm_atomic_helper_wait_for_flip_done(dev, &state->base);
- for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
- new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
-
- if (new_crtc_state->active &&
- !needs_modeset(to_intel_crtc_state(new_crtc_state)) &&
- (new_intel_crtc_state->base.color_mgmt_changed ||
- new_intel_crtc_state->update_pipe))
- intel_color_load_luts(new_intel_crtc_state);
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->base.active &&
+ !needs_modeset(new_crtc_state) &&
+ (new_crtc_state->base.color_mgmt_changed ||
+ new_crtc_state->update_pipe))
+ intel_color_load_luts(new_crtc_state);
}
/*
@@ -13904,16 +13875,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
*
* TODO: Move this (and other cleanup) to an async worker eventually.
*/
- for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
- new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
-
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(intel_state,
- new_intel_crtc_state);
+ dev_priv->display.optimize_watermarks(state,
+ new_crtc_state);
}
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
- intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ intel_post_plane_update(old_crtc_state);
if (put_domains[i])
modeset_put_power_domains(dev_priv, put_domains[i]);
@@ -13921,15 +13890,15 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
}
- if (intel_state->modeset)
- intel_verify_planes(intel_state);
+ if (state->modeset)
+ intel_verify_planes(state);
- if (intel_state->modeset && intel_can_enable_sagv(state))
+ if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
- drm_atomic_helper_commit_hw_done(state);
+ drm_atomic_helper_commit_hw_done(&state->base);
- if (intel_state->modeset) {
+ if (state->modeset) {
/* As one of the primary mmio accessors, KMS has a high
* likelihood of triggering bugs in unclaimed access. After we
* finish modesetting, see if an error has been flagged, and if
@@ -13939,7 +13908,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
}
- intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);
+ intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
/*
* Defer the cleanup of the old state to a separate worker to not
@@ -13949,14 +13918,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
* schedule point (cond_resched()) here anyway to keep latencies
* down.
*/
- INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
- queue_work(system_highpri_wq, &state->commit_work);
+ INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
+ queue_work(system_highpri_wq, &state->base.commit_work);
}
static void intel_atomic_commit_work(struct work_struct *work)
{
- struct drm_atomic_state *state =
- container_of(work, struct drm_atomic_state, commit_work);
+ struct intel_atomic_state *state =
+ container_of(work, struct intel_atomic_state, base.commit_work);
intel_atomic_commit_tail(state);
}
@@ -14099,7 +14068,7 @@ static int intel_atomic_commit(struct drm_device *dev,
} else {
if (intel_state->modeset)
flush_workqueue(dev_priv->modeset_wq);
- intel_atomic_commit_tail(state);
+ intel_atomic_commit_tail(intel_state);
}
return 0;
@@ -16878,7 +16847,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
u64 put_domains;
crtc_state = to_intel_crtc_state(crtc->base.state);
- put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
+ put_domains = modeset_get_crtc_power_domains(crtc, crtc_state);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e981b03face..7d9ae234a02e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -307,10 +307,10 @@ struct drm_i915_display_funcs {
int (*crtc_compute_clock)(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_crtc_state *pipe_config,
- struct drm_atomic_state *old_state);
+ struct intel_atomic_state *old_state);
void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- struct drm_atomic_state *old_state);
- void (*update_crtcs)(struct drm_atomic_state *state);
+ struct intel_atomic_state *old_state);
+ void (*update_crtcs)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9a7a13ce32a..4116de2a77fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3736,11 +3736,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct drm_atomic_state *state)
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
{
- struct drm_device *dev = state->dev;
+ struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *cstate;
@@ -3761,18 +3760,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
/*
* If there are no active CRTCs, no additional checks need be performed
*/
- if (hweight32(intel_state->active_crtcs) == 0)
+ if (hweight32(state->active_crtcs) == 0)
return true;
/*
* SKL+ workaround: bspec recommends we disable SAGV when we have
* more then one pipe enabled
*/
- if (hweight32(intel_state->active_crtcs) > 1)
+ if (hweight32(state->active_crtcs) > 1)
return false;
/* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(intel_state->active_crtcs) - 1;
+ pipe = ffs(state->active_crtcs) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
cstate = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 1b489fa399e1..e3573e1e16e3 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -10,10 +10,10 @@
#include "i915_reg.h"
-struct drm_atomic_state;
struct drm_device;
struct drm_i915_private;
struct i915_request;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
@@ -52,7 +52,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct drm_atomic_state *state);
+bool intel_can_enable_sagv(struct intel_atomic_state *state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/6] drm/i915: Convert hw state verifier to take more intel state, v2.
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 1/6] drm/i915: Pass intel_crtc_state to needs_modeset() Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 2/6] drm/i915: Convert most of atomic commit to take more intel state Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 4/6] drm/i915: Use intel_crtc_state in sanitize_watermarks() too Maarten Lankhorst
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
Like the rest of the intel atomic functions we should pass along
intel_crtc_state, and dereference drm_crtc_state only through
intel_crtc_state->base
While at it, rename old/new_state to old/new_crtc_state. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 160 +++++++++----------
1 file changed, 77 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f411f57bcacb..6be2fd714e37 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6977,7 +6977,7 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
/* Cross check the actual hw state with our own modeset state tracking (and it's
* internal consistency). */
-static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
+static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
@@ -6995,7 +6995,7 @@ static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
if (!crtc_state)
return;
- I915_STATE_WARN(!crtc_state->active,
+ I915_STATE_WARN(!crtc_state->base.active,
"connector is active, but attached crtc isn't\n");
if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
@@ -7007,7 +7007,7 @@ static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
"attached encoder crtc differs from connector crtc\n");
} else {
- I915_STATE_WARN(crtc_state && crtc_state->active,
+ I915_STATE_WARN(crtc_state && crtc_state->base.active,
"attached crtc is active, but connector isn't\n");
I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
"best encoder set without crtc!\n");
@@ -12695,10 +12695,10 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
}
}
-static void verify_wm_state(struct drm_crtc *crtc,
- struct drm_crtc_state *new_state)
+static void verify_wm_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *new_crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
@@ -12708,21 +12708,20 @@ static void verify_wm_state(struct drm_crtc *crtc,
struct skl_ddb_allocation *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- const enum pipe pipe = intel_crtc->pipe;
+ const enum pipe pipe = crtc->pipe;
int plane, level, max_level = ilk_wm_max_level(dev_priv);
- if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
+ if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
return;
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
if (!hw)
return;
- skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
- sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
+ skl_pipe_wm_get_hw_state(crtc, &hw->wm);
+ sw_wm = &new_crtc_state->wm.skl.optimal;
- skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
+ skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
skl_ddb_get_hw_state(dev_priv, &hw->ddb);
sw_ddb = &dev_priv->wm.skl_hw.ddb;
@@ -12770,7 +12769,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
/* DDB */
hw_ddb_entry = &hw->ddb_y[plane];
- sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
+ sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
@@ -12822,7 +12821,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
/* DDB */
hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
- sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
+ sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
@@ -12836,23 +12835,22 @@ static void verify_wm_state(struct drm_crtc *crtc,
}
static void
-verify_connector_state(struct drm_device *dev,
- struct drm_atomic_state *state,
- struct drm_crtc *crtc)
+verify_connector_state(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct drm_connector *connector;
struct drm_connector_state *new_conn_state;
int i;
- for_each_new_connector_in_state(state, connector, new_conn_state, i) {
+ for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
struct drm_encoder *encoder = connector->encoder;
- struct drm_crtc_state *crtc_state = NULL;
+ struct intel_crtc_state *crtc_state = NULL;
- if (new_conn_state->crtc != crtc)
+ if (new_conn_state->crtc != &crtc->base)
continue;
if (crtc)
- crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
intel_connector_verify_state(crtc_state, new_conn_state);
@@ -12862,14 +12860,14 @@ verify_connector_state(struct drm_device *dev,
}
static void
-verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
+verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
{
struct intel_encoder *encoder;
struct drm_connector *connector;
struct drm_connector_state *old_conn_state, *new_conn_state;
int i;
- for_each_intel_encoder(dev, encoder) {
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
bool enabled = false, found = false;
enum pipe pipe;
@@ -12877,7 +12875,7 @@ verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
encoder->base.base.id,
encoder->base.name);
- for_each_oldnew_connector_in_state(state, connector, old_conn_state,
+ for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
new_conn_state, i) {
if (old_conn_state->best_encoder == &encoder->base)
found = true;
@@ -12911,50 +12909,49 @@ verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
}
static void
-verify_crtc_state(struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state,
- struct drm_crtc_state *new_crtc_state)
+verify_crtc_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_encoder *encoder;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *pipe_config, *sw_config;
+ struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
bool active;
- state = old_crtc_state->state;
- __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
- pipe_config = to_intel_crtc_state(old_crtc_state);
+ state = old_crtc_state->base.state;
+ __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
+ pipe_config = old_crtc_state;
memset(pipe_config, 0, sizeof(*pipe_config));
- pipe_config->base.crtc = crtc;
+ pipe_config->base.crtc = &crtc->base;
pipe_config->base.state = state;
- DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
+ DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
- active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
+ active = dev_priv->display.get_pipe_config(crtc, pipe_config);
/* we keep both pipes enabled on 830 */
if (IS_I830(dev_priv))
- active = new_crtc_state->active;
+ active = new_crtc_state->base.active;
- I915_STATE_WARN(new_crtc_state->active != active,
+ I915_STATE_WARN(new_crtc_state->base.active != active,
"crtc active state doesn't match with hw state "
- "(expected %i, found %i)\n", new_crtc_state->active, active);
+ "(expected %i, found %i)\n", new_crtc_state->base.active, active);
- I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
+ I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
"transitional active state does not match atomic hw state "
- "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
+ "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
- for_each_encoder_on_crtc(dev, crtc, encoder) {
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
enum pipe pipe;
active = encoder->get_hw_state(encoder, &pipe);
- I915_STATE_WARN(active != new_crtc_state->active,
+ I915_STATE_WARN(active != new_crtc_state->base.active,
"[ENCODER:%i] active %i with crtc active %i\n",
- encoder->base.base.id, active, new_crtc_state->active);
+ encoder->base.base.id, active, new_crtc_state->base.active);
- I915_STATE_WARN(active && intel_crtc->pipe != pipe,
+ I915_STATE_WARN(active && crtc->pipe != pipe,
"Encoder connected to wrong pipe %c\n",
pipe_name(pipe));
@@ -12964,16 +12961,16 @@ verify_crtc_state(struct drm_crtc *crtc,
intel_crtc_compute_pixel_rate(pipe_config);
- if (!new_crtc_state->active)
+ if (!new_crtc_state->base.active)
return;
intel_pipe_config_sanity_check(dev_priv, pipe_config);
- sw_config = to_intel_crtc_state(new_crtc_state);
- if (!intel_pipe_config_compare(sw_config, pipe_config, false)) {
+ if (!intel_pipe_config_compare(new_crtc_state,
+ pipe_config, false)) {
I915_STATE_WARN(1, "pipe state doesn't match!\n");
intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
- intel_dump_pipe_config(sw_config, NULL, "[sw state]");
+ intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
}
}
@@ -12993,8 +12990,8 @@ intel_verify_planes(struct intel_atomic_state *state)
static void
verify_single_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
- struct drm_crtc *crtc,
- struct drm_crtc_state *new_state)
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *new_crtc_state)
{
struct intel_dpll_hw_state dpll_hw_state;
unsigned int crtc_mask;
@@ -13024,16 +13021,16 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
return;
}
- crtc_mask = drm_crtc_mask(crtc);
+ crtc_mask = drm_crtc_mask(&crtc->base);
- if (new_state->active)
+ if (new_crtc_state->base.active)
I915_STATE_WARN(!(pll->active_mask & crtc_mask),
"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
- pipe_name(drm_crtc_index(crtc)), pll->active_mask);
+ pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
else
I915_STATE_WARN(pll->active_mask & crtc_mask,
"pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
- pipe_name(drm_crtc_index(crtc)), pll->active_mask);
+ pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
"pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
@@ -13046,50 +13043,47 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
}
static void
-verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state,
- struct drm_crtc_state *new_crtc_state)
+verify_shared_dpll_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
- struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (new_state->shared_dpll)
- verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
+ if (new_crtc_state->shared_dpll)
+ verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
- if (old_state->shared_dpll &&
- old_state->shared_dpll != new_state->shared_dpll) {
- unsigned int crtc_mask = drm_crtc_mask(crtc);
- struct intel_shared_dpll *pll = old_state->shared_dpll;
+ if (old_crtc_state->shared_dpll &&
+ old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+ unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
+ struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
I915_STATE_WARN(pll->active_mask & crtc_mask,
"pll active mismatch (didn't expect pipe %c in active mask)\n",
- pipe_name(drm_crtc_index(crtc)));
+ pipe_name(drm_crtc_index(&crtc->base)));
I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
"pll enabled crtcs mismatch (found %x in enabled mask)\n",
- pipe_name(drm_crtc_index(crtc)));
+ pipe_name(drm_crtc_index(&crtc->base)));
}
}
static void
intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_atomic_state *state,
- struct intel_crtc_state *old_state,
- struct intel_crtc_state *new_state)
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
{
- if (!needs_modeset(new_state) && !new_state->update_pipe)
+ if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
return;
- verify_wm_state(&crtc->base, &new_state->base);
- verify_connector_state(crtc->base.dev, &state->base, &crtc->base);
- verify_crtc_state(&crtc->base, &old_state->base, &new_state->base);
- verify_shared_dpll_state(crtc->base.dev, &crtc->base, &old_state->base, &new_state->base);
+ verify_wm_state(crtc, new_crtc_state);
+ verify_connector_state(state, crtc);
+ verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
+ verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
}
static void
-verify_disabled_dpll_state(struct drm_device *dev)
+verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
int i;
for (i = 0; i < dev_priv->num_shared_dpll; i++)
@@ -13097,12 +13091,12 @@ verify_disabled_dpll_state(struct drm_device *dev)
}
static void
-intel_modeset_verify_disabled(struct drm_device *dev,
+intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state)
{
- verify_encoder_state(dev, &state->base);
- verify_connector_state(dev, &state->base, NULL);
- verify_disabled_dpll_state(dev);
+ verify_encoder_state(dev_priv, state);
+ verify_connector_state(state, NULL);
+ verify_disabled_dpll_state(dev_priv);
}
static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
@@ -13823,7 +13817,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (!intel_can_enable_sagv(state))
intel_disable_sagv(dev_priv);
- intel_modeset_verify_disabled(dev, state);
+ intel_modeset_verify_disabled(dev_priv, state);
}
/* Complete the events for pipes that have now been disabled */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 4/6] drm/i915: Use intel_crtc_state in sanitize_watermarks() too
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (2 preceding siblings ...)
2019-06-28 8:55 ` [PATCH v2 3/6] drm/i915: Convert hw state verifier to take more intel state, v2 Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 5/6] drm/i915: Pass intel state to plane functions as well Maarten Lankhorst
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
Get rid of all instances of drm_crtc_state, and rename cstate to
crtc_state for more clarity.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6be2fd714e37..4ea63026d9c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15812,8 +15812,8 @@ static void sanitize_watermarks(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *state;
struct intel_atomic_state *intel_state;
- struct drm_crtc *crtc;
- struct drm_crtc_state *cstate;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
struct drm_modeset_acquire_ctx ctx;
int ret;
int i;
@@ -15868,13 +15868,11 @@ static void sanitize_watermarks(struct drm_device *dev)
}
/* Write calculated watermark values back */
- for_each_new_crtc_in_state(state, crtc, cstate, i) {
- struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
-
- cs->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, cs);
+ for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
+ crtc_state->wm.need_postvbl_update = true;
+ dev_priv->display.optimize_watermarks(intel_state, crtc_state);
- to_intel_crtc_state(crtc->state)->wm = cs->wm;
+ to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
put_state:
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/6] drm/i915: Pass intel state to plane functions as well
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (3 preceding siblings ...)
2019-06-28 8:55 ` [PATCH v2 4/6] drm/i915: Use intel_crtc_state in sanitize_watermarks() too Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-06-28 8:55 ` [PATCH v2 6/6] drm/i915: Use intel state as much as possible in wm code Maarten Lankhorst
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
Pass along the correct state as much as possible, instead of relying
on the drm state internally. This is required to rely on hw state
internally soon.
While at it, clean up intel_plane_atomic_check slightly, by using a
helper function to get the intel_crtc. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 56 +++++++++++-------
.../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++----------
3 files changed, 64 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 30bd4e76fff9..ab411d5e093c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -176,33 +176,49 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
new_crtc_state->data_rate[plane->id] =
intel_plane_data_rate(new_crtc_state, new_plane_state);
- return intel_plane_atomic_calc_changes(old_crtc_state,
- &new_crtc_state->base,
- old_plane_state,
- &new_plane_state->base);
+ return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
+ old_plane_state, new_plane_state);
}
-static int intel_plane_atomic_check(struct drm_plane *plane,
- struct drm_plane_state *new_plane_state)
+static struct intel_crtc *
+get_crtc_from_states(const struct intel_plane_state *old_plane_state,
+ const struct intel_plane_state *new_plane_state)
{
- struct drm_atomic_state *state = new_plane_state->state;
- const struct drm_plane_state *old_plane_state =
- drm_atomic_get_old_plane_state(state, plane);
- struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
- const struct drm_crtc_state *old_crtc_state;
- struct drm_crtc_state *new_crtc_state;
-
- new_plane_state->visible = false;
+ if (new_plane_state->base.crtc)
+ return to_intel_crtc(new_plane_state->base.crtc);
+
+ if (old_plane_state->base.crtc)
+ return to_intel_crtc(old_plane_state->base.crtc);
+
+ return NULL;
+}
+
+static int intel_plane_atomic_check(struct drm_plane *_plane,
+ struct drm_plane_state *_new_plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(_plane);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(_new_plane_state->state);
+ struct intel_plane_state *new_plane_state =
+ to_intel_plane_state(_new_plane_state);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ struct intel_crtc *crtc =
+ get_crtc_from_states(old_plane_state, new_plane_state);
+ const struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
+
+ new_plane_state->base.visible = false;
if (!crtc)
return 0;
- old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
- new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
- return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
- to_intel_crtc_state(new_crtc_state),
- to_intel_plane_state(old_plane_state),
- to_intel_plane_state(new_plane_state));
+ return intel_plane_atomic_check_with_state(old_crtc_state,
+ new_crtc_state,
+ old_plane_state,
+ new_plane_state);
}
static struct intel_plane *
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 1437a8797e10..cb7ef4f9eafd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -8,7 +8,6 @@
#include <linux/types.h>
-struct drm_crtc_state;
struct drm_plane;
struct drm_property;
struct intel_atomic_state;
@@ -43,8 +42,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *intel_state);
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
- struct drm_crtc_state *crtc_state,
+ struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
- struct drm_plane_state *plane_state);
+ struct intel_plane_state *plane_state);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4ea63026d9c4..c97c0a9f6208 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11286,7 +11286,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
*
* Returns true or false.
*/
-static bool intel_wm_need_update(struct intel_plane_state *cur,
+static bool intel_wm_need_update(const struct intel_plane_state *cur,
struct intel_plane_state *new)
{
/* Update watermarks on tiling or size changes. */
@@ -11318,33 +11318,28 @@ static bool needs_scaling(const struct intel_plane_state *state)
}
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
- struct drm_crtc_state *crtc_state,
+ struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
- struct drm_plane_state *plane_state)
+ struct intel_plane_state *plane_state)
{
- struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
- struct drm_crtc *crtc = crtc_state->crtc;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_plane *plane = to_intel_plane(plane_state->plane);
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- bool mode_changed = needs_modeset(pipe_config);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ bool mode_changed = needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->base.active;
- bool is_crtc_enabled = crtc_state->active;
+ bool is_crtc_enabled = crtc_state->base.active;
bool turn_off, turn_on, visible, was_visible;
- struct drm_framebuffer *fb = plane_state->fb;
+ struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
- ret = skl_update_scaler_plane(
- to_intel_crtc_state(crtc_state),
- to_intel_plane_state(plane_state));
+ ret = skl_update_scaler_plane(crtc_state, plane_state);
if (ret)
return ret;
}
was_visible = old_plane_state->base.visible;
- visible = plane_state->visible;
+ visible = plane_state->base.visible;
if (!was_crtc_enabled && WARN_ON(was_visible))
was_visible = false;
@@ -11360,22 +11355,22 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
* only combine the results from all planes in the current place?
*/
if (!is_crtc_enabled) {
- plane_state->visible = visible = false;
- to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
- to_intel_crtc_state(crtc_state)->data_rate[plane->id] = 0;
+ plane_state->base.visible = visible = false;
+ crtc_state->active_planes &= ~BIT(plane->id);
+ crtc_state->data_rate[plane->id] = 0;
}
if (!was_visible && !visible)
return 0;
if (fb != old_plane_state->base.fb)
- pipe_config->fb_changed = true;
+ crtc_state->fb_changed = true;
turn_off = was_visible && (!visible || mode_changed);
turn_on = visible && (!was_visible || mode_changed);
DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
- intel_crtc->base.base.id, intel_crtc->base.name,
+ crtc->base.base.id, crtc->base.name,
plane->base.base.id, plane->base.name,
fb ? fb->base.id : -1);
@@ -11386,29 +11381,28 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
if (turn_on) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
- pipe_config->update_wm_pre = true;
+ crtc_state->update_wm_pre = true;
/* must disable cxsr around plane enable/disable */
if (plane->id != PLANE_CURSOR)
- pipe_config->disable_cxsr = true;
+ crtc_state->disable_cxsr = true;
} else if (turn_off) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
- pipe_config->update_wm_post = true;
+ crtc_state->update_wm_post = true;
/* must disable cxsr around plane enable/disable */
if (plane->id != PLANE_CURSOR)
- pipe_config->disable_cxsr = true;
- } else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
- to_intel_plane_state(plane_state))) {
+ crtc_state->disable_cxsr = true;
+ } else if (intel_wm_need_update(old_plane_state, plane_state)) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
/* FIXME bollocks */
- pipe_config->update_wm_pre = true;
- pipe_config->update_wm_post = true;
+ crtc_state->update_wm_pre = true;
+ crtc_state->update_wm_post = true;
}
}
if (visible || was_visible)
- pipe_config->fb_bits |= plane->frontbuffer_bit;
+ crtc_state->fb_bits |= plane->frontbuffer_bit;
/*
* ILK/SNB DVSACNTR/Sprite Enable
@@ -11447,8 +11441,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
(IS_GEN_RANGE(dev_priv, 5, 6) ||
IS_IVYBRIDGE(dev_priv)) &&
(turn_on || (!needs_scaling(old_plane_state) &&
- needs_scaling(to_intel_plane_state(plane_state)))))
- pipe_config->disable_lp_wm = true;
+ needs_scaling(plane_state))))
+ crtc_state->disable_lp_wm = true;
return 0;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 6/6] drm/i915: Use intel state as much as possible in wm code
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (4 preceding siblings ...)
2019-06-28 8:55 ` [PATCH v2 5/6] drm/i915: Pass intel state to plane functions as well Maarten Lankhorst
@ 2019-06-28 8:55 ` Maarten Lankhorst
2019-07-01 8:34 ` Maarten Lankhorst
2019-06-28 9:21 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use intel_crtc_state everywhere! Patchwork
` (3 subsequent siblings)
9 siblings, 1 reply; 12+ messages in thread
From: Maarten Lankhorst @ 2019-06-28 8:55 UTC (permalink / raw)
To: intel-gfx
Instead of directly referencing drm_crtc_state, convert to
intel_ctc_state and use the base struct. This is useful when we're
making the split between uapi and hw state, and also makes the
code slightly more readable.
A lot of places also use cstate, instead of the more common crtc_state.
Clean those up to use crtc_state. Same for pstate vs plane_state. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 12 +-
drivers/gpu/drm/i915/intel_pm.c | 402 +++++++++++++++-----------------
2 files changed, 200 insertions(+), 214 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d9ae234a02e..02dd9f9f3a89 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -287,14 +287,14 @@ struct drm_i915_display_funcs {
enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
- int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
- int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
+ int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
+ int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate);
+ struct intel_crtc_state *crtc_state);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate);
+ struct intel_crtc_state *crtc_state);
void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate);
+ struct intel_crtc_state *crtc_state);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
@@ -1646,7 +1646,7 @@ struct drm_i915_private {
/*
* Should be held around atomic WM register writing; also
* protects * intel_crtc->wm.active and
- * cstate->wm.need_postvbl_update.
+ * crtc_state->wm.need_postvbl_update.
*/
struct mutex wm_mutex;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4116de2a77fd..d10c62d3f10c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1198,8 +1198,8 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
return dirty;
}
-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
u32 pri_val);
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
@@ -2493,8 +2493,8 @@ struct ilk_wm_maximums {
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
+static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
u32 mem_value, bool is_lp)
{
u32 method1, method2;
@@ -2503,19 +2503,19 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
if (mem_value == 0)
return U32_MAX;
- if (!intel_wm_plane_visible(cstate, pstate))
+ if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = pstate->base.fb->format->cpp[0];
+ cpp = plane_state->base.fb->format->cpp[0];
- method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
+ method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
if (!is_lp)
return method1;
- method2 = ilk_wm_method2(cstate->pixel_rate,
- cstate->base.adjusted_mode.crtc_htotal,
- drm_rect_width(&pstate->base.dst),
+ method2 = ilk_wm_method2(crtc_state->pixel_rate,
+ crtc_state->base.adjusted_mode.crtc_htotal,
+ drm_rect_width(&plane_state->base.dst),
cpp, mem_value);
return min(method1, method2);
@@ -2525,8 +2525,8 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
+static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
u32 mem_value)
{
u32 method1, method2;
@@ -2535,15 +2535,15 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
if (mem_value == 0)
return U32_MAX;
- if (!intel_wm_plane_visible(cstate, pstate))
+ if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = pstate->base.fb->format->cpp[0];
+ cpp = plane_state->base.fb->format->cpp[0];
- method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
- method2 = ilk_wm_method2(cstate->pixel_rate,
- cstate->base.adjusted_mode.crtc_htotal,
- drm_rect_width(&pstate->base.dst),
+ method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
+ method2 = ilk_wm_method2(crtc_state->pixel_rate,
+ crtc_state->base.adjusted_mode.crtc_htotal,
+ drm_rect_width(&plane_state->base.dst),
cpp, mem_value);
return min(method1, method2);
}
@@ -2552,8 +2552,8 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
+static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
u32 mem_value)
{
int cpp;
@@ -2561,29 +2561,29 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
if (mem_value == 0)
return U32_MAX;
- if (!intel_wm_plane_visible(cstate, pstate))
+ if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = pstate->base.fb->format->cpp[0];
+ cpp = plane_state->base.fb->format->cpp[0];
- return ilk_wm_method2(cstate->pixel_rate,
- cstate->base.adjusted_mode.crtc_htotal,
- pstate->base.crtc_w, cpp, mem_value);
+ return ilk_wm_method2(crtc_state->pixel_rate,
+ crtc_state->base.adjusted_mode.crtc_htotal,
+ plane_state->base.crtc_w, cpp, mem_value);
}
/* Only for WM_LP. */
-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
u32 pri_val)
{
int cpp;
- if (!intel_wm_plane_visible(cstate, pstate))
+ if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = pstate->base.fb->format->cpp[0];
+ cpp = plane_state->base.fb->format->cpp[0];
- return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
+ return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
}
static unsigned int
@@ -2752,7 +2752,7 @@ static bool ilk_validate_wm_level(int level,
static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_crtc *intel_crtc,
int level,
- struct intel_crtc_state *cstate,
+ struct intel_crtc_state *crtc_state,
const struct intel_plane_state *pristate,
const struct intel_plane_state *sprstate,
const struct intel_plane_state *curstate,
@@ -2770,30 +2770,30 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
}
if (pristate) {
- result->pri_val = ilk_compute_pri_wm(cstate, pristate,
+ result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
pri_latency, level);
- result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
+ result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
}
if (sprstate)
- result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
+ result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
if (curstate)
- result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
+ result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
result->enable = true;
}
static u32
-hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
+hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
{
const struct intel_atomic_state *intel_state =
- to_intel_atomic_state(cstate->base.state);
+ to_intel_atomic_state(crtc_state->base.state);
const struct drm_display_mode *adjusted_mode =
- &cstate->base.adjusted_mode;
+ &crtc_state->base.adjusted_mode;
u32 linetime, ips_linetime;
- if (!cstate->base.active)
+ if (!crtc_state->base.active)
return 0;
if (WARN_ON(adjusted_mode->crtc_clock == 0))
return 0;
@@ -3101,10 +3101,10 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
}
/* Compute new watermarks for the pipe */
-static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
+static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct drm_atomic_state *state = cstate->base.state;
- struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct intel_pipe_wm *pipe_wm;
struct drm_device *dev = state->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3116,9 +3116,9 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
struct ilk_wm_maximums max;
- pipe_wm = &cstate->wm.ilk.optimal;
+ pipe_wm = &crtc_state->wm.ilk.optimal;
- drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
@@ -3129,7 +3129,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
curstate = ps;
}
- pipe_wm->pipe_enabled = cstate->base.active;
+ pipe_wm->pipe_enabled = crtc_state->base.active;
if (sprstate) {
pipe_wm->sprites_enabled = sprstate->base.visible;
pipe_wm->sprites_scaled = sprstate->base.visible &&
@@ -3148,11 +3148,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
usable_level = 0;
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
- ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
+ ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
+ pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3162,7 +3162,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
for (level = 1; level <= usable_level; level++) {
struct intel_wm_level *wm = &pipe_wm->wm[level];
- ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
+ ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
pristate, sprstate, curstate, wm);
/*
@@ -3742,7 +3742,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
- struct intel_crtc_state *cstate;
+ struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
int sagv_block_time_us;
@@ -3773,14 +3773,14 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
/* Since we're now guaranteed to only have one active CRTC... */
pipe = ffs(state->active_crtcs) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- cstate = to_intel_crtc_state(crtc->base.state);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
- &cstate->wm.skl.optimal.planes[plane->id];
+ &crtc_state->wm.skl.optimal.planes[plane->id];
/* Skip this plane if it's not enabled */
if (!wm->wm[0].plane_en)
@@ -3811,7 +3811,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
}
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *cstate,
+ const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
const int num_active,
struct skl_ddb_allocation *ddb)
@@ -3825,7 +3825,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &cstate->base.adjusted_mode;
+ adjusted_mode = &crtc_state->base.adjusted_mode;
total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
/*
@@ -3848,23 +3848,22 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *cstate,
+ const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
- struct drm_atomic_state *state = cstate->base.state;
+ struct drm_atomic_state *state = crtc_state->base.state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct drm_crtc *for_crtc = cstate->base.crtc;
- const struct drm_crtc_state *crtc_state;
- const struct drm_crtc *crtc;
+ struct drm_crtc *for_crtc = crtc_state->base.crtc;
+ const struct intel_crtc *crtc;
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
u32 i;
- if (WARN_ON(!state) || !cstate->base.active) {
+ if (WARN_ON(!state) || !crtc_state->base.active) {
alloc->start = 0;
alloc->end = 0;
*num_active = hweight32(dev_priv->active_crtcs);
@@ -3876,7 +3875,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
else
*num_active = hweight32(dev_priv->active_crtcs);
- ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
+ ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
*num_active, ddb);
/*
@@ -3901,16 +3900,15 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
- for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
- const struct drm_display_mode *adjusted_mode;
+ for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
- enum pipe pipe;
- if (!crtc_state->enable)
+ if (!crtc_state->base.enable)
continue;
- pipe = to_intel_crtc(crtc)->pipe;
- adjusted_mode = &crtc_state->adjusted_mode;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
total_width += hdisplay;
@@ -3929,7 +3927,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane);
-static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
+static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
@@ -4061,15 +4059,15 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
* Caller should take care of dividing & rounding off the value.
*/
static uint_fixed_16_16_t
-skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate)
+skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(pstate->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 src_w, src_h, dst_w, dst_h;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
- if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
+ if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
return u32_to_fixed16(0);
/* n.b., src is 16.16 fixed point, dst is whole integer */
@@ -4078,20 +4076,20 @@ skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
* Cursors only support 0/180 degree rotation,
* hence no need to account for rotation here.
*/
- src_w = pstate->base.src_w >> 16;
- src_h = pstate->base.src_h >> 16;
- dst_w = pstate->base.crtc_w;
- dst_h = pstate->base.crtc_h;
+ src_w = plane_state->base.src_w >> 16;
+ src_h = plane_state->base.src_h >> 16;
+ dst_w = plane_state->base.crtc_w;
+ dst_h = plane_state->base.crtc_h;
} else {
/*
* Src coordinates are already rotated by 270 degrees for
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- src_w = drm_rect_width(&pstate->base.src) >> 16;
- src_h = drm_rect_height(&pstate->base.src) >> 16;
- dst_w = drm_rect_width(&pstate->base.dst);
- dst_h = drm_rect_height(&pstate->base.dst);
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ dst_w = drm_rect_width(&plane_state->base.dst);
+ dst_h = drm_rect_height(&plane_state->base.dst);
}
fp_w_ratio = div_fixed16(src_w, dst_w);
@@ -4136,49 +4134,46 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
}
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *cstate)
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct drm_crtc_state *crtc_state = &cstate->base;
- struct drm_atomic_state *state = crtc_state->state;
+ struct drm_atomic_state *state = crtc_state->base.state;
struct drm_plane *plane;
- const struct drm_plane_state *pstate;
- struct intel_plane_state *intel_pstate;
+ const struct drm_plane_state *drm_plane_state;
int crtc_clock, dotclk;
u32 pipe_max_pixel_rate;
uint_fixed_16_16_t pipe_downscale;
uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
- if (!cstate->base.enable)
+ if (!crtc_state->base.enable)
return 0;
- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
uint_fixed_16_16_t plane_downscale;
uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
int bpp;
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(drm_plane_state);
- if (!intel_wm_plane_visible(cstate,
- to_intel_plane_state(pstate)))
+ if (!intel_wm_plane_visible(crtc_state, plane_state))
continue;
- if (WARN_ON(!pstate->fb))
+ if (WARN_ON(!plane_state->base.fb))
return -EINVAL;
- intel_pstate = to_intel_plane_state(pstate);
- plane_downscale = skl_plane_downscale_amount(cstate,
- intel_pstate);
- bpp = pstate->fb->format->cpp[0] * 8;
+ plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
+ bpp = plane_state->base.fb->format->cpp[0] * 8;
if (bpp == 64)
plane_downscale = mul_fixed16(plane_downscale,
fp_9_div_8);
max_downscale = max_fixed16(plane_downscale, max_downscale);
}
- pipe_downscale = skl_pipe_downscale_amount(cstate);
+ pipe_downscale = skl_pipe_downscale_amount(crtc_state);
pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
- crtc_clock = crtc_state->adjusted_mode.crtc_clock;
+ crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
@@ -4195,12 +4190,11 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
}
static u64
-skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *intel_pstate,
+skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
const int plane)
{
- struct intel_plane *intel_plane =
- to_intel_plane(intel_pstate->base.plane);
+ struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
u32 data_rate;
u32 width = 0, height = 0;
struct drm_framebuffer *fb;
@@ -4208,10 +4202,10 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
uint_fixed_16_16_t down_scale_amount;
u64 rate;
- if (!intel_pstate->base.visible)
+ if (!plane_state->base.visible)
return 0;
- fb = intel_pstate->base.fb;
+ fb = plane_state->base.fb;
format = fb->format->format;
if (intel_plane->id == PLANE_CURSOR)
@@ -4224,8 +4218,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- width = drm_rect_width(&intel_pstate->base.src) >> 16;
- height = drm_rect_height(&intel_pstate->base.src) >> 16;
+ width = drm_rect_width(&plane_state->base.src) >> 16;
+ height = drm_rect_height(&plane_state->base.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
if (plane == 1 && is_planar_yuv_format(format)) {
@@ -4235,7 +4229,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
data_rate = width * height;
- down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
+ down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4244,35 +4238,32 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
}
static u64
-skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
+skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate,
u64 *uv_plane_data_rate)
{
- struct drm_crtc_state *cstate = &intel_cstate->base;
- struct drm_atomic_state *state = cstate->state;
+ struct drm_atomic_state *state = crtc_state->base.state;
struct drm_plane *plane;
- const struct drm_plane_state *pstate;
+ const struct drm_plane_state *drm_plane_state;
u64 total_data_rate = 0;
if (WARN_ON(!state))
return 0;
/* Calculate and cache data rate for each plane */
- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
enum plane_id plane_id = to_intel_plane(plane)->id;
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(drm_plane_state);
u64 rate;
- const struct intel_plane_state *intel_pstate =
- to_intel_plane_state(pstate);
/* packed/y */
- rate = skl_plane_relative_data_rate(intel_cstate,
- intel_pstate, 0);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
/* uv-plane */
- rate = skl_plane_relative_data_rate(intel_cstate,
- intel_pstate, 1);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4281,28 +4272,25 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
}
static u64
-icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
+icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate)
{
- struct drm_crtc_state *cstate = &intel_cstate->base;
- struct drm_atomic_state *state = cstate->state;
struct drm_plane *plane;
- const struct drm_plane_state *pstate;
+ const struct drm_plane_state *drm_plane_state;
u64 total_data_rate = 0;
- if (WARN_ON(!state))
+ if (WARN_ON(!crtc_state->base.state))
return 0;
/* Calculate and cache data rate for each plane */
- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
- const struct intel_plane_state *intel_pstate =
- to_intel_plane_state(pstate);
+ drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(drm_plane_state);
enum plane_id plane_id = to_intel_plane(plane)->id;
u64 rate;
- if (!intel_pstate->linked_plane) {
- rate = skl_plane_relative_data_rate(intel_cstate,
- intel_pstate, 0);
+ if (!plane_state->linked_plane) {
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
} else {
@@ -4315,18 +4303,16 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
* NULL if we try get_new_plane_state(), so we
* always calculate from the master.
*/
- if (intel_pstate->slave)
+ if (plane_state->slave)
continue;
/* Y plane rate is calculated on the slave */
- rate = skl_plane_relative_data_rate(intel_cstate,
- intel_pstate, 0);
- y_plane_id = intel_pstate->linked_plane->id;
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
+ y_plane_id = plane_state->linked_plane->id;
plane_data_rate[y_plane_id] = rate;
total_data_rate += rate;
- rate = skl_plane_relative_data_rate(intel_cstate,
- intel_pstate, 1);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4336,14 +4322,14 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
}
static int
-skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
+skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
{
- struct drm_atomic_state *state = cstate->base.state;
- struct drm_crtc *crtc = cstate->base.crtc;
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_crtc *crtc = crtc_state->base.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
u16 alloc_size, start = 0;
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
@@ -4356,40 +4342,40 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int level;
/* Clear the partitioning for disabled planes. */
- memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
- memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
+ memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
+ memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
if (WARN_ON(!state))
return 0;
- if (!cstate->base.active) {
+ if (!crtc_state->base.active) {
alloc->start = alloc->end = 0;
return 0;
}
if (INTEL_GEN(dev_priv) >= 11)
total_data_rate =
- icl_get_total_relative_data_rate(cstate,
+ icl_get_total_relative_data_rate(crtc_state,
plane_data_rate);
else
total_data_rate =
- skl_get_total_relative_data_rate(cstate,
+ skl_get_total_relative_data_rate(crtc_state,
plane_data_rate,
uv_plane_data_rate);
- skl_ddb_get_pipe_allocation_limits(dev_priv, cstate, total_data_rate,
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
ddb, alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
/* Allocate fixed number of blocks for cursor. */
- total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
alloc_size -= total[PLANE_CURSOR];
- cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
alloc->end - total[PLANE_CURSOR];
- cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
if (total_data_rate == 0)
return 0;
@@ -4402,7 +4388,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
blocks = 0;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
const struct skl_plane_wm *wm =
- &cstate->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane_id];
if (plane_id == PLANE_CURSOR) {
if (WARN_ON(wm->wm[level].min_ddb_alloc >
@@ -4437,7 +4423,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
const struct skl_plane_wm *wm =
- &cstate->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane_id];
u64 rate;
u16 extra;
@@ -4476,9 +4462,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
start = alloc->start;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
struct skl_ddb_entry *plane_alloc =
- &cstate->wm.skl.plane_ddb_y[plane_id];
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
struct skl_ddb_entry *uv_plane_alloc =
- &cstate->wm.skl.plane_ddb_uv[plane_id];
+ &crtc_state->wm.skl.plane_ddb_uv[plane_id];
if (plane_id == PLANE_CURSOR)
continue;
@@ -4509,7 +4495,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
struct skl_plane_wm *wm =
- &cstate->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane_id];
/*
* We only disable the watermarks for each plane if
@@ -4546,7 +4532,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
struct skl_plane_wm *wm =
- &cstate->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane_id];
if (wm->trans_wm.plane_res_b >= total[plane_id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
@@ -4598,43 +4584,43 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
}
static uint_fixed_16_16_t
-intel_get_linetime_us(const struct intel_crtc_state *cstate)
+intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate;
u32 crtc_htotal;
uint_fixed_16_16_t linetime_us;
- if (!cstate->base.active)
+ if (!crtc_state->base.active)
return u32_to_fixed16(0);
- pixel_rate = cstate->pixel_rate;
+ pixel_rate = crtc_state->pixel_rate;
if (WARN_ON(pixel_rate == 0))
return u32_to_fixed16(0);
- crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
return linetime_us;
}
static u32
-skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate)
+skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
u64 adjusted_pixel_rate;
uint_fixed_16_16_t downscale_amount;
/* Shouldn't reach here on disabled planes... */
- if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
+ if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
return 0;
/*
* Adjusted plane pixel rate is just the pipe's adjusted pixel rate
* with additional adjustments for plane-specific scaling.
*/
- adjusted_pixel_rate = cstate->pixel_rate;
- downscale_amount = skl_plane_downscale_amount(cstate, pstate);
+ adjusted_pixel_rate = crtc_state->pixel_rate;
+ downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
return mul_round_up_u32_fixed16(adjusted_pixel_rate,
downscale_amount);
@@ -4767,13 +4753,13 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
return level > 0;
}
-static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
+static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
@@ -4799,14 +4785,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
- cstate->base.adjusted_mode.crtc_htotal,
+ crtc_state->base.adjusted_mode.crtc_htotal,
latency,
wp->plane_blocks_per_line);
if (wp->y_tiled) {
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
- if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
+ if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
wp->dbuf_block_size < 1) &&
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
@@ -4893,18 +4879,18 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
}
static void
-skl_compute_wm_levels(const struct intel_crtc_state *cstate,
+skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
- skl_compute_plane_wm(cstate, level, wm_params,
+ skl_compute_plane_wm(crtc_state, level, wm_params,
result_prev, result);
result_prev = result;
@@ -4912,14 +4898,14 @@ skl_compute_wm_levels(const struct intel_crtc_state *cstate,
}
static u32
-skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
+skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
{
- struct drm_atomic_state *state = cstate->base.state;
+ struct drm_atomic_state *state = crtc_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->dev);
uint_fixed_16_16_t linetime_us;
u32 linetime_wm;
- linetime_us = intel_get_linetime_us(cstate);
+ linetime_us = intel_get_linetime_us(crtc_state);
linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
/* Display WA #1135: BXT:ALL GLK:ALL */
@@ -4929,11 +4915,11 @@ skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
return linetime_wm;
}
-static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
+static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
{
- struct drm_device *dev = cstate->base.crtc->dev;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
u16 trans_min, trans_y_tile_min;
const u16 trans_amount = 10; /* This is configurable amount */
@@ -5091,13 +5077,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
return 0;
}
-static int skl_build_pipe_wm(struct intel_crtc_state *cstate)
+static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
- struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
- struct drm_crtc_state *crtc_state = &cstate->base;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
struct drm_plane *plane;
- const struct drm_plane_state *pstate;
+ const struct drm_plane_state *drm_plane_state;
int ret;
/*
@@ -5106,19 +5091,20 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate)
*/
memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
- const struct intel_plane_state *intel_pstate =
- to_intel_plane_state(pstate);
+ drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
+ &crtc_state->base) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(drm_plane_state);
if (INTEL_GEN(dev_priv) >= 11)
- ret = icl_build_plane_wm(cstate, intel_pstate);
+ ret = icl_build_plane_wm(crtc_state, plane_state);
else
- ret = skl_build_plane_wm(cstate, intel_pstate);
+ ret = skl_build_plane_wm(crtc_state, plane_state);
if (ret)
return ret;
}
- pipe_wm->linetime = skl_compute_linetime_wm(cstate);
+ pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
return 0;
}
@@ -5272,10 +5258,10 @@ static u32
pipes_modified(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
- struct intel_crtc_state *cstate;
+ struct intel_crtc_state *crtc_state;
u32 i, ret = 0;
- for_each_new_intel_crtc_in_state(state, crtc, cstate, i)
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
ret |= drm_crtc_mask(&crtc->base);
return ret;
@@ -5651,11 +5637,11 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate)
+ struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
+ struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
@@ -5665,9 +5651,9 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
}
static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate)
+ struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct skl_ddb_values *results = &state->wm_results;
@@ -5677,8 +5663,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
- if (cstate->base.active_changed)
- skl_atomic_update_crtc_wm(state, cstate);
+ if (crtc_state->base.active_changed)
+ skl_atomic_update_crtc_wm(state, crtc_state);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5734,26 +5720,26 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate)
+ struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
- intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
+ intel_crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
ilk_program_watermarks(dev_priv);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *cstate)
+ struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
- if (cstate->wm.need_postvbl_update) {
- intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
+ if (crtc_state->wm.need_postvbl_update) {
+ intel_crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
ilk_program_watermarks(dev_priv);
}
mutex_unlock(&dev_priv->wm.wm_mutex);
@@ -5811,13 +5797,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
- struct intel_crtc_state *cstate;
+ struct intel_crtc_state *crtc_state;
skl_ddb_get_hw_state(dev_priv, ddb);
for_each_intel_crtc(&dev_priv->drm, crtc) {
- cstate = to_intel_crtc_state(crtc->base.state);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
- skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
+ skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
if (crtc->active)
hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
@@ -5834,8 +5820,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct ilk_wm_values *hw = &dev_priv->wm.hw;
- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
- struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
static const i915_reg_t wm0_pipe_reg[] = {
[PIPE_A] = WM0_PIPEA_ILK,
@@ -7191,7 +7177,7 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
* next request to execute. If the idle hysteresis is less than that
* interrupt service latency, the hardware will automatically gate
* the power well and we will then incur the wake up cost on top of
- * the service latency. A similar guide from intel_pstate is that we
+ * the service latency. A similar guide from plane_state is that we
* do not want the enable hysteresis to less than the wakeup latency.
*
* igt/gem_exec_nop/sequential provides a rough estimate for the
@@ -7270,7 +7256,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
* next request to execute. If the idle hysteresis is less than that
* interrupt service latency, the hardware will automatically gate
* the power well and we will then incur the wake up cost on top of
- * the service latency. A similar guide from intel_pstate is that we
+ * the service latency. A similar guide from plane_state is that we
* do not want the enable hysteresis to less than the wakeup latency.
*
* igt/gem_exec_nop/sequential provides a rough estimate for the
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 6/6] drm/i915: Use intel state as much as possible in wm code
2019-06-28 8:55 ` [PATCH v2 6/6] drm/i915: Use intel state as much as possible in wm code Maarten Lankhorst
@ 2019-07-01 8:34 ` Maarten Lankhorst
0 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-07-01 8:34 UTC (permalink / raw)
To: intel-gfx
Op 28-06-2019 om 10:55 schreef Maarten Lankhorst:
> Instead of directly referencing drm_crtc_state, convert to
> intel_ctc_state and use the base struct. This is useful when we're
> making the split between uapi and hw state, and also makes the
> code slightly more readable.
>
> A lot of places also use cstate, instead of the more common crtc_state.
> Clean those up to use crtc_state. Same for pstate vs plane_state. (Ville)
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 12 +-
> drivers/gpu/drm/i915/intel_pm.c | 402 +++++++++++++++-----------------
> 2 files changed, 200 insertions(+), 214 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7d9ae234a02e..02dd9f9f3a89 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -287,14 +287,14 @@ struct drm_i915_display_funcs {
> enum pipe pipe);
> int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane);
> - int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
> - int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
> + int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> + int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> void (*initial_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate);
> + struct intel_crtc_state *crtc_state);
> void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate);
> + struct intel_crtc_state *crtc_state);
> void (*optimize_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate);
> + struct intel_crtc_state *crtc_state);
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> void (*update_wm)(struct intel_crtc *crtc);
> int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> @@ -1646,7 +1646,7 @@ struct drm_i915_private {
> /*
> * Should be held around atomic WM register writing; also
> * protects * intel_crtc->wm.active and
> - * cstate->wm.need_postvbl_update.
> + * crtc_state->wm.need_postvbl_update.
> */
> struct mutex wm_mutex;
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4116de2a77fd..d10c62d3f10c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1198,8 +1198,8 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
> return dirty;
> }
>
> -static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate,
> +static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> u32 pri_val);
>
> static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
> @@ -2493,8 +2493,8 @@ struct ilk_wm_maximums {
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate,
> +static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> u32 mem_value, bool is_lp)
> {
> u32 method1, method2;
> @@ -2503,19 +2503,19 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> if (mem_value == 0)
> return U32_MAX;
>
> - if (!intel_wm_plane_visible(cstate, pstate))
> + if (!intel_wm_plane_visible(crtc_state, plane_state))
> return 0;
>
> - cpp = pstate->base.fb->format->cpp[0];
> + cpp = plane_state->base.fb->format->cpp[0];
>
> - method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
> + method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
>
> if (!is_lp)
> return method1;
>
> - method2 = ilk_wm_method2(cstate->pixel_rate,
> - cstate->base.adjusted_mode.crtc_htotal,
> - drm_rect_width(&pstate->base.dst),
> + method2 = ilk_wm_method2(crtc_state->pixel_rate,
> + crtc_state->base.adjusted_mode.crtc_htotal,
> + drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
>
> return min(method1, method2);
> @@ -2525,8 +2525,8 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate,
> +static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> u32 mem_value)
> {
> u32 method1, method2;
> @@ -2535,15 +2535,15 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
> if (mem_value == 0)
> return U32_MAX;
>
> - if (!intel_wm_plane_visible(cstate, pstate))
> + if (!intel_wm_plane_visible(crtc_state, plane_state))
> return 0;
>
> - cpp = pstate->base.fb->format->cpp[0];
> + cpp = plane_state->base.fb->format->cpp[0];
>
> - method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
> - method2 = ilk_wm_method2(cstate->pixel_rate,
> - cstate->base.adjusted_mode.crtc_htotal,
> - drm_rect_width(&pstate->base.dst),
> + method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> + method2 = ilk_wm_method2(crtc_state->pixel_rate,
> + crtc_state->base.adjusted_mode.crtc_htotal,
> + drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
> return min(method1, method2);
> }
> @@ -2552,8 +2552,8 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate,
> +static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> u32 mem_value)
> {
> int cpp;
> @@ -2561,29 +2561,29 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> if (mem_value == 0)
> return U32_MAX;
>
> - if (!intel_wm_plane_visible(cstate, pstate))
> + if (!intel_wm_plane_visible(crtc_state, plane_state))
> return 0;
>
> - cpp = pstate->base.fb->format->cpp[0];
> + cpp = plane_state->base.fb->format->cpp[0];
>
> - return ilk_wm_method2(cstate->pixel_rate,
> - cstate->base.adjusted_mode.crtc_htotal,
> - pstate->base.crtc_w, cpp, mem_value);
> + return ilk_wm_method2(crtc_state->pixel_rate,
> + crtc_state->base.adjusted_mode.crtc_htotal,
> + plane_state->base.crtc_w, cpp, mem_value);
> }
>
> /* Only for WM_LP. */
> -static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate,
> +static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> u32 pri_val)
> {
> int cpp;
>
> - if (!intel_wm_plane_visible(cstate, pstate))
> + if (!intel_wm_plane_visible(crtc_state, plane_state))
> return 0;
>
> - cpp = pstate->base.fb->format->cpp[0];
> + cpp = plane_state->base.fb->format->cpp[0];
>
> - return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
> + return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
> }
>
> static unsigned int
> @@ -2752,7 +2752,7 @@ static bool ilk_validate_wm_level(int level,
> static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
> const struct intel_crtc *intel_crtc,
> int level,
> - struct intel_crtc_state *cstate,
> + struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *pristate,
> const struct intel_plane_state *sprstate,
> const struct intel_plane_state *curstate,
> @@ -2770,30 +2770,30 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
> }
>
> if (pristate) {
> - result->pri_val = ilk_compute_pri_wm(cstate, pristate,
> + result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
> pri_latency, level);
> - result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
> + result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
> }
>
> if (sprstate)
> - result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
> + result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
>
> if (curstate)
> - result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
> + result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
>
> result->enable = true;
> }
>
> static u32
> -hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
> +hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(cstate->base.state);
> + to_intel_atomic_state(crtc_state->base.state);
> const struct drm_display_mode *adjusted_mode =
> - &cstate->base.adjusted_mode;
> + &crtc_state->base.adjusted_mode;
> u32 linetime, ips_linetime;
>
> - if (!cstate->base.active)
> + if (!crtc_state->base.active)
> return 0;
> if (WARN_ON(adjusted_mode->crtc_clock == 0))
> return 0;
> @@ -3101,10 +3101,10 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
> }
>
> /* Compute new watermarks for the pipe */
> -static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> +static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = cstate->base.state;
> - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
> + struct drm_atomic_state *state = crtc_state->base.state;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> struct intel_pipe_wm *pipe_wm;
> struct drm_device *dev = state->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3116,9 +3116,9 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
> struct ilk_wm_maximums max;
>
> - pipe_wm = &cstate->wm.ilk.optimal;
> + pipe_wm = &crtc_state->wm.ilk.optimal;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
> + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
> const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
>
> if (plane->type == DRM_PLANE_TYPE_PRIMARY)
> @@ -3129,7 +3129,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> curstate = ps;
> }
>
> - pipe_wm->pipe_enabled = cstate->base.active;
> + pipe_wm->pipe_enabled = crtc_state->base.active;
> if (sprstate) {
> pipe_wm->sprites_enabled = sprstate->base.visible;
> pipe_wm->sprites_scaled = sprstate->base.visible &&
> @@ -3148,11 +3148,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> usable_level = 0;
>
> memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
> - ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
> + ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
> pristate, sprstate, curstate, &pipe_wm->wm[0]);
>
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> - pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
> + pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
>
> if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
> return -EINVAL;
> @@ -3162,7 +3162,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> for (level = 1; level <= usable_level; level++) {
> struct intel_wm_level *wm = &pipe_wm->wm[level];
>
> - ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
> + ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
> pristate, sprstate, curstate, wm);
>
> /*
> @@ -3742,7 +3742,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc;
> struct intel_plane *plane;
> - struct intel_crtc_state *cstate;
> + struct intel_crtc_state *crtc_state;
> enum pipe pipe;
> int level, latency;
> int sagv_block_time_us;
> @@ -3773,14 +3773,14 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> /* Since we're now guaranteed to only have one active CRTC... */
> pipe = ffs(state->active_crtcs) - 1;
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> - cstate = to_intel_crtc_state(crtc->base.state);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
>
> if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> return false;
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> struct skl_plane_wm *wm =
> - &cstate->wm.skl.optimal.planes[plane->id];
> + &crtc_state->wm.skl.optimal.planes[plane->id];
>
> /* Skip this plane if it's not enabled */
> if (!wm->wm[0].plane_en)
> @@ -3811,7 +3811,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> }
>
> static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *cstate,
> + const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> const int num_active,
> struct skl_ddb_allocation *ddb)
> @@ -3825,7 +3825,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> return ddb_size - 4; /* 4 blocks for bypass path allocation */
>
> - adjusted_mode = &cstate->base.adjusted_mode;
> + adjusted_mode = &crtc_state->base.adjusted_mode;
> total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
>
> /*
> @@ -3848,23 +3848,22 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
>
> static void
> skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *cstate,
> + const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> struct skl_ddb_allocation *ddb,
> struct skl_ddb_entry *alloc, /* out */
> int *num_active /* out */)
> {
> - struct drm_atomic_state *state = cstate->base.state;
> + struct drm_atomic_state *state = crtc_state->base.state;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct drm_crtc *for_crtc = cstate->base.crtc;
> - const struct drm_crtc_state *crtc_state;
> - const struct drm_crtc *crtc;
> + struct drm_crtc *for_crtc = crtc_state->base.crtc;
> + const struct intel_crtc *crtc;
> u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
> enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> u16 ddb_size;
> u32 i;
>
> - if (WARN_ON(!state) || !cstate->base.active) {
> + if (WARN_ON(!state) || !crtc_state->base.active) {
> alloc->start = 0;
> alloc->end = 0;
> *num_active = hweight32(dev_priv->active_crtcs);
> @@ -3876,7 +3875,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> else
> *num_active = hweight32(dev_priv->active_crtcs);
>
> - ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
> + ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
> *num_active, ddb);
>
> /*
> @@ -3901,16 +3900,15 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> * framebuffer, So instead of allocating DDB equally among pipes
> * distribute DDB based on resolution/width of the display.
> */
> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - const struct drm_display_mode *adjusted_mode;
> + for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->base.adjusted_mode;
> + enum pipe pipe = crtc->pipe;
> int hdisplay, vdisplay;
> - enum pipe pipe;
>
> - if (!crtc_state->enable)
> + if (!crtc_state->base.enable)
> continue;
>
> - pipe = to_intel_crtc(crtc)->pipe;
> - adjusted_mode = &crtc_state->adjusted_mode;
> drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> total_width += hdisplay;
>
> @@ -3929,7 +3927,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> u64 modifier, unsigned int rotation,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> int color_plane);
> -static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> +static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> @@ -4061,15 +4059,15 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> * Caller should take care of dividing & rounding off the value.
> */
> static uint_fixed_16_16_t
> -skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate)
> +skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> - struct intel_plane *plane = to_intel_plane(pstate->base.plane);
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 src_w, src_h, dst_w, dst_h;
> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> uint_fixed_16_16_t downscale_h, downscale_w;
>
> - if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
> + if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> return u32_to_fixed16(0);
>
> /* n.b., src is 16.16 fixed point, dst is whole integer */
> @@ -4078,20 +4076,20 @@ skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
> * Cursors only support 0/180 degree rotation,
> * hence no need to account for rotation here.
> */
> - src_w = pstate->base.src_w >> 16;
> - src_h = pstate->base.src_h >> 16;
> - dst_w = pstate->base.crtc_w;
> - dst_h = pstate->base.crtc_h;
> + src_w = plane_state->base.src_w >> 16;
> + src_h = plane_state->base.src_h >> 16;
> + dst_w = plane_state->base.crtc_w;
> + dst_h = plane_state->base.crtc_h;
> } else {
> /*
> * Src coordinates are already rotated by 270 degrees for
> * the 90/270 degree plane rotation cases (to match the
> * GTT mapping), hence no need to account for rotation here.
> */
> - src_w = drm_rect_width(&pstate->base.src) >> 16;
> - src_h = drm_rect_height(&pstate->base.src) >> 16;
> - dst_w = drm_rect_width(&pstate->base.dst);
> - dst_h = drm_rect_height(&pstate->base.dst);
> + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + dst_w = drm_rect_width(&plane_state->base.dst);
> + dst_h = drm_rect_height(&plane_state->base.dst);
> }
>
> fp_w_ratio = div_fixed16(src_w, dst_w);
> @@ -4136,49 +4134,46 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
> }
>
> int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *cstate)
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> - struct drm_crtc_state *crtc_state = &cstate->base;
> - struct drm_atomic_state *state = crtc_state->state;
> + struct drm_atomic_state *state = crtc_state->base.state;
> struct drm_plane *plane;
> - const struct drm_plane_state *pstate;
> - struct intel_plane_state *intel_pstate;
> + const struct drm_plane_state *drm_plane_state;
> int crtc_clock, dotclk;
> u32 pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
>
> - if (!cstate->base.enable)
> + if (!crtc_state->base.enable)
> return 0;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
> + drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> uint_fixed_16_16_t plane_downscale;
> uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
> int bpp;
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(drm_plane_state);
>
> - if (!intel_wm_plane_visible(cstate,
> - to_intel_plane_state(pstate)))
> + if (!intel_wm_plane_visible(crtc_state, plane_state))
> continue;
>
> - if (WARN_ON(!pstate->fb))
> + if (WARN_ON(!plane_state->base.fb))
> return -EINVAL;
>
> - intel_pstate = to_intel_plane_state(pstate);
> - plane_downscale = skl_plane_downscale_amount(cstate,
> - intel_pstate);
> - bpp = pstate->fb->format->cpp[0] * 8;
> + plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
> + bpp = plane_state->base.fb->format->cpp[0] * 8;
> if (bpp == 64)
> plane_downscale = mul_fixed16(plane_downscale,
> fp_9_div_8);
>
> max_downscale = max_fixed16(plane_downscale, max_downscale);
> }
> - pipe_downscale = skl_pipe_downscale_amount(cstate);
> + pipe_downscale = skl_pipe_downscale_amount(crtc_state);
>
> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>
> - crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> + crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>
> if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> @@ -4195,12 +4190,11 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> }
>
> static u64
> -skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *intel_pstate,
> +skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> const int plane)
> {
> - struct intel_plane *intel_plane =
> - to_intel_plane(intel_pstate->base.plane);
> + struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
> u32 data_rate;
> u32 width = 0, height = 0;
> struct drm_framebuffer *fb;
> @@ -4208,10 +4202,10 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> uint_fixed_16_16_t down_scale_amount;
> u64 rate;
>
> - if (!intel_pstate->base.visible)
> + if (!plane_state->base.visible)
> return 0;
>
> - fb = intel_pstate->base.fb;
> + fb = plane_state->base.fb;
> format = fb->format->format;
>
> if (intel_plane->id == PLANE_CURSOR)
> @@ -4224,8 +4218,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> * the 90/270 degree plane rotation cases (to match the
> * GTT mapping), hence no need to account for rotation here.
> */
> - width = drm_rect_width(&intel_pstate->base.src) >> 16;
> - height = drm_rect_height(&intel_pstate->base.src) >> 16;
> + width = drm_rect_width(&plane_state->base.src) >> 16;
> + height = drm_rect_height(&plane_state->base.src) >> 16;
>
> /* UV plane does 1/2 pixel sub-sampling */
> if (plane == 1 && is_planar_yuv_format(format)) {
> @@ -4235,7 +4229,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>
> data_rate = width * height;
>
> - down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
> + down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
>
> rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
>
> @@ -4244,35 +4238,32 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> }
>
> static u64
> -skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> +skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate,
> u64 *uv_plane_data_rate)
> {
> - struct drm_crtc_state *cstate = &intel_cstate->base;
> - struct drm_atomic_state *state = cstate->state;
> + struct drm_atomic_state *state = crtc_state->base.state;
> struct drm_plane *plane;
> - const struct drm_plane_state *pstate;
> + const struct drm_plane_state *drm_plane_state;
> u64 total_data_rate = 0;
>
> if (WARN_ON(!state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
> + drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> enum plane_id plane_id = to_intel_plane(plane)->id;
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(drm_plane_state);
> u64 rate;
> - const struct intel_plane_state *intel_pstate =
> - to_intel_plane_state(pstate);
>
> /* packed/y */
> - rate = skl_plane_relative_data_rate(intel_cstate,
> - intel_pstate, 0);
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
>
> /* uv-plane */
> - rate = skl_plane_relative_data_rate(intel_cstate,
> - intel_pstate, 1);
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> uv_plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
> }
> @@ -4281,28 +4272,25 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> }
>
> static u64
> -icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> +icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate)
> {
> - struct drm_crtc_state *cstate = &intel_cstate->base;
> - struct drm_atomic_state *state = cstate->state;
> struct drm_plane *plane;
> - const struct drm_plane_state *pstate;
> + const struct drm_plane_state *drm_plane_state;
> u64 total_data_rate = 0;
>
> - if (WARN_ON(!state))
> + if (WARN_ON(!crtc_state->base.state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
> - const struct intel_plane_state *intel_pstate =
> - to_intel_plane_state(pstate);
> + drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(drm_plane_state);
> enum plane_id plane_id = to_intel_plane(plane)->id;
> u64 rate;
>
> - if (!intel_pstate->linked_plane) {
> - rate = skl_plane_relative_data_rate(intel_cstate,
> - intel_pstate, 0);
> + if (!plane_state->linked_plane) {
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
> } else {
> @@ -4315,18 +4303,16 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> * NULL if we try get_new_plane_state(), so we
> * always calculate from the master.
> */
> - if (intel_pstate->slave)
> + if (plane_state->slave)
> continue;
>
> /* Y plane rate is calculated on the slave */
> - rate = skl_plane_relative_data_rate(intel_cstate,
> - intel_pstate, 0);
> - y_plane_id = intel_pstate->linked_plane->id;
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> + y_plane_id = plane_state->linked_plane->id;
> plane_data_rate[y_plane_id] = rate;
> total_data_rate += rate;
>
> - rate = skl_plane_relative_data_rate(intel_cstate,
> - intel_pstate, 1);
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
> }
> @@ -4336,14 +4322,14 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> }
>
> static int
> -skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> +skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> {
> - struct drm_atomic_state *state = cstate->base.state;
> - struct drm_crtc *crtc = cstate->base.crtc;
> + struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_crtc *crtc = crtc_state->base.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> u16 alloc_size, start = 0;
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> @@ -4356,40 +4342,40 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> int level;
>
> /* Clear the partitioning for disabled planes. */
> - memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
> - memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
> + memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
> + memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
>
> if (WARN_ON(!state))
> return 0;
>
> - if (!cstate->base.active) {
> + if (!crtc_state->base.active) {
> alloc->start = alloc->end = 0;
> return 0;
> }
>
> if (INTEL_GEN(dev_priv) >= 11)
> total_data_rate =
> - icl_get_total_relative_data_rate(cstate,
> + icl_get_total_relative_data_rate(crtc_state,
> plane_data_rate);
> else
> total_data_rate =
> - skl_get_total_relative_data_rate(cstate,
> + skl_get_total_relative_data_rate(crtc_state,
> plane_data_rate,
> uv_plane_data_rate);
>
>
> - skl_ddb_get_pipe_allocation_limits(dev_priv, cstate, total_data_rate,
> + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> ddb, alloc, &num_active);
> alloc_size = skl_ddb_entry_size(alloc);
> if (alloc_size == 0)
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
> + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> alloc_size -= total[PLANE_CURSOR];
> - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> alloc->end - total[PLANE_CURSOR];
> - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
>
> if (total_data_rate == 0)
> return 0;
> @@ -4402,7 +4388,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> blocks = 0;
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> const struct skl_plane_wm *wm =
> - &cstate->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane_id];
>
> if (plane_id == PLANE_CURSOR) {
> if (WARN_ON(wm->wm[level].min_ddb_alloc >
> @@ -4437,7 +4423,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> */
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> const struct skl_plane_wm *wm =
> - &cstate->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> u64 rate;
> u16 extra;
>
> @@ -4476,9 +4462,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> start = alloc->start;
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> struct skl_ddb_entry *plane_alloc =
> - &cstate->wm.skl.plane_ddb_y[plane_id];
> + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> struct skl_ddb_entry *uv_plane_alloc =
> - &cstate->wm.skl.plane_ddb_uv[plane_id];
> + &crtc_state->wm.skl.plane_ddb_uv[plane_id];
>
> if (plane_id == PLANE_CURSOR)
> continue;
> @@ -4509,7 +4495,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> struct skl_plane_wm *wm =
> - &cstate->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane_id];
>
> /*
> * We only disable the watermarks for each plane if
> @@ -4546,7 +4532,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> */
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> struct skl_plane_wm *wm =
> - &cstate->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane_id];
>
> if (wm->trans_wm.plane_res_b >= total[plane_id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> @@ -4598,43 +4584,43 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
> }
>
> static uint_fixed_16_16_t
> -intel_get_linetime_us(const struct intel_crtc_state *cstate)
> +intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> {
> u32 pixel_rate;
> u32 crtc_htotal;
> uint_fixed_16_16_t linetime_us;
>
> - if (!cstate->base.active)
> + if (!crtc_state->base.active)
> return u32_to_fixed16(0);
>
> - pixel_rate = cstate->pixel_rate;
> + pixel_rate = crtc_state->pixel_rate;
>
> if (WARN_ON(pixel_rate == 0))
> return u32_to_fixed16(0);
>
> - crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
> + crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
> linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
>
> return linetime_us;
> }
>
> static u32
> -skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate)
> +skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> u64 adjusted_pixel_rate;
> uint_fixed_16_16_t downscale_amount;
>
> /* Shouldn't reach here on disabled planes... */
> - if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
> + if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> return 0;
>
> /*
> * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> * with additional adjustments for plane-specific scaling.
> */
> - adjusted_pixel_rate = cstate->pixel_rate;
> - downscale_amount = skl_plane_downscale_amount(cstate, pstate);
> + adjusted_pixel_rate = crtc_state->pixel_rate;
> + downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
>
> return mul_round_up_u32_fixed16(adjusted_pixel_rate,
> downscale_amount);
> @@ -4767,13 +4753,13 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
> return level > 0;
> }
>
> -static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> +static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> @@ -4799,14 +4785,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> wp->cpp, latency, wp->dbuf_block_size);
> method2 = skl_wm_method2(wp->plane_pixel_rate,
> - cstate->base.adjusted_mode.crtc_htotal,
> + crtc_state->base.adjusted_mode.crtc_htotal,
> latency,
> wp->plane_blocks_per_line);
>
> if (wp->y_tiled) {
> selected_result = max_fixed16(method2, wp->y_tile_minimum);
> } else {
> - if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
> + if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
> wp->dbuf_block_size < 1) &&
> (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> selected_result = method2;
> @@ -4893,18 +4879,18 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> }
>
> static void
> -skl_compute_wm_levels(const struct intel_crtc_state *cstate,
> +skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level *result_prev = &levels[0];
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
>
> - skl_compute_plane_wm(cstate, level, wm_params,
> + skl_compute_plane_wm(crtc_state, level, wm_params,
> result_prev, result);
>
> result_prev = result;
> @@ -4912,14 +4898,14 @@ skl_compute_wm_levels(const struct intel_crtc_state *cstate,
> }
>
> static u32
> -skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
> +skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = cstate->base.state;
> + struct drm_atomic_state *state = crtc_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> uint_fixed_16_16_t linetime_us;
> u32 linetime_wm;
>
> - linetime_us = intel_get_linetime_us(cstate);
> + linetime_us = intel_get_linetime_us(crtc_state);
> linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
>
> /* Display WA #1135: BXT:ALL GLK:ALL */
> @@ -4929,11 +4915,11 @@ skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
> return linetime_wm;
> }
>
> -static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
> +static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wp,
> struct skl_plane_wm *wm)
> {
> - struct drm_device *dev = cstate->base.crtc->dev;
> + struct drm_device *dev = crtc_state->base.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> u16 trans_min, trans_y_tile_min;
> const u16 trans_amount = 10; /* This is configurable amount */
> @@ -5091,13 +5077,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static int skl_build_pipe_wm(struct intel_crtc_state *cstate)
> +static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> - struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
> - struct drm_crtc_state *crtc_state = &cstate->base;
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> struct drm_plane *plane;
> - const struct drm_plane_state *pstate;
> + const struct drm_plane_state *drm_plane_state;
> int ret;
>
> /*
> @@ -5106,19 +5091,20 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate)
> */
> memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
> - const struct intel_plane_state *intel_pstate =
> - to_intel_plane_state(pstate);
> + drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
> + &crtc_state->base) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(drm_plane_state);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - ret = icl_build_plane_wm(cstate, intel_pstate);
> + ret = icl_build_plane_wm(crtc_state, plane_state);
> else
> - ret = skl_build_plane_wm(cstate, intel_pstate);
> + ret = skl_build_plane_wm(crtc_state, plane_state);
> if (ret)
> return ret;
> }
>
> - pipe_wm->linetime = skl_compute_linetime_wm(cstate);
> + pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
>
> return 0;
> }
> @@ -5272,10 +5258,10 @@ static u32
> pipes_modified(struct intel_atomic_state *state)
> {
> struct intel_crtc *crtc;
> - struct intel_crtc_state *cstate;
> + struct intel_crtc_state *crtc_state;
> u32 i, ret = 0;
>
> - for_each_new_intel_crtc_in_state(state, crtc, cstate, i)
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
> ret |= drm_crtc_mask(&crtc->base);
>
> return ret;
> @@ -5651,11 +5637,11 @@ skl_compute_wm(struct intel_atomic_state *state)
> }
>
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate)
> + struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
> + struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> enum pipe pipe = crtc->pipe;
>
> if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
> @@ -5665,9 +5651,9 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> }
>
> static void skl_initial_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate)
> + struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct skl_ddb_values *results = &state->wm_results;
> @@ -5677,8 +5663,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>
> mutex_lock(&dev_priv->wm.wm_mutex);
>
> - if (cstate->base.active_changed)
> - skl_atomic_update_crtc_wm(state, cstate);
> + if (crtc_state->base.active_changed)
> + skl_atomic_update_crtc_wm(state, crtc_state);
>
> mutex_unlock(&dev_priv->wm.wm_mutex);
> }
> @@ -5734,26 +5720,26 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate)
> + struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> - intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
> + intel_crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> ilk_program_watermarks(dev_priv);
> mutex_unlock(&dev_priv->wm.wm_mutex);
> }
>
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *cstate)
> + struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> - if (cstate->wm.need_postvbl_update) {
> - intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
> + if (crtc_state->wm.need_postvbl_update) {
> + intel_crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
> ilk_program_watermarks(dev_priv);
> }
> mutex_unlock(&dev_priv->wm.wm_mutex);
> @@ -5811,13 +5797,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
> struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
> struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> struct intel_crtc *crtc;
> - struct intel_crtc_state *cstate;
> + struct intel_crtc_state *crtc_state;
>
> skl_ddb_get_hw_state(dev_priv, ddb);
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> - cstate = to_intel_crtc_state(crtc->base.state);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
>
> - skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
> + skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
>
> if (crtc->active)
> hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
> @@ -5834,8 +5820,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct ilk_wm_values *hw = &dev_priv->wm.hw;
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
> - struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> + struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
> enum pipe pipe = crtc->pipe;
> static const i915_reg_t wm0_pipe_reg[] = {
> [PIPE_A] = WM0_PIPEA_ILK,
> @@ -7191,7 +7177,7 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
> * next request to execute. If the idle hysteresis is less than that
> * interrupt service latency, the hardware will automatically gate
> * the power well and we will then incur the wake up cost on top of
> - * the service latency. A similar guide from intel_pstate is that we
> + * the service latency. A similar guide from plane_state is that we
> * do not want the enable hysteresis to less than the wakeup latency.
> *
> * igt/gem_exec_nop/sequential provides a rough estimate for the
> @@ -7270,7 +7256,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> * next request to execute. If the idle hysteresis is less than that
> * interrupt service latency, the hardware will automatically gate
> * the power well and we will then incur the wake up cost on top of
> - * the service latency. A similar guide from intel_pstate is that we
> + * the service latency. A similar guide from plane_state is that we
> * do not want the enable hysteresis to less than the wakeup latency.
> *
> * igt/gem_exec_nop/sequential provides a rough estimate for the
And pushed, with CI being happy. :)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use intel_crtc_state everywhere!
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (5 preceding siblings ...)
2019-06-28 8:55 ` [PATCH v2 6/6] drm/i915: Use intel state as much as possible in wm code Maarten Lankhorst
@ 2019-06-28 9:21 ` Patchwork
2019-06-28 9:24 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-28 9:21 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
86e398aa0e65 drm/i915: Pass intel_crtc_state to needs_modeset()
83682e1854bb drm/i915: Convert most of atomic commit to take more intel state
-:449: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#449: FILE: drivers/gpu/drm/i915/display/intel_display.c:6675:
+ crtc->enabled_power_domains = new_domains =
-:770: WARNING:LONG_LINE: line over 100 characters
#770: FILE: drivers/gpu/drm/i915/display/intel_display.c:13647:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
total: 0 errors, 1 warnings, 1 checks, 1060 lines checked
a6061facf2c3 drm/i915: Convert hw state verifier to take more intel state, v2.
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#38: FILE: drivers/gpu/drm/i915/display/intel_display.c:6999:
+ I915_STATE_WARN(!crtc_state->base.active,
"connector is active, but attached crtc isn't\n");
-:47: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#47: FILE: drivers/gpu/drm/i915/display/intel_display.c:7011:
+ I915_STATE_WARN(crtc_state && crtc_state->base.active,
"attached crtc is active, but connector isn't\n");
-:210: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#210: FILE: drivers/gpu/drm/i915/display/intel_display.c:12939:
+ I915_STATE_WARN(new_crtc_state->base.active != active,
"crtc active state doesn't match with hw state "
-:216: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#216: FILE: drivers/gpu/drm/i915/display/intel_display.c:12943:
+ I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
"transitional active state does not match atomic hw state "
-:227: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#227: FILE: drivers/gpu/drm/i915/display/intel_display.c:12951:
+ I915_STATE_WARN(active != new_crtc_state->base.active,
"[ENCODER:%i] active %i with crtc active %i\n",
-:308: WARNING:LONG_LINE: line over 100 characters
#308: FILE: drivers/gpu/drm/i915/display/intel_display.c:13053:
+ verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
total: 0 errors, 1 warnings, 5 checks, 346 lines checked
2fe9f8734334 drm/i915: Use intel_crtc_state in sanitize_watermarks() too
73e1ba270a31 drm/i915: Pass intel state to plane functions as well
-:180: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#180: FILE: drivers/gpu/drm/i915/display/intel_display.c:11358:
+ plane_state->base.visible = visible = false;
total: 0 errors, 0 warnings, 1 checks, 211 lines checked
8e4ffa6ce214 drm/i915: Use intel state as much as possible in wm code
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: Use intel_crtc_state everywhere!
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (6 preceding siblings ...)
2019-06-28 9:21 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use intel_crtc_state everywhere! Patchwork
@ 2019-06-28 9:24 ` Patchwork
2019-06-28 15:51 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-28 23:21 ` ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-28 9:24 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Pass intel_crtc_state to needs_modeset()
Okay!
Commit: drm/i915: Convert most of atomic commit to take more intel state
Okay!
Commit: drm/i915: Convert hw state verifier to take more intel state, v2.
Okay!
Commit: drm/i915: Use intel_crtc_state in sanitize_watermarks() too
Okay!
Commit: drm/i915: Pass intel state to plane functions as well
Okay!
Commit: drm/i915: Use intel state as much as possible in wm code
-O:drivers/gpu/drm/i915/intel_pm.c:2521:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2521:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2521:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2521:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Use intel_crtc_state everywhere!
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (7 preceding siblings ...)
2019-06-28 9:24 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-06-28 15:51 ` Patchwork
2019-06-28 23:21 ` ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-28 15:51 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6379 -> Patchwork_13468
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/
Known issues
------------
Here are the changes found in Patchwork_13468 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_reset:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([fdo#107709])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-bsw-kefka/igt@i915_selftest@live_reset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/fi-bsw-kefka/igt@i915_selftest@live_reset.html
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-skl-gvtdvm
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6379 -> Patchwork_13468
CI_DRM_6379: 12f8aba06508afb9b668a2496b2fb296ed21e377 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5072: 5f6cf7070b249975bac4d747a9c44d81c94c4381 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13468: 8e4ffa6ce214e98a0a3adc9245d493ebae100174 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
8e4ffa6ce214 drm/i915: Use intel state as much as possible in wm code
73e1ba270a31 drm/i915: Pass intel state to plane functions as well
2fe9f8734334 drm/i915: Use intel_crtc_state in sanitize_watermarks() too
a6061facf2c3 drm/i915: Convert hw state verifier to take more intel state, v2.
83682e1854bb drm/i915: Convert most of atomic commit to take more intel state
86e398aa0e65 drm/i915: Pass intel_crtc_state to needs_modeset()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Use intel_crtc_state everywhere!
2019-06-28 8:55 [PATCH v2 0/6] drm/i915: Use intel_crtc_state everywhere! Maarten Lankhorst
` (8 preceding siblings ...)
2019-06-28 15:51 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-06-28 23:21 ` Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-28 23:21 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6379_full -> Patchwork_13468_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13468_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-suspend:
- shard-glk: [PASS][1] -> [FAIL][2] ([fdo#110667])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-glk5/igt@gem_eio@in-flight-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-glk7/igt@gem_eio@in-flight-suspend.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl2/igt@i915_suspend@sysfs-reader.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-kbl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108682])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl2/igt@kms_color@pipe-c-ctm-0-25.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl5/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#103355])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) +26 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103184] / [fdo#103232])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw7/igt@kms_flip@2x-flip-vs-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-snb1/igt@kms_plane_lowres@pipe-b-tiling-none.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-snb4/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([fdo#104108])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-kbl: [PASS][31] -> [FAIL][32] ([fdo#105010])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl3/igt@perf_pmu@rc6-runtime-pm-long.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-kbl1/igt@perf_pmu@rc6-runtime-pm-long.html
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][33] ([fdo#104108]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl10/igt@gem_softpin@noreloc-s3.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl5/igt@gem_softpin@noreloc-s3.html
* igt@i915_selftest@mock_requests:
- shard-skl: [INCOMPLETE][35] ([fdo#110550]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@i915_selftest@mock_requests.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl9/igt@i915_selftest@mock_requests.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl3/igt@i915_suspend@debugfs-reader.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-kbl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-b:
- shard-snb: [SKIP][39] ([fdo#109271] / [fdo#109278]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-snb5/igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-b.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-snb7/igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-b.html
* igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque:
- shard-skl: [FAIL][41] ([fdo#103232]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][43] ([fdo#105767]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [FAIL][45] ([fdo#102670] / [fdo#106081]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][47] ([fdo#105363]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][49] ([fdo#105363]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][51] ([fdo#103167]) -> [PASS][52] +5 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-hsw: [SKIP][53] ([fdo#109271]) -> [PASS][54] +10 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-iclb: [INCOMPLETE][55] ([fdo#106978] / [fdo#107713]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] +8 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-snb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-snb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][59] ([fdo#108566]) -> [PASS][60] +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][61] ([fdo#108145]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb1/igt@kms_psr@psr2_basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][65] ([fdo#99912]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl2/igt@kms_setmode@basic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-kbl2/igt@kms_setmode@basic.html
- shard-snb: [FAIL][67] ([fdo#99912]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-snb1/igt@kms_setmode@basic.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-snb4/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [FAIL][69] ([fdo#100047]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb3/igt@kms_sysfs_edid_timing.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb8/igt@kms_sysfs_edid_timing.html
* igt@tools_test@tools_test:
- shard-glk: [SKIP][71] ([fdo#109271]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-glk2/igt@tools_test@tools_test.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-glk9/igt@tools_test@tools_test.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][73] ([fdo#109349]) -> [DMESG-WARN][74] ([fdo#107724])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-skl: [FAIL][75] ([fdo#103167]) -> [FAIL][76] ([fdo#108040])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-skl: [FAIL][77] ([fdo#108040]) -> [FAIL][78] ([fdo#103167])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][79] ([fdo#99912]) -> [INCOMPLETE][80] ([fdo#103540])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw7/igt@kms_setmode@basic.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/shard-hsw7/igt@kms_setmode@basic.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106081]: https://bugs.freedesktop.org/show_bug.cgi?id=106081
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110550]: https://bugs.freedesktop.org/show_bug.cgi?id=110550
[fdo#110667]: https://bugs.freedesktop.org/show_bug.cgi?id=110667
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6379 -> Patchwork_13468
CI_DRM_6379: 12f8aba06508afb9b668a2496b2fb296ed21e377 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5072: 5f6cf7070b249975bac4d747a9c44d81c94c4381 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13468: 8e4ffa6ce214e98a0a3adc9245d493ebae100174 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13468/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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