* [PATCH v6 1/3] drm/i915: fix whitelist selftests with readonly registers
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
@ 2019-06-27 9:01 ` Lionel Landwerlin
2019-06-27 11:57 ` Chris Wilson
2019-06-27 9:01 ` [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT Lionel Landwerlin
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2019-06-27 9:01 UTC (permalink / raw)
To: intel-gfx
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.
For PS_INVOCATION_COUNT we've got the following piglit tests :
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
Vulkan CTS tests :
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f12cb20fe785..a06f96df1bfd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -926,6 +926,9 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
err = 0;
for (i = 0; i < engine->whitelist.count; i++) {
+ if (engine->whitelist.list[i].reg.reg & RING_FORCE_TO_NONPRIV_RD)
+ continue;
+
if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
err = -EINVAL;
}
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 1/3] drm/i915: fix whitelist selftests with readonly registers
2019-06-27 9:01 ` [PATCH v6 1/3] drm/i915: fix whitelist selftests with readonly registers Lionel Landwerlin
@ 2019-06-27 11:57 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2019-06-27 11:57 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-06-27 10:01:14)
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register from userspace.
>
> For PS_INVOCATION_COUNT we've got the following piglit tests :
>
> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
>
> Vulkan CTS tests :
>
> dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index f12cb20fe785..a06f96df1bfd 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -926,6 +926,9 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
>
> err = 0;
> for (i = 0; i < engine->whitelist.count; i++) {
> + if (engine->whitelist.list[i].reg.reg & RING_FORCE_TO_NONPRIV_RD)
Ville would like you to use
i915_mmio_reg_offset(engine->whitelist.list[i].reg)
I think we might benefit from a reg local :)
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
2019-06-27 9:01 ` [PATCH v6 1/3] drm/i915: fix whitelist selftests with readonly registers Lionel Landwerlin
@ 2019-06-27 9:01 ` Lionel Landwerlin
2019-06-27 11:53 ` Chris Wilson
2019-06-27 9:01 ` [PATCH v6 3/3] drm/i915/icl: " Lionel Landwerlin
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2019-06-27 9:01 UTC (permalink / raw)
To: intel-gfx
CFL:C0+ changed the status of those registers which are now
blacklisted by default.
This is breaking a number of CTS tests on GL & Vulkan :
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
v2: Only use one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 993804d09517..b117583e38bb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1092,10 +1092,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
static void cfl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
if (engine->class != RENDER_CLASS)
return;
- gen9_whitelist_build(&engine->whitelist);
+ gen9_whitelist_build(w);
+
+ /*
+ * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
+ *
+ * This covers 4 register which are next to one another :
+ * - PS_INVOCATION_COUNT
+ * - PS_INVOCATION_COUNT_UDW
+ * - PS_DEPTH_COUNT
+ * - PS_DEPTH_COUNT_UDW
+ */
+ whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+ RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void cnl_whitelist_build(struct intel_engine_cs *engine)
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
2019-06-27 9:01 ` [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT Lionel Landwerlin
@ 2019-06-27 11:53 ` Chris Wilson
2019-06-27 23:53 ` Lionel Landwerlin
0 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2019-06-27 11:53 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-06-27 10:01:15)
> CFL:C0+ changed the status of those registers which are now
> blacklisted by default.
>
> This is breaking a number of CTS tests on GL & Vulkan :
>
> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)
>
> dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
>
> v2: Only use one whitelist entry (Lionel)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 993804d09517..b117583e38bb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1092,10 +1092,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
>
> static void cfl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> if (engine->class != RENDER_CLASS)
> return;
>
> - gen9_whitelist_build(&engine->whitelist);
> + gen9_whitelist_build(w);
> +
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
> + *
> + * This covers 4 register which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
Magic! As we can't rely on our selftests to verify that this allows
access from user batches, could you poke Anuj for another tested by?
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
2019-06-27 11:53 ` Chris Wilson
@ 2019-06-27 23:53 ` Lionel Landwerlin
2019-06-28 0:25 ` Chris Wilson
0 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2019-06-27 23:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/06/2019 14:53, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-06-27 10:01:15)
>> CFL:C0+ changed the status of those registers which are now
>> blacklisted by default.
>>
>> This is breaking a number of CTS tests on GL & Vulkan :
>>
>> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)
>>
>> dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
>>
>> v2: Only use one whitelist entry (Lionel)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 ++++++++++++++++-
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 993804d09517..b117583e38bb 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1092,10 +1092,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
>>
>> static void cfl_whitelist_build(struct intel_engine_cs *engine)
>> {
>> + struct i915_wa_list *w = &engine->whitelist;
>> +
>> if (engine->class != RENDER_CLASS)
>> return;
>>
>> - gen9_whitelist_build(&engine->whitelist);
>> + gen9_whitelist_build(w);
>> +
>> + /*
>> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
>> + *
>> + * This covers 4 register which are next to one another :
>> + * - PS_INVOCATION_COUNT
>> + * - PS_INVOCATION_COUNT_UDW
>> + * - PS_DEPTH_COUNT
>> + * - PS_DEPTH_COUNT_UDW
>> + */
>> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>> + RING_FORCE_TO_NONPRIV_RD |
>> + RING_FORCE_TO_NONPRIV_RANGE_4);
> Magic! As we can't rely on our selftests to verify that this allows
> access from user batches, could you poke Anuj for another tested by?
> -Chris
>
I'll let Anuj answer.
Do I need Cc: stable@vger.kernel.org ?
-Lionel
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
2019-06-27 23:53 ` Lionel Landwerlin
@ 2019-06-28 0:25 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2019-06-28 0:25 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-06-28 00:53:09)
> On 27/06/2019 14:53, Chris Wilson wrote:
> > Magic! As we can't rely on our selftests to verify that this allows
> > access from user batches, could you poke Anuj for another tested by?
> > -Chris
> >
> I'll let Anuj answer.
>
> Do I need Cc: stable@vger.kernel.org ?
Yes, you need this for working userspace on released systems so
backporting is required.
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
2019-06-27 9:01 ` [PATCH v6 1/3] drm/i915: fix whitelist selftests with readonly registers Lionel Landwerlin
2019-06-27 9:01 ` [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT Lionel Landwerlin
@ 2019-06-27 9:01 ` Lionel Landwerlin
2019-06-27 10:03 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTS fixes (rev6) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Lionel Landwerlin @ 2019-06-27 9:01 UTC (permalink / raw)
To: intel-gfx
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
v2: Use only one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b117583e38bb..a908d829d6bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1138,6 +1138,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
/* WaEnableStateCacheRedirectToCS:icl */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+
+ /*
+ * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
+ *
+ * This covers 4 register which are next to one another :
+ * - PS_INVOCATION_COUNT
+ * - PS_INVOCATION_COUNT_UDW
+ * - PS_DEPTH_COUNT
+ * - PS_DEPTH_COUNT_UDW
+ */
+ whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+ RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
break;
case VIDEO_DECODE_CLASS:
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 13+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTS fixes (rev6)
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
` (2 preceding siblings ...)
2019-06-27 9:01 ` [PATCH v6 3/3] drm/i915/icl: " Lionel Landwerlin
@ 2019-06-27 10:03 ` Patchwork
2019-06-27 10:38 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-28 9:52 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-06-27 10:03 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTS fixes (rev6)
URL : https://patchwork.freedesktop.org/series/62437/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
810e2eae3f1b drm/i915: fix whitelist selftests with readonly registers
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12:
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
total: 0 errors, 1 warnings, 0 checks, 9 lines checked
5ce4bb57b4e1 drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11:
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
8230d46384b3 drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
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^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: CTS fixes (rev6)
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
` (3 preceding siblings ...)
2019-06-27 10:03 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTS fixes (rev6) Patchwork
@ 2019-06-27 10:38 ` Patchwork
2019-06-27 11:20 ` Lionel Landwerlin
2019-06-28 9:52 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2019-06-27 10:38 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTS fixes (rev6)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6373 -> Patchwork_13451
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/
Known issues
------------
Here are the changes found in Patchwork_13451 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-icl-u3/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-icl-u3/igt@debugfs_test@read_all_entries.html
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#110566])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-cml-u2/igt@gem_ctx_create@basic-files.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-cml-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-cml-u: [PASS][5] -> [INCOMPLETE][6] ([fdo#110566])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-cml-u/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-cml-u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-r: [PASS][7] -> [DMESG-WARN][8] ([fdo#111012])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-kbl-r/igt@i915_pm_rpm@basic-pci-d3-state.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-kbl-r/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-ilk-650: [PASS][9] -> [DMESG-WARN][10] ([fdo#106387])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-ilk-650/igt@kms_force_connector_basic@force-connector-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-ilk-650/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][11] -> [DMESG-WARN][12] ([fdo#102614])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-gtt:
- fi-icl-dsi: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-icl-dsi/igt@prime_vgem@basic-gtt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-icl-dsi/igt@prime_vgem@basic-gtt.html
#### Possible fixes ####
* igt@gem_ctx_switch@basic-default:
- fi-icl-u2: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-icl-u2/igt@gem_ctx_switch@basic-default.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-icl-u2/igt@gem_ctx_switch@basic-default.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
* igt@gem_mmap@basic-small-bo:
- fi-icl-dsi: [DMESG-WARN][19] ([fdo#106107]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-icl-dsi/igt@gem_mmap@basic-small-bo.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-icl-dsi/igt@gem_mmap@basic-small-bo.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][21] ([fdo#108511]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
Participating hosts (52 -> 44)
------------------------------
Additional (1): fi-skl-gvtdvm
Missing (9): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6373 -> Patchwork_13451
CI_DRM_6373: cc7ffe2a301509ba233652ec17d0f74c18b5c8a9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5069: 439a9f5d615f31f03cc3a3a5cbab19367a1af763 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13451: 8230d46384b3f9d9325e5397a833bae675012e60 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
8230d46384b3 drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
5ce4bb57b4e1 drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
810e2eae3f1b drm/i915: fix whitelist selftests with readonly registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: CTS fixes (rev6)
2019-06-27 9:01 [PATCH v6 0/3] drm/i915: CTS fixes Lionel Landwerlin
` (4 preceding siblings ...)
2019-06-27 10:38 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-06-28 9:52 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-06-28 9:52 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTS fixes (rev6)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6373_full -> Patchwork_13451_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13451_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb2/igt@gem_exec_balancer@smoke.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl6/igt@gem_workarounds@suspend-resume-context.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl1/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][7] -> [FAIL][8] ([fdo#104873])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +15 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-hsw7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@pipe-a-forked-move:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb2/igt@kms_cursor_legacy@pipe-a-forked-move.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb7/igt@kms_cursor_legacy@pipe-a-forked-move.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb2/igt@kms_psr@psr2_basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb5/igt@kms_psr@psr2_basic.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#100047])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb5/igt@kms_sysfs_edid_timing.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb3/igt@kms_sysfs_edid_timing.html
- shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#100047])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-hsw1/igt@kms_sysfs_edid_timing.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-hsw1/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [SKIP][25] ([fdo#109271]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-snb4/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rpm@i2c:
- shard-hsw: [FAIL][27] ([fdo#104097]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-hsw1/igt@i915_pm_rpm@i2c.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-hsw7/igt@i915_pm_rpm@i2c.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: [DMESG-WARN][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-apl5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-apl3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][31] ([fdo#105363]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][33] ([fdo#109507]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-hsw: [SKIP][37] ([fdo#109271]) -> [PASS][38] +21 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
- shard-skl: [FAIL][39] ([fdo#103167]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl9/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][41] ([fdo#108145] / [fdo#110403]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][43] ([fdo#109642]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb7/igt@kms_psr2_su@page_flip.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6373/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6373 -> Patchwork_13451
CI_DRM_6373: cc7ffe2a301509ba233652ec17d0f74c18b5c8a9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5069: 439a9f5d615f31f03cc3a3a5cbab19367a1af763 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13451: 8230d46384b3f9d9325e5397a833bae675012e60 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13451/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread