* [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
@ 2019-07-02 5:54 Ramalingam C
2019-07-02 17:04 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Ramalingam C @ 2019-07-02 5:54 UTC (permalink / raw)
To: shashank.sharma, Daniel Vetter, intel-gfx
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++++++++++++++--------
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 120 +++++++++++++++--
drivers/gpu/drm/i915/intel_drv.h | 8 ++
4 files changed, 221 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bc3a94d491c4..14ba723a3561 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,6 +17,7 @@
#include "intel_drv.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(PORT_HDCP_STATUS(port));
+ reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
return reg & HDCP_STATUS_ENC;
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(HDCP2_STATUS_DDI(port));
+ reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
return reg & LINK_ENCRYPTION_STATUS;
}
@@ -253,37 +252,59 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- enum port port = intel_dig_port->base.port;
- switch (port) {
- case PORT_A:
- return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
- case PORT_B:
- return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
- case PORT_C:
- return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
- case PORT_D:
- return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
- case PORT_E:
- return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
- default:
- break;
- }
- DRM_ERROR("Unknown port %d\n", port);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (pipe) {
+ case PIPE_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case PIPE_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case PIPE_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ /* FIXME: Add a case for PIPE_D */
+ default:
+ DRM_ERROR("Unknown pipe %d\n", pipe);
+ break;
+ }
+ } else {
+ switch (port) {
+ case PORT_A:
+ return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
+ case PORT_B:
+ return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
+ case PORT_C:
+ return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
+ case PORT_D:
+ return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
+ case PORT_E:
+ return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
+ default:
+ DRM_ERROR("Unknown port %d\n", port);
+ break;
+ }
+ }
return -EINVAL;
}
static
-int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+int intel_hdcp_validate_v_prime(struct intel_connector *connector,
const struct intel_hdcp_shim *shim,
u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
struct drm_i915_private *dev_priv;
+ enum pipe pipe = connector->hdcp.pipe;
+ enum port port;
u32 vprime, sha_text, sha_leftovers, rep_ctl;
int ret, i, j, sha_idx;
dev_priv = intel_dig_port->base.base.dev->dev_private;
+ port = intel_dig_port->base.port;
/* Process V' values from the receiver */
for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
@@ -306,7 +327,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
sha_idx = 0;
sha_text = 0;
sha_leftovers = 0;
- rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
+ rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, pipe, port);
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
for (i = 0; i < num_downstream; i++) {
unsigned int sha_empty;
@@ -544,7 +565,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
* V prime atleast twice.
*/
for (i = 0; i < tries; i++) {
- ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
+ ret = intel_hdcp_validate_v_prime(connector, shim,
ksv_fifo, num_downstream,
bstatus);
if (!ret)
@@ -572,6 +593,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
struct drm_device *dev = connector->base.dev;
const struct intel_hdcp_shim *shim = hdcp->shim;
struct drm_i915_private *dev_priv;
+ enum pipe pipe = connector->hdcp.pipe;
enum port port;
unsigned long r0_prime_gen_start;
int ret, i, tries = 2;
@@ -611,19 +633,20 @@ static int intel_hdcp_auth(struct intel_connector *connector)
/* Initialize An with 2 random values and acquire it */
for (i = 0; i < 2; i++)
- I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
- I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
+ I915_WRITE(HDCP_ANINIT(dev_priv, pipe, port), get_random_u32());
+ I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_CAPTURE_AN);
/* Wait for An to be acquired */
- if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore,
+ HDCP_STATUS(dev_priv, pipe, port),
HDCP_STATUS_AN_READY,
HDCP_STATUS_AN_READY, 1)) {
DRM_ERROR("Timed out waiting for An\n");
return -ETIMEDOUT;
}
- an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
- an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
+ an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, pipe, port));
+ an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, pipe, port));
ret = shim->write_an_aksv(intel_dig_port, an.shim);
if (ret)
return ret;
@@ -641,24 +664,24 @@ static int intel_hdcp_auth(struct intel_connector *connector)
return -EPERM;
}
- I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
- I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
+ I915_WRITE(HDCP_BKSVLO(dev_priv, pipe, port), bksv.reg[0]);
+ I915_WRITE(HDCP_BKSVHI(dev_priv, pipe, port), bksv.reg[1]);
ret = shim->repeater_present(intel_dig_port, &repeater_present);
if (ret)
return ret;
if (repeater_present)
I915_WRITE(HDCP_REP_CTL,
- intel_hdcp_get_repeater_ctl(intel_dig_port));
+ intel_hdcp_get_repeater_ctl(dev_priv, pipe, port));
ret = shim->toggle_signalling(intel_dig_port, true);
if (ret)
return ret;
- I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
+ I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_AUTH_AND_ENC);
/* Wait for R0 ready */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
(HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Timed out waiting for R0 ready\n");
return -ETIMEDOUT;
@@ -686,22 +709,23 @@ static int intel_hdcp_auth(struct intel_connector *connector)
ret = shim->read_ri_prime(intel_dig_port, ri.shim);
if (ret)
return ret;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
/* Wait for Ri prime match */
- if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
break;
}
if (i == tries) {
DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
return -ETIMEDOUT;
}
/* Wait for encryption confirmation */
- if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore,
+ HDCP_STATUS(dev_priv, pipe, port),
HDCP_STATUS_ENC, HDCP_STATUS_ENC,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Timed out waiting for encryption\n");
@@ -726,15 +750,16 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
+ enum pipe pipe = hdcp->pipe;
int ret;
DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
hdcp->hdcp_encrypted = false;
- I915_WRITE(PORT_HDCP_CONF(port), 0);
+ I915_WRITE(HDCP_CONF(dev_priv, pipe, port), 0);
if (intel_wait_for_register(&dev_priv->uncore,
- PORT_HDCP_STATUS(port), ~0, 0,
+ HDCP_STATUS(dev_priv, pipe, port), ~0, 0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -806,9 +831,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
+ enum pipe pipe;
int ret = 0;
mutex_lock(&hdcp->mutex);
+ pipe = hdcp->pipe;
/* Check_link valid only when HDCP1.4 is enabled */
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
@@ -817,10 +844,10 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp_in_use(connector))) {
+ if (WARN_ON(!intel_hdcp_in_use(dev_priv, pipe, port))) {
DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
connector->base.name, connector->base.base.id,
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
ret = -ENXIO;
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
schedule_work(&hdcp->prop_work);
@@ -1491,10 +1518,11 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum pipe pipe = hdcp->pipe;
int ret;
- WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
-
+ WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
+ LINK_ENCRYPTION_STATUS);
if (hdcp->shim->toggle_signalling) {
ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
if (ret) {
@@ -1504,14 +1532,15 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
}
}
- if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
+ if (I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) & LINK_AUTH_STATUS) {
/* Link is Authenticated. Now set for Encryption */
- I915_WRITE(HDCP2_CTL_DDI(port),
- I915_READ(HDCP2_CTL_DDI(port)) |
+ I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
+ I915_READ(HDCP2_CTL(dev_priv, pipe, port)) |
CTL_LINK_ENCRYPTION_REQ);
}
- ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
+ ret = intel_wait_for_register(&dev_priv->uncore,
+ HDCP2_STATUS(dev_priv, pipe, port),
LINK_ENCRYPTION_STATUS,
LINK_ENCRYPTION_STATUS,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
@@ -1525,14 +1554,17 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum pipe pipe = hdcp->pipe;
int ret;
- WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
+ WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
+ LINK_ENCRYPTION_STATUS));
+ I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
+ I915_READ(HDCP2_CTL(dev_priv, pipe, port)) &
+ ~CTL_LINK_ENCRYPTION_REQ);
- I915_WRITE(HDCP2_CTL_DDI(port),
- I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
-
- ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
+ ret = intel_wait_for_register(&dev_priv->uncore,
+ HDCP2_STATUS(dev_priv, pipe, port),
LINK_ENCRYPTION_STATUS, 0x0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
@@ -1631,9 +1663,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum pipe pipe;
int ret = 0;
mutex_lock(&hdcp->mutex);
+ pipe = hdcp->pipe;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
@@ -1642,9 +1676,9 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp2_in_use(connector))) {
+ if (WARN_ON(!intel_hdcp2_in_use(dev_priv, pipe, port))) {
DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
- I915_READ(HDCP2_STATUS_DDI(port)));
+ I915_READ(HDCP2_STATUS(dev_priv, pipe, port)));
ret = -ENXIO;
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
schedule_work(&hdcp->prop_work);
@@ -1857,6 +1891,9 @@ int intel_hdcp_enable(struct intel_connector *connector)
mutex_lock(&hdcp->mutex);
WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ /* FIXME: Need to take the drm modeset lock for connection_mutex. */
+ hdcp->pipe = intel_connector_get_pipe(connector);
+
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
* is capable of HDCP2.2, it is preferred to use HDCP2.2.
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..2096aee174b2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
{
struct drm_i915_private *dev_priv =
intel_dig_port->base.base.dev->dev_private;
+ struct intel_connector *connector =
+ intel_dig_port->hdmi.attached_connector;
enum port port = intel_dig_port->base.port;
+ enum pipe pipe = connector->hdcp.pipe;
int ret;
union {
u32 reg;
@@ -1502,13 +1505,13 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
if (ret)
return false;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
/* Wait for Ri prime match */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
return false;
}
return true;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..2306e83b16fc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9225,12 +9225,20 @@ enum skl_power_gate {
/* HDCP Repeater Registers */
#define HDCP_REP_CTL _MMIO(0x66d00)
+#define HDCP_TRANSA_REP_PRESENT BIT(31)
+#define HDCP_TRANSB_REP_PRESENT BIT(30)
+#define HDCP_TRANSC_REP_PRESENT BIT(29)
+#define HDCP_TRANSD_REP_PRESENT BIT(28)
#define HDCP_DDIB_REP_PRESENT BIT(30)
#define HDCP_DDIA_REP_PRESENT BIT(29)
#define HDCP_DDIC_REP_PRESENT BIT(28)
#define HDCP_DDID_REP_PRESENT BIT(27)
#define HDCP_DDIF_REP_PRESENT BIT(26)
#define HDCP_DDIE_REP_PRESENT BIT(25)
+#define HDCP_TRANSA_SHA1_M0 (1 << 20)
+#define HDCP_TRANSB_SHA1_M0 (2 << 20)
+#define HDCP_TRANSC_SHA1_M0 (3 << 20)
+#define HDCP_TRANSD_SHA1_M0 (4 << 20)
#define HDCP_DDIB_SHA1_M0 (1 << 20)
#define HDCP_DDIA_SHA1_M0 (2 << 20)
#define HDCP_DDIC_SHA1_M0 (3 << 20)
@@ -9270,15 +9278,89 @@ enum skl_power_gate {
_PORTE_HDCP_AUTHENC, \
_PORTF_HDCP_AUTHENC) + (x))
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
+#define _TRANSA_HDCP_CONF 0x66400
+#define _TRANSB_HDCP_CONF 0x66500
+#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
+ _TRANSB_HDCP_CONF)
+#define HDCP_CONF(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_CONF(pipe) : \
+ PORT_HDCP_CONF(port))
+
#define HDCP_CONF_CAPTURE_AN BIT(0)
#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
+#define _TRANSA_HDCP_ANINIT 0x66404
+#define _TRANSB_HDCP_ANINIT 0x66504
+#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_ANINIT, \
+ _TRANSB_HDCP_ANINIT)
+#define HDCP_ANINIT(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANINIT(pipe) : \
+ PORT_HDCP_ANINIT(port))
+
#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
+#define _TRANSA_HDCP_ANLO 0x66408
+#define _TRANSB_HDCP_ANLO 0x66508
+#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
+ _TRANSB_HDCP_ANLO)
+#define HDCP_ANLO(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANLO(pipe) : \
+ PORT_HDCP_ANLO(port))
+
#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
+#define _TRANSA_HDCP_ANHI 0x6640C
+#define _TRANSB_HDCP_ANHI 0x6650C
+#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
+ _TRANSB_HDCP_ANHI)
+#define HDCP_ANHI(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANHI(pipe) : \
+ PORT_HDCP_ANHI(port))
+
#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
+#define _TRANSA_HDCP_BKSVLO 0x66410
+#define _TRANSB_HDCP_BKSVLO 0x66510
+#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_BKSVLO, \
+ _TRANSB_HDCP_BKSVLO)
+#define HDCP_BKSVLO(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_BKSVLO(pipe) : \
+ PORT_HDCP_BKSVLO(port))
+
#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
+#define _TRANSA_HDCP_BKSVHI 0x66414
+#define _TRANSB_HDCP_BKSVHI 0x66514
+#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_BKSVHI, \
+ _TRANSB_HDCP_BKSVHI)
+#define HDCP_BKSVHI(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_BKSVHI(pipe) : \
+ PORT_HDCP_BKSVHI(port))
+
#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
+#define _TRANSA_HDCP_RPRIME 0x66418
+#define _TRANSB_HDCP_RPRIME 0x66518
+#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_RPRIME, \
+ _TRANSB_HDCP_RPRIME)
+#define HDCP_RPRIME(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_RPRIME(pipe) : \
+ PORT_HDCP_RPRIME(port))
+
#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
+#define _TRANSA_HDCP_STATUS 0x6641C
+#define _TRANSB_HDCP_STATUS 0x6651C
+#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_STATUS, \
+ _TRANSB_HDCP_STATUS)
+#define HDCP_STATUS(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_STATUS(pipe) : \
+ PORT_HDCP_STATUS(port))
+
#define HDCP_STATUS_STREAM_A_ENC BIT(31)
#define HDCP_STATUS_STREAM_B_ENC BIT(30)
#define HDCP_STATUS_STREAM_C_ENC BIT(29)
@@ -9305,23 +9387,43 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
-
-#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
+#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
+#define _TRANSA_HDCP2_AUTH 0x66498
+#define _TRANSB_HDCP2_AUTH 0x66598
+#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
+ _TRANSB_HDCP2_AUTH)
#define AUTH_LINK_AUTHENTICATED BIT(31)
#define AUTH_LINK_TYPE BIT(30)
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
#define AUTH_CLR_KEYS BIT(18)
-
-#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
+#define HDCP2_AUTH(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_AUTH(pipe) : \
+ PORT_HDCP2_AUTH(port))
+
+#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
+#define _TRANSA_HDCP2_CTL 0x664B0
+#define _TRANSB_HDCP2_CTL 0x665B0
+#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
+ _TRANSB_HDCP2_CTL)
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
-
-#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
-#define STREAM_ENCRYPTION_STATUS_A BIT(31)
-#define STREAM_ENCRYPTION_STATUS_B BIT(30)
-#define STREAM_ENCRYPTION_STATUS_C BIT(29)
+#define HDCP2_CTL(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_CTL(pipe) : \
+ PORT_HDCP2_CTL(port))
+
+#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
+#define _TRANSA_HDCP2_STATUS 0x664B4
+#define _TRANSB_HDCP2_STATUS 0x665B4
+#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_STATUS, \
+ _TRANSB_HDCP2_STATUS)
#define LINK_TYPE_STATUS BIT(22)
#define LINK_AUTH_STATUS BIT(21)
#define LINK_ENCRYPTION_STATUS BIT(20)
+#define HDCP2_STATUS(dev_priv, pipe, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_STATUS(pipe) : \
+ PORT_HDCP2_STATUS(port))
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..53f13e6a5a73 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -359,6 +359,14 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ /*
+ * Gen 12 onwards, HDCP is part of transcoder(previously DDI).
+ * So chacheing the pipe associated to connector at hdcp_enable
+ * would help in subsequent functions to derive the right offsets
+ * for HDCP registers.
+ */
+ enum pipe pipe;
};
struct intel_connector {
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
2019-07-02 5:54 [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
@ 2019-07-02 17:04 ` Patchwork
2019-07-03 15:02 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-09 4:09 ` [PATCH] " Sharma, Shashank
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-07-02 17:04 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
URL : https://patchwork.freedesktop.org/series/63074/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6396 -> Patchwork_13490
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_13490 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13490, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13490:
### IGT changes ###
#### Warnings ####
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: [INCOMPLETE][1] ([fdo#110976]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
Known issues
------------
Here are the changes found in Patchwork_13490 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-blb-e6850/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@kms_addfb_basic@tile-pitch-mismatch.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-u3/igt@kms_addfb_basic@tile-pitch-mismatch.html
#### Possible fixes ####
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@gem_basic@create-close.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-u3/igt@gem_basic@create-close.html
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_blt:
- fi-skl-iommu: [INCOMPLETE][11] ([fdo#108602]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-iommu/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-skl-iommu/igt@i915_selftest@live_blt.html
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976
Participating hosts (56 -> 46)
------------------------------
Missing (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6396 -> Patchwork_13490
CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13490: 4f21a937a4bd44dd48b1e2271e1a1d0552de3a4e @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
4f21a937a4bd drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
2019-07-02 5:54 [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-07-02 17:04 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-07-03 15:02 ` Patchwork
2019-07-09 4:09 ` [PATCH] " Sharma, Shashank
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-07-03 15:02 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
URL : https://patchwork.freedesktop.org/series/63074/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6396_full -> Patchwork_13490_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13490_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb4/igt@gem_exec_balancer@smoke.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][3] -> [FAIL][4] ([fdo#105363])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#108303])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb5/igt@kms_flip_tiling@flip-x-tiled.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb8/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103166])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl3/igt@perf@polling.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl9/igt@perf@polling.html
* igt@perf_pmu@cpu-hotplug:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb2/igt@perf_pmu@cpu-hotplug.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb7/igt@perf_pmu@cpu-hotplug.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-snb: [FAIL][23] ([fdo#109661]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-snb1/igt@gem_eio@unwedge-stress.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-snb4/igt@gem_eio@unwedge-stress.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [DMESG-WARN][25] ([fdo#108686]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-apl1/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [INCOMPLETE][27] ([fdo#104108]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl4/igt@gem_workarounds@suspend-resume-context.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl9/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@mock_requests:
- shard-skl: [INCOMPLETE][29] ([fdo#110550]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl8/igt@i915_selftest@mock_requests.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl8/igt@i915_selftest@mock_requests.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
- shard-hsw: [INCOMPLETE][31] ([fdo#103540]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-hsw7/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][33] ([fdo#109507]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl3/igt@kms_flip@flip-vs-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl9/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-iclb: [INCOMPLETE][39] ([fdo#106978] / [fdo#107713]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-skl: [FAIL][41] ([fdo#103167]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][43] ([fdo#108145]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb1/igt@kms_psr@psr2_suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb2/igt@kms_psr@psr2_suspend.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][47] ([fdo#107724]) -> [SKIP][48] ([fdo#109349])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110550]: https://bugs.freedesktop.org/show_bug.cgi?id=110550
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6396 -> Patchwork_13490
CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13490: 4f21a937a4bd44dd48b1e2271e1a1d0552de3a4e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
2019-07-09 4:09 ` [PATCH] " Sharma, Shashank
@ 2019-07-08 23:59 ` Ramalingam C
0 siblings, 0 replies; 5+ messages in thread
From: Ramalingam C @ 2019-07-08 23:59 UTC (permalink / raw)
To: Sharma, Shashank; +Cc: intel-gfx
On 2019-07-09 at 09:39:24 +0530, Sharma, Shashank wrote:
> Hello Ram,
>
> On 7/2/2019 11:24 AM, Ramalingam C wrote:
>
> > From Gen12 onwards, HDCP HW block is implemented within transcoders.
> > Till Gen11 HDCP HW block was part of DDI.
> >
> > Hence required changes in HW programming is handled here.
> >
> > v2:
> > _MMIO_TRANS is used [Lucas and Daniel]
> > platform check is moved into the caller [Lucas]
> > v3:
> > platform check is moved into a macro [Shashank]
> >
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++++++++++++++--------
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
> > drivers/gpu/drm/i915/i915_reg.h | 120 +++++++++++++++--
> > drivers/gpu/drm/i915/intel_drv.h | 8 ++
> > 4 files changed, 221 insertions(+), 71 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index bc3a94d491c4..14ba723a3561 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -17,6 +17,7 @@
> > #include "intel_drv.h"
> > #include "intel_hdcp.h"
> > #include "intel_sideband.h"
> > +#include "intel_connector.h"
> > #define KEY_LOAD_TRIES 5
> > #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> > @@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
> > return capable;
> > }
> > -static inline bool intel_hdcp_in_use(struct intel_connector *connector)
> > +static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
> > + enum pipe pipe, enum port port)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - enum port port = connector->encoder->port;
> > u32 reg;
> > - reg = I915_READ(PORT_HDCP_STATUS(port));
> > + reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
> > return reg & HDCP_STATUS_ENC;
> directly return I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> HDCP_STATUS_ENC; ?
Sure.
> > }
> > -static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
> > +static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
> > + enum pipe pipe, enum port port)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - enum port port = connector->encoder->port;
> > u32 reg;
> > - reg = I915_READ(HDCP2_STATUS_DDI(port));
> > + reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
> > return reg & LINK_ENCRYPTION_STATUS;
> same here
> > }
> > @@ -253,37 +252,59 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
> > }
> > static
> > -u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
> > +u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
> > + enum pipe pipe, enum port port)
> > {
> > - enum port port = intel_dig_port->base.port;
> > - switch (port) {
> > - case PORT_A:
> > - return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> > - case PORT_B:
> > - return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
> > - case PORT_C:
> > - return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
> > - case PORT_D:
> > - return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
> > - case PORT_E:
> > - return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> > - default:
> > - break;
> > - }
> > - DRM_ERROR("Unknown port %d\n", port);
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + switch (pipe) {
> > + case PIPE_A:
> > + return HDCP_TRANSA_REP_PRESENT |
> > + HDCP_TRANSA_SHA1_M0;
> > + case PIPE_B:
> > + return HDCP_TRANSB_REP_PRESENT |
> > + HDCP_TRANSB_SHA1_M0;
> > + case PIPE_C:
> > + return HDCP_TRANSC_REP_PRESENT |
> > + HDCP_TRANSC_SHA1_M0;
> > + /* FIXME: Add a case for PIPE_D */
> > + default:
> > + DRM_ERROR("Unknown pipe %d\n", pipe);
> > + break;
> > + }
>
> return -EINVAL here, then we don't need the else condition
>
> may be something like:
>
> ret = -EINVAL
>
> if (GEN >=12) {
>
> switch(pipe) {
>
> case PIPEA: ret = ; break;
>
> case PIPE_B: ret =; break;
>
> default: DRM_ERROR(); break;
>
> }
>
> return ret;
>
> }
>
> switch (port) {
>
> case PORT_A: ret = ;
>
> case PORT_B: ret =;
>
> default: DRM_ERROR();
>
> }
>
> return ret;
Was not thinking to remove the else part. perhaps will look better
without else.
>
> > + } else {
> > + switch (port) {
> > + case PORT_A:
> > + return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> > + case PORT_B:
> > + return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
> > + case PORT_C:
> > + return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
> > + case PORT_D:
> > + return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
> > + case PORT_E:
> > + return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> > + default:
> > + DRM_ERROR("Unknown port %d\n", port);
> > + break;
> > + }
> > + }
> > return -EINVAL;
> > }
> > static
> > -int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> > +int intel_hdcp_validate_v_prime(struct intel_connector *connector,
> > const struct intel_hdcp_shim *shim,
> > u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
> > {
> > + struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> > struct drm_i915_private *dev_priv;
> > + enum pipe pipe = connector->hdcp.pipe;
> > + enum port port;
> enum port port = intel_dig_port->base.port;?
sure.
> > u32 vprime, sha_text, sha_leftovers, rep_ctl;
> > int ret, i, j, sha_idx;
> > dev_priv = intel_dig_port->base.base.dev->dev_private;
> > + port = intel_dig_port->base.port;
> > /* Process V' values from the receiver */
> > for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
> > @@ -306,7 +327,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> > sha_idx = 0;
> > sha_text = 0;
> > sha_leftovers = 0;
> > - rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
> > + rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, pipe, port);
> > I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
> > for (i = 0; i < num_downstream; i++) {
> > unsigned int sha_empty;
> > @@ -544,7 +565,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> > * V prime atleast twice.
> > */
> > for (i = 0; i < tries; i++) {
> > - ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> > + ret = intel_hdcp_validate_v_prime(connector, shim,
> > ksv_fifo, num_downstream,
> > bstatus);
> > if (!ret)
> > @@ -572,6 +593,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > struct drm_device *dev = connector->base.dev;
> > const struct intel_hdcp_shim *shim = hdcp->shim;
> > struct drm_i915_private *dev_priv;
> > + enum pipe pipe = connector->hdcp.pipe;
> > enum port port;
> > unsigned long r0_prime_gen_start;
> > int ret, i, tries = 2;
> > @@ -611,19 +633,20 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > /* Initialize An with 2 random values and acquire it */
> > for (i = 0; i < 2; i++)
> > - I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
> > - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
> > + I915_WRITE(HDCP_ANINIT(dev_priv, pipe, port), get_random_u32());
> > + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_CAPTURE_AN);
> > /* Wait for An to be acquired */
> > - if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
> > + if (intel_wait_for_register(&dev_priv->uncore,
> > + HDCP_STATUS(dev_priv, pipe, port),
> > HDCP_STATUS_AN_READY,
> > HDCP_STATUS_AN_READY, 1)) {
> > DRM_ERROR("Timed out waiting for An\n");
> > return -ETIMEDOUT;
> > }
> > - an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
> > - an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
> > + an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, pipe, port));
> > + an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, pipe, port));
> > ret = shim->write_an_aksv(intel_dig_port, an.shim);
> > if (ret)
> > return ret;
> > @@ -641,24 +664,24 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > return -EPERM;
> > }
> > - I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
> > - I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
> > + I915_WRITE(HDCP_BKSVLO(dev_priv, pipe, port), bksv.reg[0]);
> > + I915_WRITE(HDCP_BKSVHI(dev_priv, pipe, port), bksv.reg[1]);
> > ret = shim->repeater_present(intel_dig_port, &repeater_present);
> > if (ret)
> > return ret;
> > if (repeater_present)
> > I915_WRITE(HDCP_REP_CTL,
> > - intel_hdcp_get_repeater_ctl(intel_dig_port));
> > + intel_hdcp_get_repeater_ctl(dev_priv, pipe, port));
> > ret = shim->toggle_signalling(intel_dig_port, true);
> > if (ret)
> > return ret;
> > - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
> > + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_AUTH_AND_ENC);
> > /* Wait for R0 ready */
> > - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> > + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> > (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
> > DRM_ERROR("Timed out waiting for R0 ready\n");
> > return -ETIMEDOUT;
> > @@ -686,22 +709,23 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> > if (ret)
> > return ret;
> > - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> > + I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
> > /* Wait for Ri prime match */
> > - if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> > + if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> > break;
> > }
> > if (i == tries) {
> > DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
> > - I915_READ(PORT_HDCP_STATUS(port)));
> > + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> > return -ETIMEDOUT;
> > }
> > /* Wait for encryption confirmation */
> > - if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
> > + if (intel_wait_for_register(&dev_priv->uncore,
> > + HDCP_STATUS(dev_priv, pipe, port),
> > HDCP_STATUS_ENC, HDCP_STATUS_ENC,
> > ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > DRM_ERROR("Timed out waiting for encryption\n");
> > @@ -726,15 +750,16 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> > struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> > struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> > enum port port = intel_dig_port->base.port;
> > + enum pipe pipe = hdcp->pipe;
> > int ret;
> > DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> > hdcp->hdcp_encrypted = false;
> > - I915_WRITE(PORT_HDCP_CONF(port), 0);
> > + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), 0);
> > if (intel_wait_for_register(&dev_priv->uncore,
> > - PORT_HDCP_STATUS(port), ~0, 0,
> > + HDCP_STATUS(dev_priv, pipe, port), ~0, 0,
> > ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
> > return -ETIMEDOUT;
> > @@ -806,9 +831,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
> > struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> > struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> > enum port port = intel_dig_port->base.port;
> > + enum pipe pipe;
> > int ret = 0;
> > mutex_lock(&hdcp->mutex);
> > + pipe = hdcp->pipe;
> > /* Check_link valid only when HDCP1.4 is enabled */
> > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> > @@ -817,10 +844,10 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
> > goto out;
> > }
> > - if (WARN_ON(!intel_hdcp_in_use(connector))) {
> > + if (WARN_ON(!intel_hdcp_in_use(dev_priv, pipe, port))) {
> > DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
> > connector->base.name, connector->base.base.id,
> > - I915_READ(PORT_HDCP_STATUS(port)));
> > + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> > ret = -ENXIO;
> > hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> > schedule_work(&hdcp->prop_work);
> > @@ -1491,10 +1518,11 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > enum port port = connector->encoder->port;
> > + enum pipe pipe = hdcp->pipe;
> > int ret;
> > - WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
> > -
> > + WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
> > + LINK_ENCRYPTION_STATUS);
> > if (hdcp->shim->toggle_signalling) {
> > ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
> > if (ret) {
> > @@ -1504,14 +1532,15 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > }
> > }
> > - if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
> > + if (I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) & LINK_AUTH_STATUS) {
> > /* Link is Authenticated. Now set for Encryption */
> > - I915_WRITE(HDCP2_CTL_DDI(port),
> > - I915_READ(HDCP2_CTL_DDI(port)) |
> > + I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
> > + I915_READ(HDCP2_CTL(dev_priv, pipe, port)) |
> > CTL_LINK_ENCRYPTION_REQ);
> > }
> > - ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
> > + ret = intel_wait_for_register(&dev_priv->uncore,
> > + HDCP2_STATUS(dev_priv, pipe, port),
> > LINK_ENCRYPTION_STATUS,
> > LINK_ENCRYPTION_STATUS,
> > ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > @@ -1525,14 +1554,17 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > enum port port = connector->encoder->port;
> > + enum pipe pipe = hdcp->pipe;
> > int ret;
> > - WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
> > + WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
> > + LINK_ENCRYPTION_STATUS));
> > + I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
> > + I915_READ(HDCP2_CTL(dev_priv, pipe, port)) &
> > + ~CTL_LINK_ENCRYPTION_REQ);
> > - I915_WRITE(HDCP2_CTL_DDI(port),
> > - I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
> > -
> > - ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
> > + ret = intel_wait_for_register(&dev_priv->uncore,
> > + HDCP2_STATUS(dev_priv, pipe, port),
> > LINK_ENCRYPTION_STATUS, 0x0,
> > ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > if (ret == -ETIMEDOUT)
> > @@ -1631,9 +1663,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > enum port port = connector->encoder->port;
> > + enum pipe pipe;
> > int ret = 0;
> > mutex_lock(&hdcp->mutex);
> > + pipe = hdcp->pipe;
> > /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
> > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> > @@ -1642,9 +1676,9 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> > goto out;
> > }
> > - if (WARN_ON(!intel_hdcp2_in_use(connector))) {
> > + if (WARN_ON(!intel_hdcp2_in_use(dev_priv, pipe, port))) {
> > DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
> > - I915_READ(HDCP2_STATUS_DDI(port)));
> > + I915_READ(HDCP2_STATUS(dev_priv, pipe, port)));
> > ret = -ENXIO;
> > hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> > schedule_work(&hdcp->prop_work);
> > @@ -1857,6 +1891,9 @@ int intel_hdcp_enable(struct intel_connector *connector)
> > mutex_lock(&hdcp->mutex);
> > WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> > + /* FIXME: Need to take the drm modeset lock for connection_mutex. */
> And we can't take this right now because.... ?
Sorry this FIXME is supposed to be removed. drm mode set lock is already
acquired at this point in time.
> > + hdcp->pipe = intel_connector_get_pipe(connector);
> > +
> > /*
> > * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> > * is capable of HDCP2.2, it is preferred to use HDCP2.2.
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0ebec69bbbfc..2096aee174b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> > {
> > struct drm_i915_private *dev_priv =
> > intel_dig_port->base.base.dev->dev_private;
> > + struct intel_connector *connector =
> > + intel_dig_port->hdmi.attached_connector;
> > enum port port = intel_dig_port->base.port;
> > + enum pipe pipe = connector->hdcp.pipe;
> > int ret;
> > union {
> > u32 reg;
> > @@ -1502,13 +1505,13 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> > if (ret)
> > return false;
> > - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> > + I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
> > /* Wait for Ri prime match */
> > - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> > + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> > DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
> > - I915_READ(PORT_HDCP_STATUS(port)));
> > + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> > return false;
> > }
> > return true;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7e6009cefb18..2306e83b16fc 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9225,12 +9225,20 @@ enum skl_power_gate {
> > /* HDCP Repeater Registers */
> > #define HDCP_REP_CTL _MMIO(0x66d00)
> > +#define HDCP_TRANSA_REP_PRESENT BIT(31)
> > +#define HDCP_TRANSB_REP_PRESENT BIT(30)
> > +#define HDCP_TRANSC_REP_PRESENT BIT(29)
> > +#define HDCP_TRANSD_REP_PRESENT BIT(28)
> > #define HDCP_DDIB_REP_PRESENT BIT(30)
> > #define HDCP_DDIA_REP_PRESENT BIT(29)
> > #define HDCP_DDIC_REP_PRESENT BIT(28)
> > #define HDCP_DDID_REP_PRESENT BIT(27)
> > #define HDCP_DDIF_REP_PRESENT BIT(26)
> > #define HDCP_DDIE_REP_PRESENT BIT(25)
> > +#define HDCP_TRANSA_SHA1_M0 (1 << 20)
> > +#define HDCP_TRANSB_SHA1_M0 (2 << 20)
> > +#define HDCP_TRANSC_SHA1_M0 (3 << 20)
> > +#define HDCP_TRANSD_SHA1_M0 (4 << 20)
> > #define HDCP_DDIB_SHA1_M0 (1 << 20)
> > #define HDCP_DDIA_SHA1_M0 (2 << 20)
> > #define HDCP_DDIC_SHA1_M0 (3 << 20)
> > @@ -9270,15 +9278,89 @@ enum skl_power_gate {
> > _PORTE_HDCP_AUTHENC, \
> > _PORTF_HDCP_AUTHENC) + (x))
> > #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
> > +#define _TRANSA_HDCP_CONF 0x66400
> > +#define _TRANSB_HDCP_CONF 0x66500
> > +#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
> > + _TRANSB_HDCP_CONF)
> > +#define HDCP_CONF(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_CONF(pipe) : \
> > + PORT_HDCP_CONF(port))
> Alignment
Shashank,
in diff this looks misaligned. But in file this is in place.
-Ram
> > +
> > #define HDCP_CONF_CAPTURE_AN BIT(0)
> > #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
> > #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
> > +#define _TRANSA_HDCP_ANINIT 0x66404
> > +#define _TRANSB_HDCP_ANINIT 0x66504
> > +#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP_ANINIT, \
> > + _TRANSB_HDCP_ANINIT)
> > +#define HDCP_ANINIT(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_ANINIT(pipe) : \
> > + PORT_HDCP_ANINIT(port))
> Alignment
> > +
> > #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
> > +#define _TRANSA_HDCP_ANLO 0x66408
> > +#define _TRANSB_HDCP_ANLO 0x66508
> > +#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
> > + _TRANSB_HDCP_ANLO)
> > +#define HDCP_ANLO(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_ANLO(pipe) : \
> > + PORT_HDCP_ANLO(port))
> > +
> Alignment
> > #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
> > +#define _TRANSA_HDCP_ANHI 0x6640C
> > +#define _TRANSB_HDCP_ANHI 0x6650C
> > +#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
> > + _TRANSB_HDCP_ANHI)
> > +#define HDCP_ANHI(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_ANHI(pipe) : \
> > + PORT_HDCP_ANHI(port))
> > +
> Alignment
> > #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
> > +#define _TRANSA_HDCP_BKSVLO 0x66410
> > +#define _TRANSB_HDCP_BKSVLO 0x66510
> > +#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP_BKSVLO, \
> > + _TRANSB_HDCP_BKSVLO)
> > +#define HDCP_BKSVLO(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_BKSVLO(pipe) : \
> > + PORT_HDCP_BKSVLO(port))
> > +
> Alignment
> > #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
> > +#define _TRANSA_HDCP_BKSVHI 0x66414
> > +#define _TRANSB_HDCP_BKSVHI 0x66514
> > +#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP_BKSVHI, \
> > + _TRANSB_HDCP_BKSVHI)
> > +#define HDCP_BKSVHI(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_BKSVHI(pipe) : \
> > + PORT_HDCP_BKSVHI(port))
> > +
> Alignment
> > #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
> > +#define _TRANSA_HDCP_RPRIME 0x66418
> > +#define _TRANSB_HDCP_RPRIME 0x66518
> > +#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP_RPRIME, \
> > + _TRANSB_HDCP_RPRIME)
> > +#define HDCP_RPRIME(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_RPRIME(pipe) : \
> > + PORT_HDCP_RPRIME(port))
> > +
> Alignment
> > #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
> > +#define _TRANSA_HDCP_STATUS 0x6641C
> > +#define _TRANSB_HDCP_STATUS 0x6651C
> > +#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP_STATUS, \
> > + _TRANSB_HDCP_STATUS)
> > +#define HDCP_STATUS(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP_STATUS(pipe) : \
> > + PORT_HDCP_STATUS(port))
> > +
> Alignment
> > #define HDCP_STATUS_STREAM_A_ENC BIT(31)
> > #define HDCP_STATUS_STREAM_B_ENC BIT(30)
> > #define HDCP_STATUS_STREAM_C_ENC BIT(29)
> > @@ -9305,23 +9387,43 @@ enum skl_power_gate {
> > _PORTD_HDCP2_BASE, \
> > _PORTE_HDCP2_BASE, \
> > _PORTF_HDCP2_BASE) + (x))
> > -
> > -#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
> > +#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> > +#define _TRANSA_HDCP2_AUTH 0x66498
> > +#define _TRANSB_HDCP2_AUTH 0x66598
> > +#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
> > + _TRANSB_HDCP2_AUTH)
> Alignment
> > #define AUTH_LINK_AUTHENTICATED BIT(31)
> > #define AUTH_LINK_TYPE BIT(30)
> > #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
> > #define AUTH_CLR_KEYS BIT(18)
> > -
> > -#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
> > +#define HDCP2_AUTH(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP2_AUTH(pipe) : \
> > + PORT_HDCP2_AUTH(port))
> > +
> > +#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
> > +#define _TRANSA_HDCP2_CTL 0x664B0
> > +#define _TRANSB_HDCP2_CTL 0x665B0
> > +#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
> > + _TRANSB_HDCP2_CTL)
> > #define CTL_LINK_ENCRYPTION_REQ BIT(31)
> > -
> > -#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
> > -#define STREAM_ENCRYPTION_STATUS_A BIT(31)
> > -#define STREAM_ENCRYPTION_STATUS_B BIT(30)
> > -#define STREAM_ENCRYPTION_STATUS_C BIT(29)
> > +#define HDCP2_CTL(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP2_CTL(pipe) : \
> > + PORT_HDCP2_CTL(port))
> > +
> Alignment
> > +#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
> > +#define _TRANSA_HDCP2_STATUS 0x664B4
> > +#define _TRANSB_HDCP2_STATUS 0x665B4
> > +#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
> > + _TRANSA_HDCP2_STATUS, \
> > + _TRANSB_HDCP2_STATUS)
> > #define LINK_TYPE_STATUS BIT(22)
> > #define LINK_AUTH_STATUS BIT(21)
> > #define LINK_ENCRYPTION_STATUS BIT(20)
> > +#define HDCP2_STATUS(dev_priv, pipe, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > + TRANS_HDCP2_STATUS(pipe) : \
> > + PORT_HDCP2_STATUS(port))
> > /* Per-pipe DDI Function Control */
> > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 1d58f7ec5d84..53f13e6a5a73 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -359,6 +359,14 @@ struct intel_hdcp {
> > wait_queue_head_t cp_irq_queue;
> > atomic_t cp_irq_count;
> > int cp_irq_count_cached;
> > +
> > + /*
> > + * Gen 12 onwards, HDCP is part of transcoder(previously DDI).
> > + * So chacheing the pipe associated to connector at hdcp_enable
> > + * would help in subsequent functions to derive the right offsets
> > + * for HDCP registers.
> > + */
> > + enum pipe pipe;
> > };
> > struct intel_connector {
> - Shashank
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
2019-07-02 5:54 [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-07-02 17:04 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-07-03 15:02 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-07-09 4:09 ` Sharma, Shashank
2019-07-08 23:59 ` Ramalingam C
2 siblings, 1 reply; 5+ messages in thread
From: Sharma, Shashank @ 2019-07-09 4:09 UTC (permalink / raw)
To: Ramalingam C, Daniel Vetter, intel-gfx
Hello Ram,
On 7/2/2019 11:24 AM, Ramalingam C wrote:
> From Gen12 onwards, HDCP HW block is implemented within transcoders.
> Till Gen11 HDCP HW block was part of DDI.
>
> Hence required changes in HW programming is handled here.
>
> v2:
> _MMIO_TRANS is used [Lucas and Daniel]
> platform check is moved into the caller [Lucas]
> v3:
> platform check is moved into a macro [Shashank]
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++++++++++++++--------
> drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
> drivers/gpu/drm/i915/i915_reg.h | 120 +++++++++++++++--
> drivers/gpu/drm/i915/intel_drv.h | 8 ++
> 4 files changed, 221 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index bc3a94d491c4..14ba723a3561 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -17,6 +17,7 @@
> #include "intel_drv.h"
> #include "intel_hdcp.h"
> #include "intel_sideband.h"
> +#include "intel_connector.h"
>
> #define KEY_LOAD_TRIES 5
> #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> @@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
> return capable;
> }
>
> -static inline bool intel_hdcp_in_use(struct intel_connector *connector)
> +static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum port port)
> {
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - enum port port = connector->encoder->port;
> u32 reg;
>
> - reg = I915_READ(PORT_HDCP_STATUS(port));
> + reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
> return reg & HDCP_STATUS_ENC;
directly return I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
HDCP_STATUS_ENC; ?
> }
>
> -static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
> +static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum port port)
> {
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - enum port port = connector->encoder->port;
> u32 reg;
>
> - reg = I915_READ(HDCP2_STATUS_DDI(port));
> + reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
> return reg & LINK_ENCRYPTION_STATUS;
same here
> }
>
> @@ -253,37 +252,59 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
> }
>
> static
> -u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
> +u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum port port)
> {
> - enum port port = intel_dig_port->base.port;
> - switch (port) {
> - case PORT_A:
> - return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> - case PORT_B:
> - return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
> - case PORT_C:
> - return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
> - case PORT_D:
> - return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
> - case PORT_E:
> - return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> - default:
> - break;
> - }
> - DRM_ERROR("Unknown port %d\n", port);
> + if (INTEL_GEN(dev_priv) >= 12) {
> + switch (pipe) {
> + case PIPE_A:
> + return HDCP_TRANSA_REP_PRESENT |
> + HDCP_TRANSA_SHA1_M0;
> + case PIPE_B:
> + return HDCP_TRANSB_REP_PRESENT |
> + HDCP_TRANSB_SHA1_M0;
> + case PIPE_C:
> + return HDCP_TRANSC_REP_PRESENT |
> + HDCP_TRANSC_SHA1_M0;
> + /* FIXME: Add a case for PIPE_D */
> + default:
> + DRM_ERROR("Unknown pipe %d\n", pipe);
> + break;
> + }
return -EINVAL here, then we don't need the else condition
may be something like:
ret = -EINVAL
if (GEN >=12) {
switch(pipe) {
case PIPEA: ret = ; break;
case PIPE_B: ret =; break;
default: DRM_ERROR(); break;
}
return ret;
}
switch (port) {
case PORT_A: ret = ;
case PORT_B: ret =;
default: DRM_ERROR();
}
return ret;
> + } else {
> + switch (port) {
> + case PORT_A:
> + return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> + case PORT_B:
> + return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
> + case PORT_C:
> + return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
> + case PORT_D:
> + return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
> + case PORT_E:
> + return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> + default:
> + DRM_ERROR("Unknown port %d\n", port);
> + break;
> + }
> + }
> return -EINVAL;
> }
>
> static
> -int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> +int intel_hdcp_validate_v_prime(struct intel_connector *connector,
> const struct intel_hdcp_shim *shim,
> u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
> {
> + struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> struct drm_i915_private *dev_priv;
> + enum pipe pipe = connector->hdcp.pipe;
> + enum port port;
enum port port = intel_dig_port->base.port;?
> u32 vprime, sha_text, sha_leftovers, rep_ctl;
> int ret, i, j, sha_idx;
>
> dev_priv = intel_dig_port->base.base.dev->dev_private;
> + port = intel_dig_port->base.port;
>
> /* Process V' values from the receiver */
> for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
> @@ -306,7 +327,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> sha_idx = 0;
> sha_text = 0;
> sha_leftovers = 0;
> - rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
> + rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, pipe, port);
> I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
> for (i = 0; i < num_downstream; i++) {
> unsigned int sha_empty;
> @@ -544,7 +565,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> * V prime atleast twice.
> */
> for (i = 0; i < tries; i++) {
> - ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> + ret = intel_hdcp_validate_v_prime(connector, shim,
> ksv_fifo, num_downstream,
> bstatus);
> if (!ret)
> @@ -572,6 +593,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> struct drm_device *dev = connector->base.dev;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> struct drm_i915_private *dev_priv;
> + enum pipe pipe = connector->hdcp.pipe;
> enum port port;
> unsigned long r0_prime_gen_start;
> int ret, i, tries = 2;
> @@ -611,19 +633,20 @@ static int intel_hdcp_auth(struct intel_connector *connector)
>
> /* Initialize An with 2 random values and acquire it */
> for (i = 0; i < 2; i++)
> - I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
> - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
> + I915_WRITE(HDCP_ANINIT(dev_priv, pipe, port), get_random_u32());
> + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_CAPTURE_AN);
>
> /* Wait for An to be acquired */
> - if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
> + if (intel_wait_for_register(&dev_priv->uncore,
> + HDCP_STATUS(dev_priv, pipe, port),
> HDCP_STATUS_AN_READY,
> HDCP_STATUS_AN_READY, 1)) {
> DRM_ERROR("Timed out waiting for An\n");
> return -ETIMEDOUT;
> }
>
> - an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
> - an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
> + an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, pipe, port));
> + an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, pipe, port));
> ret = shim->write_an_aksv(intel_dig_port, an.shim);
> if (ret)
> return ret;
> @@ -641,24 +664,24 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> return -EPERM;
> }
>
> - I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
> - I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
> + I915_WRITE(HDCP_BKSVLO(dev_priv, pipe, port), bksv.reg[0]);
> + I915_WRITE(HDCP_BKSVHI(dev_priv, pipe, port), bksv.reg[1]);
>
> ret = shim->repeater_present(intel_dig_port, &repeater_present);
> if (ret)
> return ret;
> if (repeater_present)
> I915_WRITE(HDCP_REP_CTL,
> - intel_hdcp_get_repeater_ctl(intel_dig_port));
> + intel_hdcp_get_repeater_ctl(dev_priv, pipe, port));
>
> ret = shim->toggle_signalling(intel_dig_port, true);
> if (ret)
> return ret;
>
> - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
> + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), HDCP_CONF_AUTH_AND_ENC);
>
> /* Wait for R0 ready */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
> DRM_ERROR("Timed out waiting for R0 ready\n");
> return -ETIMEDOUT;
> @@ -686,22 +709,23 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> if (ret)
> return ret;
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
>
> /* Wait for Ri prime match */
> - if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> break;
> }
>
> if (i == tries) {
> DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> return -ETIMEDOUT;
> }
>
> /* Wait for encryption confirmation */
> - if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
> + if (intel_wait_for_register(&dev_priv->uncore,
> + HDCP_STATUS(dev_priv, pipe, port),
> HDCP_STATUS_ENC, HDCP_STATUS_ENC,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> DRM_ERROR("Timed out waiting for encryption\n");
> @@ -726,15 +750,16 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> enum port port = intel_dig_port->base.port;
> + enum pipe pipe = hdcp->pipe;
> int ret;
>
> DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> hdcp->hdcp_encrypted = false;
> - I915_WRITE(PORT_HDCP_CONF(port), 0);
> + I915_WRITE(HDCP_CONF(dev_priv, pipe, port), 0);
> if (intel_wait_for_register(&dev_priv->uncore,
> - PORT_HDCP_STATUS(port), ~0, 0,
> + HDCP_STATUS(dev_priv, pipe, port), ~0, 0,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
> return -ETIMEDOUT;
> @@ -806,9 +831,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
> struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> enum port port = intel_dig_port->base.port;
> + enum pipe pipe;
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + pipe = hdcp->pipe;
>
> /* Check_link valid only when HDCP1.4 is enabled */
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -817,10 +844,10 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
> goto out;
> }
>
> - if (WARN_ON(!intel_hdcp_in_use(connector))) {
> + if (WARN_ON(!intel_hdcp_in_use(dev_priv, pipe, port))) {
> DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
> connector->base.name, connector->base.base.id,
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> ret = -ENXIO;
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> schedule_work(&hdcp->prop_work);
> @@ -1491,10 +1518,11 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum pipe pipe = hdcp->pipe;
> int ret;
>
> - WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
> -
> + WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
> + LINK_ENCRYPTION_STATUS);
> if (hdcp->shim->toggle_signalling) {
> ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
> if (ret) {
> @@ -1504,14 +1532,15 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> }
> }
>
> - if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
> + if (I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) & LINK_AUTH_STATUS) {
> /* Link is Authenticated. Now set for Encryption */
> - I915_WRITE(HDCP2_CTL_DDI(port),
> - I915_READ(HDCP2_CTL_DDI(port)) |
> + I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
> + I915_READ(HDCP2_CTL(dev_priv, pipe, port)) |
> CTL_LINK_ENCRYPTION_REQ);
> }
>
> - ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
> + ret = intel_wait_for_register(&dev_priv->uncore,
> + HDCP2_STATUS(dev_priv, pipe, port),
> LINK_ENCRYPTION_STATUS,
> LINK_ENCRYPTION_STATUS,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> @@ -1525,14 +1554,17 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum pipe pipe = hdcp->pipe;
> int ret;
>
> - WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
> + WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, pipe, port)) &
> + LINK_ENCRYPTION_STATUS));
> + I915_WRITE(HDCP2_CTL(dev_priv, pipe, port),
> + I915_READ(HDCP2_CTL(dev_priv, pipe, port)) &
> + ~CTL_LINK_ENCRYPTION_REQ);
>
> - I915_WRITE(HDCP2_CTL_DDI(port),
> - I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
> -
> - ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
> + ret = intel_wait_for_register(&dev_priv->uncore,
> + HDCP2_STATUS(dev_priv, pipe, port),
> LINK_ENCRYPTION_STATUS, 0x0,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> if (ret == -ETIMEDOUT)
> @@ -1631,9 +1663,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum pipe pipe;
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + pipe = hdcp->pipe;
>
> /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -1642,9 +1676,9 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> goto out;
> }
>
> - if (WARN_ON(!intel_hdcp2_in_use(connector))) {
> + if (WARN_ON(!intel_hdcp2_in_use(dev_priv, pipe, port))) {
> DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
> - I915_READ(HDCP2_STATUS_DDI(port)));
> + I915_READ(HDCP2_STATUS(dev_priv, pipe, port)));
> ret = -ENXIO;
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> schedule_work(&hdcp->prop_work);
> @@ -1857,6 +1891,9 @@ int intel_hdcp_enable(struct intel_connector *connector)
> mutex_lock(&hdcp->mutex);
> WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
>
> + /* FIXME: Need to take the drm modeset lock for connection_mutex. */
And we can't take this right now because.... ?
> + hdcp->pipe = intel_connector_get_pipe(connector);
> +
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> * is capable of HDCP2.2, it is preferred to use HDCP2.2.
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..2096aee174b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> {
> struct drm_i915_private *dev_priv =
> intel_dig_port->base.base.dev->dev_private;
> + struct intel_connector *connector =
> + intel_dig_port->hdmi.attached_connector;
> enum port port = intel_dig_port->base.port;
> + enum pipe pipe = connector->hdcp.pipe;
> int ret;
> union {
> u32 reg;
> @@ -1502,13 +1505,13 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> if (ret)
> return false;
>
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + I915_WRITE(HDCP_RPRIME(dev_priv, pipe, port), ri.reg);
>
> /* Wait for Ri prime match */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv, pipe, port)));
> return false;
> }
> return true;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e6009cefb18..2306e83b16fc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9225,12 +9225,20 @@ enum skl_power_gate {
>
> /* HDCP Repeater Registers */
> #define HDCP_REP_CTL _MMIO(0x66d00)
> +#define HDCP_TRANSA_REP_PRESENT BIT(31)
> +#define HDCP_TRANSB_REP_PRESENT BIT(30)
> +#define HDCP_TRANSC_REP_PRESENT BIT(29)
> +#define HDCP_TRANSD_REP_PRESENT BIT(28)
> #define HDCP_DDIB_REP_PRESENT BIT(30)
> #define HDCP_DDIA_REP_PRESENT BIT(29)
> #define HDCP_DDIC_REP_PRESENT BIT(28)
> #define HDCP_DDID_REP_PRESENT BIT(27)
> #define HDCP_DDIF_REP_PRESENT BIT(26)
> #define HDCP_DDIE_REP_PRESENT BIT(25)
> +#define HDCP_TRANSA_SHA1_M0 (1 << 20)
> +#define HDCP_TRANSB_SHA1_M0 (2 << 20)
> +#define HDCP_TRANSC_SHA1_M0 (3 << 20)
> +#define HDCP_TRANSD_SHA1_M0 (4 << 20)
> #define HDCP_DDIB_SHA1_M0 (1 << 20)
> #define HDCP_DDIA_SHA1_M0 (2 << 20)
> #define HDCP_DDIC_SHA1_M0 (3 << 20)
> @@ -9270,15 +9278,89 @@ enum skl_power_gate {
> _PORTE_HDCP_AUTHENC, \
> _PORTF_HDCP_AUTHENC) + (x))
> #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
> +#define _TRANSA_HDCP_CONF 0x66400
> +#define _TRANSB_HDCP_CONF 0x66500
> +#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
> + _TRANSB_HDCP_CONF)
> +#define HDCP_CONF(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_CONF(pipe) : \
> + PORT_HDCP_CONF(port))
Alignment
> +
> #define HDCP_CONF_CAPTURE_AN BIT(0)
> #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
> #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
> +#define _TRANSA_HDCP_ANINIT 0x66404
> +#define _TRANSB_HDCP_ANINIT 0x66504
> +#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_ANINIT, \
> + _TRANSB_HDCP_ANINIT)
> +#define HDCP_ANINIT(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANINIT(pipe) : \
> + PORT_HDCP_ANINIT(port))
Alignment
> +
> #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
> +#define _TRANSA_HDCP_ANLO 0x66408
> +#define _TRANSB_HDCP_ANLO 0x66508
> +#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
> + _TRANSB_HDCP_ANLO)
> +#define HDCP_ANLO(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANLO(pipe) : \
> + PORT_HDCP_ANLO(port))
> +
Alignment
> #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
> +#define _TRANSA_HDCP_ANHI 0x6640C
> +#define _TRANSB_HDCP_ANHI 0x6650C
> +#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
> + _TRANSB_HDCP_ANHI)
> +#define HDCP_ANHI(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANHI(pipe) : \
> + PORT_HDCP_ANHI(port))
> +
Alignment
> #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
> +#define _TRANSA_HDCP_BKSVLO 0x66410
> +#define _TRANSB_HDCP_BKSVLO 0x66510
> +#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_BKSVLO, \
> + _TRANSB_HDCP_BKSVLO)
> +#define HDCP_BKSVLO(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_BKSVLO(pipe) : \
> + PORT_HDCP_BKSVLO(port))
> +
Alignment
> #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
> +#define _TRANSA_HDCP_BKSVHI 0x66414
> +#define _TRANSB_HDCP_BKSVHI 0x66514
> +#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_BKSVHI, \
> + _TRANSB_HDCP_BKSVHI)
> +#define HDCP_BKSVHI(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_BKSVHI(pipe) : \
> + PORT_HDCP_BKSVHI(port))
> +
Alignment
> #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
> +#define _TRANSA_HDCP_RPRIME 0x66418
> +#define _TRANSB_HDCP_RPRIME 0x66518
> +#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_RPRIME, \
> + _TRANSB_HDCP_RPRIME)
> +#define HDCP_RPRIME(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_RPRIME(pipe) : \
> + PORT_HDCP_RPRIME(port))
> +
Alignment
> #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
> +#define _TRANSA_HDCP_STATUS 0x6641C
> +#define _TRANSB_HDCP_STATUS 0x6651C
> +#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_STATUS, \
> + _TRANSB_HDCP_STATUS)
> +#define HDCP_STATUS(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_STATUS(pipe) : \
> + PORT_HDCP_STATUS(port))
> +
Alignment
> #define HDCP_STATUS_STREAM_A_ENC BIT(31)
> #define HDCP_STATUS_STREAM_B_ENC BIT(30)
> #define HDCP_STATUS_STREAM_C_ENC BIT(29)
> @@ -9305,23 +9387,43 @@ enum skl_power_gate {
> _PORTD_HDCP2_BASE, \
> _PORTE_HDCP2_BASE, \
> _PORTF_HDCP2_BASE) + (x))
> -
> -#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
> +#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> +#define _TRANSA_HDCP2_AUTH 0x66498
> +#define _TRANSB_HDCP2_AUTH 0x66598
> +#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
> + _TRANSB_HDCP2_AUTH)
Alignment
> #define AUTH_LINK_AUTHENTICATED BIT(31)
> #define AUTH_LINK_TYPE BIT(30)
> #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
> #define AUTH_CLR_KEYS BIT(18)
> -
> -#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
> +#define HDCP2_AUTH(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_AUTH(pipe) : \
> + PORT_HDCP2_AUTH(port))
> +
> +#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
> +#define _TRANSA_HDCP2_CTL 0x664B0
> +#define _TRANSB_HDCP2_CTL 0x665B0
> +#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
> + _TRANSB_HDCP2_CTL)
> #define CTL_LINK_ENCRYPTION_REQ BIT(31)
> -
> -#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
> -#define STREAM_ENCRYPTION_STATUS_A BIT(31)
> -#define STREAM_ENCRYPTION_STATUS_B BIT(30)
> -#define STREAM_ENCRYPTION_STATUS_C BIT(29)
> +#define HDCP2_CTL(dev_priv, pipe, port) (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_CTL(pipe) : \
> + PORT_HDCP2_CTL(port))
> +
Alignment
> +#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
> +#define _TRANSA_HDCP2_STATUS 0x664B4
> +#define _TRANSB_HDCP2_STATUS 0x665B4
> +#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_STATUS, \
> + _TRANSB_HDCP2_STATUS)
> #define LINK_TYPE_STATUS BIT(22)
> #define LINK_AUTH_STATUS BIT(21)
> #define LINK_ENCRYPTION_STATUS BIT(20)
> +#define HDCP2_STATUS(dev_priv, pipe, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_STATUS(pipe) : \
> + PORT_HDCP2_STATUS(port))
>
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1d58f7ec5d84..53f13e6a5a73 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -359,6 +359,14 @@ struct intel_hdcp {
> wait_queue_head_t cp_irq_queue;
> atomic_t cp_irq_count;
> int cp_irq_count_cached;
> +
> + /*
> + * Gen 12 onwards, HDCP is part of transcoder(previously DDI).
> + * So chacheing the pipe associated to connector at hdcp_enable
> + * would help in subsequent functions to derive the right offsets
> + * for HDCP registers.
> + */
> + enum pipe pipe;
> };
>
> struct intel_connector {
- Shashank
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-07-09 6:58 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2019-07-02 5:54 [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-07-02 17:04 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-07-03 15:02 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-09 4:09 ` [PATCH] " Sharma, Shashank
2019-07-08 23:59 ` Ramalingam C
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