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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
Date: Tue,  9 Jul 2019 22:06:19 +0100	[thread overview]
Message-ID: <20190709210620.15805-4-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20190709210620.15805-1-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It is a more appropriate home for it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 -----------------------
 drivers/gpu/drm/i915/gt/intel_sseu.c      | 24 +++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_sseu.h      |  2 ++
 drivers/gpu/drm/i915/i915_drv.h           |  2 --
 4 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15d1934486..ee2db060e349 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -972,30 +972,6 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
-{
-	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
-	unsigned int slice = fls(sseu->slice_mask) - 1;
-	unsigned int subslice;
-	u32 mcr_s_ss_select;
-
-	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
-	subslice = fls(sseu->subslice_mask[slice]);
-	GEM_BUG_ON(!subslice);
-	subslice--;
-
-	if (IS_GEN(dev_priv, 10))
-		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
-				  GEN8_MCR_SUBSLICE(subslice);
-	else if (INTEL_GEN(dev_priv) >= 11)
-		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
-				  GEN11_MCR_SUBSLICE(subslice);
-	else
-		mcr_s_ss_select = 0;
-
-	return mcr_s_ss_select;
-}
-
 static u32
 read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
 		  i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0756f006f5f..c12cc476391f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -157,3 +157,27 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 
 	return rpcs;
 }
+
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915)
+{
+	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+	unsigned int slice = fls(sseu->slice_mask) - 1;
+	unsigned int subslice;
+	u32 mcr_s_ss_select;
+
+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+	subslice = fls(sseu->subslice_mask[slice]);
+	GEM_BUG_ON(!subslice);
+	subslice--;
+
+	if (IS_GEN(i915, 10))
+		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
+				  GEN8_MCR_SUBSLICE(subslice);
+	else if (INTEL_GEN(i915) >= 11)
+		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+				  GEN11_MCR_SUBSLICE(subslice);
+	else
+		mcr_s_ss_select = 0;
+
+	return mcr_s_ss_select;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..fbd86ed45612 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -72,4 +72,6 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 			 const struct intel_sseu *req_sseu);
 
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915);
+
 #endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..983a182d280e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2403,8 +2403,6 @@ extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
 
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
-
 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
 {
 	unsigned long delay;
-- 
2.20.1

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  parent reply	other threads:[~2019-07-09 21:06 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09 21:06 [PATCH 0/4] MCR fixes Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming Tvrtko Ursulin
2019-07-09 21:09   ` Chris Wilson
2019-07-10  6:21     ` Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads Tvrtko Ursulin
2019-07-09 21:11   ` Chris Wilson
2019-07-11  9:15     ` Tvrtko Ursulin
2019-07-11 15:59   ` [PATCH v2 " Tvrtko Ursulin
2019-07-11 23:51     ` Summers, Stuart
2019-07-12  5:32       ` Tvrtko Ursulin
2019-07-09 21:06 ` Tvrtko Ursulin [this message]
2019-07-09 21:12   ` [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c Chris Wilson
2019-07-09 21:06 ` [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 Tvrtko Ursulin
2019-07-09 21:12   ` Chris Wilson
2019-07-09 22:18 ` ✓ Fi.CI.BAT: success for MCR fixes Patchwork
2019-07-11  8:53 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-11 19:05 ` ✓ Fi.CI.BAT: success for MCR fixes (rev2) Patchwork
2019-07-12 22:17 ` ✗ Fi.CI.IGT: failure " Patchwork

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