From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming
Date: Wed, 10 Jul 2019 07:21:19 +0100 [thread overview]
Message-ID: <53e16003-66d0-ecea-1ecf-7964d2d59227@linux.intel.com> (raw)
In-Reply-To: <156270659276.11940.12155160842593062182@skylake-alporthouse-com>
On 09/07/2019 22:09, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-09 22:06:17)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> fls returns bit positions starting from one for the lsb and the MCR
>> register expects zero based (sub)slice addressing.
>>
>> Incorrent MCR programming can have the effect of directing MMIO reads of
>> registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
>> instead of actual content.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
>
> Makes sense to me, just from my meagre understanding of arrays
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index bdf279fa3b2e..ee15d1934486 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>> u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>> {
>> const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>> + unsigned int slice = fls(sseu->slice_mask) - 1;
>
> I'd vote for __fls() here instead of fls() - 1.
With fls() I get zero slice mask check for free, in the array out of
bounds check below.
>
>> + unsigned int subslice;
>> u32 mcr_s_ss_select;
>> - u32 slice = fls(sseu->slice_mask);
>> - u32 subslice = fls(sseu->subslice_mask[slice]);
>> +
>> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
>> + subslice = fls(sseu->subslice_mask[slice]);
>> + GEM_BUG_ON(!subslice);
>> + subslice--;
>
> And I think we're a bit late on the BUG_ON here (it's shouldn't change
> after probing) so could be happily reduced to __fls().
Why late? This one is not checking the array for out of bounds, just if
zero subslice mask happens to be in a valid slot. Too paranoid?
Regards,
Tvrtko
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next prev parent reply other threads:[~2019-07-10 6:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 21:06 [PATCH 0/4] MCR fixes Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming Tvrtko Ursulin
2019-07-09 21:09 ` Chris Wilson
2019-07-10 6:21 ` Tvrtko Ursulin [this message]
2019-07-09 21:06 ` [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads Tvrtko Ursulin
2019-07-09 21:11 ` Chris Wilson
2019-07-11 9:15 ` Tvrtko Ursulin
2019-07-11 15:59 ` [PATCH v2 " Tvrtko Ursulin
2019-07-11 23:51 ` Summers, Stuart
2019-07-12 5:32 ` Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c Tvrtko Ursulin
2019-07-09 21:12 ` Chris Wilson
2019-07-09 21:06 ` [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 Tvrtko Ursulin
2019-07-09 21:12 ` Chris Wilson
2019-07-09 22:18 ` ✓ Fi.CI.BAT: success for MCR fixes Patchwork
2019-07-11 8:53 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-11 19:05 ` ✓ Fi.CI.BAT: success for MCR fixes (rev2) Patchwork
2019-07-12 22:17 ` ✗ Fi.CI.IGT: failure " Patchwork
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