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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write
Date: Thu, 25 Jul 2019 16:56:43 -0700	[thread overview]
Message-ID: <20190725235643.6870-6-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190725235643.6870-1-lucas.demarchi@intel.com>

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add a new function to write to dkl phy pll registers. As per the
spec all the registers are read modify write.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 049b68e0c61c..5606a83326e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3349,7 +3349,70 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
 static void dkl_pll_write(struct drm_i915_private *dev_priv,
 			  struct intel_shared_dpll *pll)
 {
-	/* TODO */
+	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
+	u32 val;
+
+	/*
+	 * All registers programmed here have the same HIP_INDEX_REG even
+	 * though on different building block
+	 */
+	I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+	/* All the registers are RMW */
+	val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+	val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+	val |= hw_state->mg_refclkin_ctl;
+	I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
+
+	val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+	val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+	val |= hw_state->mg_clktop2_coreclkctl1;
+	I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+
+	val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+	val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+	       MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+	       MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+	       MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+	val |= hw_state->mg_clktop2_hsclkctl;
+	I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+
+	val = I915_READ(DKL_PLL_DIV0(tc_port));
+	val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
+		DKL_PLL_DIV0_PROP_COEFF_MASK |
+		DKL_PLL_DIV0_FBPREDIV_MASK |
+		DKL_PLL_DIV0_FBDIV_INT_MASK);
+	val |= hw_state->mg_pll_div0;
+	I915_WRITE(DKL_PLL_DIV0(tc_port), val);
+
+	val = I915_READ(DKL_PLL_DIV1(tc_port));
+	val = ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
+		DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+	val |= hw_state->mg_pll_div1;
+	I915_WRITE(DKL_PLL_DIV1(tc_port), val);
+
+	val = I915_READ(DKL_PLL_SSC(tc_port));
+	val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+		DKL_PLL_SSC_STEP_LEN_MASK |
+		DKL_PLL_SSC_STEP_NUM_MASK |
+		DKL_PLL_SSC_EN);
+	val |= hw_state->mg_pll_ssc;
+	I915_WRITE(DKL_PLL_SSC(tc_port), val);
+
+	val = I915_READ(DKL_PLL_BIAS(tc_port));
+	val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
+		DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+	val |= hw_state->mg_pll_bias;
+	I915_WRITE(DKL_PLL_BIAS(tc_port), val);
+
+	val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+	val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
+		DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
+	val |= hw_state->mg_pll_tdc_coldst_bias;
+	I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+
+	POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
 }
 
 static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
-- 
2.21.0

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  parent reply	other threads:[~2019-07-25 23:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
2019-07-25 23:56 ` [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
2019-07-25 23:56 ` [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
2019-07-25 23:56 ` [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
2019-07-25 23:56 ` [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
2019-07-25 23:56 ` Lucas De Marchi [this message]
2019-07-26  2:23 ` ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs Patchwork
2019-07-27  2:42 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-12 16:13 ` [PATCH 0/5] " Lucas De Marchi
2019-08-13 21:18 ` Lucas De Marchi

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