[PATCH v4 0/9] DC3CO Support for TGL

[PATCH v4 0/9] DC3CO Support for TGL

[Anshuman Gupta]

This revision is a rebased and has addressed few review comment
provided by Animesh and has some other fixes in dc3 disallow sequence.

one patch of this series "tgl-DC3CO-PSR2-helper"
will require rebase after https://patchwork.freedesktop.org/series/62416/
series will merged to drm-tip.
TGL supports DC3CO only on PipeA in LPSP mpde, so DC3CO doesn't depends
on TGL PSR "Transcoder B" feature.

B.Specs:49196
DC3CO requirements:
*Audio codec idle and disabled.
*External displays disabled.
 WD transcoders and DP/HDMI transcoders must be disabled.
*Backlight cannot be driven from the display utility pin.
 It can be driven from the south display.
*This feature should be enabled only in Display Video playback on eDP.
*DC5 and DC6 not allowed when this feature is enabled.
*PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b)
*Disable DC3co before mode set, or other Aux, PLL, and DBUF programming,
 and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.

Anshuman Gupta (9):
  drm/i915/tgl: Add DC3CO required register and bits
  drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
  drm/i915/tgl: Add power well to enable DC3CO state
  drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
  drm/i915/tgl: Add helper function to prefer dc3co over dc5
  drm/i915/tgl: Add VIDEO power domain
  drm/i915/tgl: DC3CO PSR2 helper
  drm/i915/tgl: switch between dc3co and dc5 based on display idleness
  drm/i915/tgl: Add DC3CO counter in i915_dmc_info

 drivers/gpu/drm/i915/display/intel_display.c  |   9 +
 .../drm/i915/display/intel_display_power.c    | 290 +++++++++++++++++-
 .../drm/i915/display/intel_display_power.h    |  11 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  44 +++
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c           |   6 +
 drivers/gpu/drm/i915/i915_drv.h               |   8 +
 drivers/gpu/drm/i915/i915_params.c            |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  10 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 11 files changed, 376 insertions(+), 11 deletions(-)

-- 
2.21.0

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[PATCH v4 1/9] drm/i915/tgl: Add DC3CO required register and bits

[Anshuman Gupta]

Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d760830cfd7b..efd351c882d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4198,6 +4198,7 @@ enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4244,11 +4245,16 @@ enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
@@ -10038,6 +10044,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.21.0

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[PATCH v4 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask

[Anshuman Gupta]

Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.

v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
    independently.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 29 ++++++++++++++-----
 drivers/gpu/drm/i915/i915_params.c            |  3 +-
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index dd2a50b8ba0a..e6729c107038 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -717,7 +717,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 	u32 mask;
 
 	mask = DC_STATE_EN_UPTO_DC5;
-	if (INTEL_GEN(dev_priv) >= 11)
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+					  | DC_STATE_EN_DC9;
+	else if (IS_GEN(dev_priv, 11))
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
 	else if (IS_GEN9_LP(dev_priv))
 		mask |= DC_STATE_EN_DC9;
@@ -3946,14 +3950,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int requested_dc;
 	int max_dc;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
-		max_dc = 2;
+	if (INTEL_GEN(dev_priv) >= 12) {
+		max_dc = 4;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
 		 * not depending on the DMC firmware. It's needed by system
 		 * suspend/resume, so allow it unconditionally.
 		 */
 		mask = DC_STATE_EN_DC9;
+	} else if (IS_GEN(dev_priv, 11)) {
+		max_dc = 2;
+		mask = DC_STATE_EN_DC9;
 	} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
 		max_dc = 2;
 		mask = 0;
@@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = enable_dc;
 	} else if (enable_dc == -1) {
 		requested_dc = max_dc;
-	} else if (enable_dc > max_dc && enable_dc <= 2) {
+	} else if (enable_dc > max_dc && enable_dc <= 4) {
 		DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
 			      enable_dc, max_dc);
 		requested_dc = max_dc;
@@ -3981,10 +3988,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = max_dc;
 	}
 
-	if (requested_dc > 1)
-		mask |= DC_STATE_EN_UPTO_DC6;
-	if (requested_dc > 0)
-		mask |= DC_STATE_EN_UPTO_DC5;
+	if (requested_dc == 4) {
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+	} else if (requested_dc == 3) {
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+	} else {
+		if (requested_dc > 1)
+			mask |= DC_STATE_EN_UPTO_DC6;
+		if (requested_dc > 0)
+			mask |= DC_STATE_EN_UPTO_DC5;
+	}
 
 	DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
 
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
 
 i915_param_named_unsafe(enable_dc, int, 0400,
 	"Enable power-saving display C-states. "
-	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+	"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
 i915_param_named_unsafe(enable_fbc, int, 0600,
 	"Enable frame buffer compression for power savings "
-- 
2.21.0

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[PATCH v4 3/9] drm/i915/tgl: Add power well to enable DC3CO state

[Anshuman Gupta]

"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.

v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
    Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
    Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
    to a appropriate place haswell_crtc_enable(). [Imre]
    Changed the DC3CO power well enabled call back logic as
    recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 67 ++++++++++++++++++-
 1 file changed, 66 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e6729c107038..c570fda290c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,6 +791,25 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(DC_STATE_EN);
+	val &= ~DC_STATE_DC3CO_STATUS;
+	I915_WRITE(DC_STATE_EN, val);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+	/*
+	 * Delay of 200us DC3CO Exit time B.Spec 49196
+	 */
+	udelay(200);
+}
+
 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
 	assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 		gen9_enable_dc5(dev_priv);
 }
 
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	if (!dev_priv->psr.sink_psr2_support)
+		return;
+
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	/*
+	 * Checking alone DC_STATE_EN is not enough as DC5 power well also
+	 * allow/disallow DC3CO to make sure both are not enabled at same time
+	 */
+	return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
@@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS (		\
+	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	TGL_PW_2_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
@@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
 	.is_enabled = gen9_dc_off_power_well_enabled,
 };
 
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+	.sync_hw = i9xx_power_well_sync_hw_noop,
+	.enable = tgl_dc3co_power_well_enable,
+	.disable = tgl_dc3co_power_well_disable,
+	.is_enabled = tgl_dc3co_power_well_enabled,
+};
+
 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 		},
 	},
 	{
-		.name = "DC off",
+		.name = "DC5 off",
 		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 	},
+	{
+		.name = "DC3CO off",
+		.domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+		.ops = &tgl_dc3co_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
 	{
 		.name = "power well 2",
 		.domains = TGL_PW_2_POWER_DOMAINS,
-- 
2.21.0

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[PATCH v4 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6

[Anshuman Gupta]

As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time, it makes DC3CO and DC5 mutual exclusive.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c570fda290c4..cd500fbdd8f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	/* DC3CO and DC5/6 are mutually exclusive */
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_allow_dc3co(dev_priv);
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 	if (!dev_priv->csr.dmc_payload)
 		return;
 
+	/* DC3CO and DC5/6 are mutually exclusive */
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_disallow_dc3co(dev_priv);
+
 	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 		skl_enable_dc6(dev_priv);
 	else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
-- 
2.21.0

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[PATCH v4 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5

[Anshuman Gupta]

We need to have a S/W flag based upon which driver can switch to DC3CO.
If it is only edp display connected and it has psr2 capability,
then set a prefer_dc3co flag to true, which will be used to
switch to dc3co as well as to program DC3CO PSR2 transcoder
early exitline event.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +
 .../drm/i915/display/intel_display_power.c    | 106 ++++++++++++++++++
 .../drm/i915/display/intel_display_power.h    |   5 +
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 6 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e4ee29fd0fc..a0cb635ca069 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	if (WARN_ON(intel_crtc->active))
 		return;
+	/* Enable PSR2 transcoder exit line */
+	if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+		tgl_enable_psr2_transcoder_exitline(pipe_config);
 
 	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
 
@@ -13686,6 +13689,8 @@ static int intel_atomic_check(struct drm_device *dev,
 				       "[modeset]" : "[fastset]");
 	}
 
+	tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
 	return 0;
 
  fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cd500fbdd8f3..cc6f216292ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@
 #include "intel_hotplug.h"
 #include "intel_sideband.h"
 #include "intel_tc.h"
+#include "intel_pm.h"
 
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 					 enum i915_power_well_id power_well_id);
@@ -791,6 +792,111 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate)
+{
+	u32 linetime_us, val, exit_scanlines;
+	u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+	if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+		return;
+
+	linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+	if (WARN_ON(!linetime_us))
+		return;
+	/*
+	 * DC3CO Exit time 200us B.Spec 49196
+	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+	 * Exit line event need to program above calculated scan lines before
+	 * next VBLANK.
+	 */
+	exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+	if (WARN_ON(exit_scanlines > crtc_vdisplay))
+		return;
+
+	exit_scanlines = crtc_vdisplay - exit_scanlines;
+	exit_scanlines <<= EXITLINE_SHIFT;
+	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+	val |= exit_scanlines;
+	val |= EXITLINE_ENABLE;
+	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state  *crtc_state)
+{
+	struct drm_atomic_state *state = crtc_state->base.state;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_connector *connector, *edp_connector = NULL;
+	struct drm_connector_state *connector_state;
+	int i;
+
+	for_each_new_connector_in_state(state, connector, connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		if (connector->status == connector_status_connected &&
+		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+			return false;
+		else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+			 connector->status == connector_status_connected)
+			edp_connector = connector;
+	}
+
+	if (edp_connector)
+		return true;
+
+	return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct intel_atomic_state *state)
+{
+	struct intel_crtc_state *crtc_state, *mode_changed_cstate;
+	struct intel_crtc *crtc;
+	int i;
+	u32 val;
+
+	dev_priv->csr.prefer_dc3co = false;
+
+	if (!IS_TIGERLAKE(dev_priv))
+		return;
+
+	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		if (crtc->pipe == PIPE_A)
+			mode_changed_cstate = crtc_state;
+		if (!crtc_state->has_psr2 && crtc_state->base.active) {
+			dev_priv->csr.prefer_dc3co = false;
+			return;
+		} else if (crtc_state->has_psr2) {
+			if (tgl_is_only_edp_connected(crtc_state) &&
+			    crtc_state->base.active) {
+				dev_priv->csr.prefer_dc3co = true;
+				continue;
+			} else {
+				dev_priv->csr.prefer_dc3co = false;
+				return;
+			}
+		}
+	}
+
+	if (dev_priv->csr.prefer_dc3co) {
+		val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
+		if (!(val & EXITLINE_ENABLE)) {
+			mode_changed_cstate->base.mode_changed = true;
+		}
+	}
+}
+
 static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index e4d2c1ba24b0..7a61cab1eb31 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -12,6 +12,8 @@
 
 struct drm_i915_private;
 struct intel_encoder;
+struct intel_crtc_state;
+struct intel_atomic_state;
 
 enum intel_display_power_domain {
 	POWER_DOMAIN_DISPLAY_CORE,
@@ -253,6 +255,9 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct intel_atomic_state *state);
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate);
 
 const char *
 intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8931dd847bb5..9f2aab9013fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -366,6 +366,7 @@ struct intel_csr {
 	u32 dc_state;
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
+	bool prefer_dc3co;
 };
 
 enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30399b245f07..78bf1070dc33 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4583,7 +4583,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
 	return ret;
 }
 
-static uint_fixed_16_16_t
+uint_fixed_16_16_t
 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 {
 	u32 pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index e3573e1e16e3..454e92c06dff 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+#include "i915_drv.h"
 #include "i915_reg.h"
 
 struct drm_device;
@@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
 
 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
 
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
-- 
2.21.0

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[PATCH v4 6/9] drm/i915/tgl: Add VIDEO power domain

[Anshuman Gupta]

The Power domain name VIDEO is inspired from the fact that
DC3CO should be enabled only during VIDEO playback.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
 drivers/gpu/drm/i915/i915_drv.h                    | 6 ++++++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cc6f216292ef..7aa3e0f54965 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
 		return "VGA";
 	case POWER_DOMAIN_AUDIO:
 		return "AUDIO";
+	case POWER_DOMAIN_VIDEO:
+		return "VIDEO";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2779,6 +2781,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 
 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_VIDEO) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 7a61cab1eb31..1dd221c4bee1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO,
+	POWER_DOMAIN_VIDEO,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f2aab9013fe..6a883fa92736 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -367,6 +367,12 @@ struct intel_csr {
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
+	intel_wakeref_t dc5_wakeref;
+	/*
+	 * Mutex to protect dc5_wakeref which make maintain proper
+	 * power domain reference count of POWER_DOMAIN_VIDEO
+	 */
+	struct mutex dc5_mutex;
 };
 
 enum i915_cache_level {
-- 
2.21.0

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[PATCH v4 7/9] drm/i915/tgl: DC3CO PSR2 helper

[Anshuman Gupta]

Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h |  2 ++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 69d908e6a050..85ff64111266 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames = 0;
+
+	idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames;
+
+	/*
+	 * Let's use 6 as the minimum to cover all known cases including the
+	 * off-by-one issue that HW has in some cases.
+	 */
+	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+	idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+	intel_wakeref_t wakeref __maybe_unused;
+
+	/* Before PSR2 exit disallow dc3co*/
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	wakeref	= fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+	if (wakeref)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+					dev_priv->csr.dc5_wakeref);
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 	}
 
 	if (dev_priv->psr.psr2_enabled) {
+		tgl_disallow_dc3co_on_psr2_exit(dev_priv);
 		val = I915_READ(EDP_PSR2_CTL);
 		WARN_ON(!(val & EDP_PSR2_ENABLE));
 		I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
 			    u32 *out_value);
 bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.21.0

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[PATCH v4 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness

[Anshuman Gupta]

DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.

It will be worthy to enable DC3CO after completion of each flip
and switch back to DC5 when display is idle, as driver doesn't
differentiate between video playback and a normal flip.
It is safer to allow DC5 after 6 idle frame, as PSR2 requires
minimum 6 idle frame.

v2: calculated s/w state to switch over dc3co when there is an
    update. [Imre]
    used cancel_delayed_work_sync() in order to avoid any race
    with already scheduled delayed work. [Imre]
v3: cancel_delayed_work_sync() may blocked the commit work.
    Hence dropping it, dc5_idle_thread() checks the valid wakeref before
    putting the reference count, which avoids any chances of dropping
    a zero wakeref. [Imre (IRC)]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  4 +
 .../drm/i915/display/intel_display_power.c    | 77 +++++++++++++++++++
 .../drm/i915/display/intel_display_power.h    |  5 ++
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 4 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0cb635ca069..0622f1fbafa5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14083,6 +14083,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
 		intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
 	}
+
+	tgl_switch_to_dc3co_after_flip(dev_priv);
 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
 
 	/*
@@ -16157,6 +16159,7 @@ int intel_modeset_init(struct drm_device *dev)
 	init_llist_head(&dev_priv->atomic_helper.free_list);
 	INIT_WORK(&dev_priv->atomic_helper.free_work,
 		  intel_atomic_helper_free_state_worker);
+	INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread);
 
 	intel_init_quirks(dev_priv);
 
@@ -17100,6 +17103,7 @@ void intel_modeset_driver_remove(struct drm_device *dev)
 	flush_workqueue(dev_priv->modeset_wq);
 
 	flush_work(&dev_priv->atomic_helper.free_work);
+	flush_delayed_work(&dev_priv->csr.idle_work);
 	WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7aa3e0f54965..4307e6ad4c74 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
 #include "intel_sideband.h"
 #include "intel_tc.h"
 #include "intel_pm.h"
+#include "intel_psr.h"
 
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 					 enum i915_power_well_id power_well_id);
@@ -825,6 +826,46 @@ void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate)
 	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
 }
 
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv)
+{
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *cstate;
+	u32 delay;
+
+	if (!dev_priv->csr.prefer_dc3co)
+		return;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
+		goto unlock;
+
+	/*
+	 * As every flip go through intel_atomic_commit, so tracking a
+	 * atomic commit will be a hint for idle frames.
+	 * Delayed work for 6 idle frames will be enough to allow dc6
+	 * over dc3co for deepest power savings.
+	 * At every atomic commit first cancel the delayed work ,
+	 * when delayed schedules that means display has been idle
+	 * for the 6 idle frame.
+	 */
+	cancel_delayed_work(&dev_priv->csr.idle_work);
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	if (!dev_priv->csr.dc5_wakeref) {
+		dev_priv->csr.dc5_wakeref =
+		intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO);
+		tgl_psr2_deep_sleep_disable(dev_priv);
+	}
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+	crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+	cstate = to_intel_crtc_state(crtc->base.state);
+
+	delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate);
+	schedule_delayed_work(&dev_priv->csr.idle_work,
+			      usecs_to_jiffies(delay));
+unlock:
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
 static bool tgl_is_only_edp_connected(struct intel_crtc_state  *crtc_state)
 {
 	struct drm_atomic_state *state = crtc_state->base.state;
@@ -899,6 +940,20 @@ void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
 	}
 }
 
+void intel_dc5_idle_thread(struct work_struct *work)
+{
+	intel_wakeref_t wakeref __maybe_unused;
+	struct drm_i915_private *dev_priv =
+		container_of(work, typeof(*dev_priv), csr.idle_work.work);
+
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	wakeref	= fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+	if (wakeref)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, wakeref);
+	tgl_psr2_deep_sleep_enable(dev_priv);
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
 static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
@@ -1169,6 +1224,27 @@ static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
 		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+	u32 pixel_rate, crtc_htotal, crtc_vtotal;
+	u32 frametime_us;
+
+	if (!cstate || !cstate->base.active)
+		return 0;
+
+	pixel_rate = cstate->pixel_rate;
+
+	if (WARN_ON(pixel_rate == 0))
+		return 0;
+
+	crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+	crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+	frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL,
+				    pixel_rate);
+
+	return frametime_us;
+}
+
 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
@@ -4243,6 +4319,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
 
 	mutex_init(&power_domains->lock);
+	mutex_init(&dev_priv->csr.dc5_mutex);
 
 	INIT_DELAYED_WORK(&power_domains->async_put_work,
 			  intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1dd221c4bee1..df2639078a30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -10,6 +10,8 @@
 #include "intel_runtime_pm.h"
 #include "i915_reg.h"
 
+#define DC5_REQ_IDLE_FRAMES	6
+
 struct drm_i915_private;
 struct intel_encoder;
 struct intel_crtc_state;
@@ -256,9 +258,12 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
+void intel_dc5_idle_thread(struct work_struct *work);
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate);
 void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
 				     struct intel_atomic_state *state);
 void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate);
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv);
 
 const char *
 intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6a883fa92736..54c3fe13bc8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -365,6 +365,7 @@ struct intel_csr {
 	u32 mmiodata[20];
 	u32 dc_state;
 	u32 allowed_dc_mask;
+	struct delayed_work idle_work;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
 	intel_wakeref_t dc5_wakeref;
-- 
2.21.0

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[PATCH v4 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info

[Anshuman Gupta]

Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8953336f2ae5..2e4b7d0ec3aa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2417,6 +2417,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	/*
+	 * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+	 */
+	if (IS_TIGERLAKE(dev_priv))
+		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
 	if (INTEL_GEN(dev_priv) >= 12) {
 		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
 		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efd351c882d3..fa3e5f5340ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7280,6 +7280,8 @@ enum {
 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
 
+#define DMC_DEBUG3		_MMIO(0x101090)
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.21.0

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✗ Fi.CI.BAT: failure for DC3CO Support for TGL

[Patchwork]

== Series Details ==

Series: DC3CO Support for TGL
URL   : https://patchwork.freedesktop.org/series/64923/
State : failure

== Summary ==

Applying: drm/i915/tgl: Add DC3CO required register and bits
Applying: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Applying: drm/i915/tgl: Add power well to enable DC3CO state
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display_power.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915/tgl: Add power well to enable DC3CO state
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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