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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Date: Sat, 10 Aug 2019 00:02:16 +0530	[thread overview]
Message-ID: <20190809183223.12031-3-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com>

Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.

v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
    independently.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 29 ++++++++++++++-----
 drivers/gpu/drm/i915/i915_params.c            |  3 +-
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3bea2b74ce2..e2ef202aeeef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -717,7 +717,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 	u32 mask;
 
 	mask = DC_STATE_EN_UPTO_DC5;
-	if (INTEL_GEN(dev_priv) >= 11)
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+					  | DC_STATE_EN_DC9;
+	else if (IS_GEN(dev_priv, 11))
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
 	else if (IS_GEN9_LP(dev_priv))
 		mask |= DC_STATE_EN_DC9;
@@ -3946,14 +3950,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int requested_dc;
 	int max_dc;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
-		max_dc = 2;
+	if (INTEL_GEN(dev_priv) >= 12) {
+		max_dc = 4;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
 		 * not depending on the DMC firmware. It's needed by system
 		 * suspend/resume, so allow it unconditionally.
 		 */
 		mask = DC_STATE_EN_DC9;
+	} else if (IS_GEN(dev_priv, 11)) {
+		max_dc = 2;
+		mask = DC_STATE_EN_DC9;
 	} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
 		max_dc = 2;
 		mask = 0;
@@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = enable_dc;
 	} else if (enable_dc == -1) {
 		requested_dc = max_dc;
-	} else if (enable_dc > max_dc && enable_dc <= 2) {
+	} else if (enable_dc > max_dc && enable_dc <= 4) {
 		DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
 			      enable_dc, max_dc);
 		requested_dc = max_dc;
@@ -3981,10 +3988,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = max_dc;
 	}
 
-	if (requested_dc > 1)
-		mask |= DC_STATE_EN_UPTO_DC6;
-	if (requested_dc > 0)
-		mask |= DC_STATE_EN_UPTO_DC5;
+	if (requested_dc == 4) {
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+	} else if (requested_dc == 3) {
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+	} else {
+		if (requested_dc > 1)
+			mask |= DC_STATE_EN_UPTO_DC6;
+		if (requested_dc > 0)
+			mask |= DC_STATE_EN_UPTO_DC5;
+	}
 
 	DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
 
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
 
 i915_param_named_unsafe(enable_dc, int, 0400,
 	"Enable power-saving display C-states. "
-	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+	"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
 i915_param_named_unsafe(enable_fbc, int, 0600,
 	"Enable frame buffer compression for power savings "
-- 
2.21.0

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  parent reply	other threads:[~2019-08-09 18:36 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-08-09 18:32 ` Anshuman Gupta [this message]
2019-08-09 18:32 ` [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
2019-08-11  7:46   ` Anshuman Gupta
2019-08-13 14:46   ` Imre Deak
2019-08-27 13:01     ` Gupta, Anshuman
2019-08-27 13:20       ` Imre Deak
2019-08-27 16:17         ` Gupta, Anshuman
2019-08-09 18:32 ` [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-08-13 14:52   ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
2019-08-13 15:47   ` Imre Deak
2019-08-19 12:57     ` Gupta, Anshuman
2019-08-19 13:23       ` Imre Deak
2019-08-14  9:46   ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-08-13 16:05   ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-08-10  6:17   ` kbuild test robot
2019-08-10  6:32   ` kbuild test robot
2019-08-09 18:32 ` [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-08-09 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev2) Patchwork
2019-08-09 19:17 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-09 19:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-10 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-08-11  8:12 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev3) Patchwork
2019-08-11  8:16 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-11  8:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-11 15:08 ` ✓ Fi.CI.IGT: " Patchwork

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