From: Patchwork <patchwork@emeril.freedesktop.org>
To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for Some more display uncore prep work
Date: Fri, 16 Aug 2019 01:46:27 -0000 [thread overview]
Message-ID: <20190816014627.31006.82783@emeril.freedesktop.org> (raw)
In-Reply-To: <20190816012343.36433-1-daniele.ceraolospurio@intel.com>
== Series Details ==
Series: Some more display uncore prep work
URL : https://patchwork.freedesktop.org/series/65281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
683fe77978b3 drm/i915: Move i915_power_well_id out of i915_reg.h
54c3dc873f33 drm/i915: Move engine IDs out of i915_reg.h
2fd5c6189863 drm/i915: Move gmbus definitions out of i915_reg.h
d24c490ba03f drm/i915: Dynamically allocate s0ix struct for VLV
-:98: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kmalloc(sizeof(*i915->s0ix_state)...) over kmalloc(sizeof(struct vlv_s0ix_state)...)
#98: FILE: drivers/gpu/drm/i915/i915_drv.c:537:
+ i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
total: 0 errors, 0 warnings, 1 checks, 256 lines checked
6eac8d3be838 drm/i915: Introduce i915_reg_types.h
-:1369: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#1369:
new file mode 100644
-:1374: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/i915_reg_types.h', please use '/*' instead
#1374: FILE: drivers/gpu/drm/i915/i915_reg_types.h:1:
+// SPDX-License-Identifier: MIT
-:1374: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1374: FILE: drivers/gpu/drm/i915/i915_reg_types.h:1:
+// SPDX-License-Identifier: MIT
-:1481: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#1481: FILE: drivers/gpu/drm/i915/i915_reg_types.h:108:
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
-:1495: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#1495: FILE: drivers/gpu/drm/i915/i915_reg_types.h:122:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:1495: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#1495: FILE: drivers/gpu/drm/i915/i915_reg_types.h:122:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:1504: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__x' - possible side-effects?
#1504: FILE: drivers/gpu/drm/i915/i915_reg_types.h:131:
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-:1516: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#1516: FILE: drivers/gpu/drm/i915/i915_reg_types.h:143:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1516: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#1516: FILE: drivers/gpu/drm/i915/i915_reg_types.h:143:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1521: WARNING:LONG_LINE: line over 100 characters
#1521: FILE: drivers/gpu/drm/i915/i915_reg_types.h:148:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1541: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__a' - possible side-effects?
#1541: FILE: drivers/gpu/drm/i915/i915_reg_types.h:168:
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
-:1551: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#1551: FILE: drivers/gpu/drm/i915/i915_reg_types.h:178:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
-:1551: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible side-effects?
#1551: FILE: drivers/gpu/drm/i915/i915_reg_types.h:178:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
-:1563: WARNING:NEW_TYPEDEFS: do not add new typedefs
#1563: FILE: drivers/gpu/drm/i915/i915_reg_types.h:190:
+typedef struct {
total: 0 errors, 5 warnings, 9 checks, 1145 lines checked
a2070d35d167 drm/i915: Wrappers for display register waits
-:900: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask_' - possible side-effects?
#900: FILE: drivers/gpu/drm/i915/i915_drv.h:2454:
+#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) \
+ intel_de_wait_for_register(dev_priv_, reg_, mask_, mask_, timeout_)
total: 0 errors, 0 warnings, 1 checks, 753 lines checked
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next prev parent reply other threads:[~2019-08-16 1:46 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
2019-08-16 4:52 ` Lucas De Marchi
2019-08-16 15:27 ` Daniele Ceraolo Spurio
2019-08-16 15:28 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 2/6] drm/i915: Move engine IDs " Daniele Ceraolo Spurio
2019-08-16 4:56 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 3/6] drm/i915: Move gmbus definitions " Daniele Ceraolo Spurio
2019-08-16 5:03 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
2019-08-16 5:09 ` Lucas De Marchi
2019-08-16 15:30 ` Daniele Ceraolo Spurio
2019-08-16 9:35 ` Jani Nikula
2019-08-16 9:40 ` Chris Wilson
2019-08-16 10:32 ` Jani Nikula
2019-08-16 15:33 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 5/6] drm/i915: Introduce i915_reg_types.h Daniele Ceraolo Spurio
2019-08-16 9:40 ` Michal Wajdeczko
2019-08-16 15:35 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 6/6] drm/i915: Wrappers for display register waits Daniele Ceraolo Spurio
2019-08-16 7:17 ` Chris Wilson
2019-08-16 1:46 ` Patchwork [this message]
2019-08-16 2:19 ` ✓ Fi.CI.BAT: success for Some more display uncore prep work Patchwork
2019-08-16 17:30 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-16 21:22 ` [PATCH 0/6] " Chris Wilson
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