public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Patchwork <patchwork@emeril.freedesktop.org>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3
Date: Fri, 16 Aug 2019 09:51:55 -0000	[thread overview]
Message-ID: <20190816095155.13759.66420@emeril.freedesktop.org> (raw)
In-Reply-To: <20190816080503.28594-1-lucas.demarchi@intel.com>

== Series Details ==

Series: Tiger Lake batch 3
URL   : https://patchwork.freedesktop.org/series/65290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: do not use DDIC
Okay!

Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!

Commit: drm/i915: Add transcoder restriction to PSR2
Okay!

Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

Commit: drm/i915/tgl: Change PSR2 transcoder restriction
Okay!

Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!

Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!

Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!

Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!

Commit: drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
Okay!

Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!

Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!

Commit: drm/i915: Disable pipes in reverse order
Okay!

Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!

Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!

Commit: drm/i915/tgl: Implement Wa_1406941453
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!

Commit: drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
Okay!

Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!

Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!

Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!

Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!

Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!

Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!

Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!

Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Updated Private PAT programming
Okay!

Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!

Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216

Commit: drm/i915/tgl: Add perf support on TGL
Okay!

Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-08-16  9:51 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 01/39] drm/i915/tgl: do not use DDIC Lucas De Marchi
2019-08-16  8:04 ` [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-16  8:04 ` [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-16  8:04 ` [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-16  8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-22 16:20   ` Gupta, Anshuman
2019-08-22 16:42     ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-16  8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
2019-08-16 21:28   ` Lucas De Marchi
2019-08-16 21:59     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-22  9:54   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-16  8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-22 16:46   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
2019-08-16  8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-22 12:55   ` Maarten Lankhorst
2019-08-16  8:04 ` [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-16  8:04 ` [PATCH 16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-16  8:04 ` [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-16  8:04 ` [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-16  8:04 ` [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-16  8:04 ` [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-16  8:04 ` [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi
2019-08-16  8:04 ` [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-16  8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-19 14:21   ` Maarten Lankhorst
2019-08-19 21:26     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-16  8:04 ` [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-16  8:04 ` [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-16  8:04 ` [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-16  8:04 ` [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-16  8:04 ` [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-16  8:04 ` [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-16  8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-19 18:31   ` Umesh Nerlige Ramappa
2019-08-21  8:37   ` Lionel Landwerlin
2019-08-22 10:43   ` Joonas Lahtinen
2019-08-22 12:13     ` Lionel Landwerlin
2019-08-23  8:30       ` Lucas De Marchi
2019-08-16  8:04 ` [PATCH 34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-16  8:04 ` [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-16  8:05 ` [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 39/39] drm/i915/tgl: " Lucas De Marchi
2019-08-16  9:37 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 Patchwork
2019-08-16  9:51 ` Patchwork [this message]
2019-08-16  9:57 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-16 21:26 ` ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190816095155.13759.66420@emeril.freedesktop.org \
    --to=patchwork@emeril.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox