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From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port
Date: Thu, 22 Aug 2019 22:12:59 +0530	[thread overview]
Message-ID: <ad72a444-58c1-7301-e81f-eacd3238f94f@intel.com> (raw)
In-Reply-To: <6939d64c-eae0-fd7b-e3d3-88b5809b5621@intel.com>



On 8/22/2019 9:50 PM, Gupta, Anshuman wrote:
> Verified from B.Specs:7723 and B.Spec:8041
> 
> On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>>  From BDW+ the PSR registers moved from DDIA to transcoder, so any port
>> with a eDP panel connected can have PSR, so lets remove this limitation.
>>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
>>   1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 36bdc16fb43b..6eedd8281e72 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp 
>> *intel_dp,
>>       /*
>>        * HSW spec explicitly says PSR is tied to port A.
>> -     * BDW+ platforms have a instance of PSR registers per transcoder 
>> but
>> -     * for now it only supports one instance of PSR, so lets keep it
>> -     * hardcoded to PORT_A
>> +         * BDW+ platforms with DDI implementation of PSR have different
>> +     * PSR registers per transcoder.
>>        */
>> -    if (dig_port->base.port != PORT_A) {
>> +    if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
>>           DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>>           return;
>>       }
>>
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  reply	other threads:[~2019-08-23  8:04 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 01/39] drm/i915/tgl: do not use DDIC Lucas De Marchi
2019-08-16  8:04 ` [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-16  8:04 ` [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-16  8:04 ` [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-16  8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-22 16:20   ` Gupta, Anshuman
2019-08-22 16:42     ` Gupta, Anshuman [this message]
2019-08-16  8:04 ` [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-16  8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
2019-08-16 21:28   ` Lucas De Marchi
2019-08-16 21:59     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-22  9:54   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-16  8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-22 16:46   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
2019-08-16  8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-22 12:55   ` Maarten Lankhorst
2019-08-16  8:04 ` [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-16  8:04 ` [PATCH 16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-16  8:04 ` [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-16  8:04 ` [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-16  8:04 ` [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-16  8:04 ` [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-16  8:04 ` [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi
2019-08-16  8:04 ` [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-16  8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-19 14:21   ` Maarten Lankhorst
2019-08-19 21:26     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-16  8:04 ` [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-16  8:04 ` [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-16  8:04 ` [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-16  8:04 ` [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-16  8:04 ` [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-16  8:04 ` [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-16  8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-19 18:31   ` Umesh Nerlige Ramappa
2019-08-21  8:37   ` Lionel Landwerlin
2019-08-22 10:43   ` Joonas Lahtinen
2019-08-22 12:13     ` Lionel Landwerlin
2019-08-23  8:30       ` Lucas De Marchi
2019-08-16  8:04 ` [PATCH 34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-16  8:04 ` [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-16  8:05 ` [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 39/39] drm/i915/tgl: " Lucas De Marchi
2019-08-16  9:37 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 Patchwork
2019-08-16  9:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-16  9:57 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-16 21:26 ` ✓ Fi.CI.IGT: " Patchwork

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