* [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers
@ 2019-10-01 19:37 José Roberto de Souza
2019-10-01 21:36 ` Lucas De Marchi
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: José Roberto de Souza @ 2019-10-01 19:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
All the MG registers is based on the tc_port not port, so
MG_PHY_PORT_LN() was subtracting port and PORT_C what is very
fragile.
So replacing port to tc_port in all MG register macros and users
like we have for DKL.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++++--------
drivers/gpu/drm/i915/i915_reg.h | 100 +++++++++++------------
2 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b463e51f8b45..3c1e885e0187 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2681,7 +2681,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
u32 level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
u32 n_entries, val;
int ln;
@@ -2697,33 +2697,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
- val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
}
/* Program MG_TX_SWINGCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
}
/* Program MG_TX_DRVCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2731,9 +2731,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2741,7 +2741,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
}
@@ -2752,17 +2752,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
* values from table for which TX1 and TX2 enabled.
*/
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_CLKHUB(ln, port));
+ val = I915_READ(MG_CLKHUB(ln, tc_port));
if (link_clock < 300000)
val |= CFG_LOW_RATE_LKREN_EN;
else
val &= ~CFG_LOW_RATE_LKREN_EN;
- I915_WRITE(MG_CLKHUB(ln, port), val);
+ I915_WRITE(MG_CLKHUB(ln, tc_port), val);
}
/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_DCC(ln, port));
+ val = I915_READ(MG_TX1_DCC(ln, tc_port));
val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
if (link_clock <= 500000) {
val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
@@ -2770,9 +2770,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
}
- I915_WRITE(MG_TX1_DCC(ln, port), val);
+ I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
- val = I915_READ(MG_TX2_DCC(ln, port));
+ val = I915_READ(MG_TX2_DCC(ln, tc_port));
val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
if (link_clock <= 500000) {
val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
@@ -2780,18 +2780,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
}
- I915_WRITE(MG_TX2_DCC(ln, port), val);
+ I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
}
/* Program MG_TX_PISO_READLOAD with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
+ val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
val |= CRI_CALCINIT;
- I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
+ I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
- val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
+ val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
val |= CRI_CALCINIT;
- I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
+ I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
}
}
@@ -3150,8 +3150,7 @@ static void
icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
{
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum port port = dig_port->base.port;
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
u32 val, bits;
int ln;
@@ -3167,7 +3166,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
val = I915_READ(DKL_DP_MODE(tc_port));
} else {
- val = I915_READ(MG_DP_MODE(ln, port));
+ val = I915_READ(MG_DP_MODE(ln, tc_port));
}
if (enable)
@@ -3178,7 +3177,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
if (INTEL_GEN(dev_priv) >= 12)
I915_WRITE(DKL_DP_MODE(tc_port), val);
else
- I915_WRITE(MG_DP_MODE(ln, port), val);
+ I915_WRITE(MG_DP_MODE(ln, tc_port), val);
}
if (INTEL_GEN(dev_priv) == 11) {
@@ -3203,8 +3202,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
- enum port port = intel_dig_port->base.port;
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
u32 ln0, ln1, pin_assignment;
u8 width;
@@ -3217,8 +3215,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
ln1 = I915_READ(DKL_DP_MODE(tc_port));
} else {
- ln0 = I915_READ(MG_DP_MODE(0, port));
- ln1 = I915_READ(MG_DP_MODE(1, port));
+ ln0 = I915_READ(MG_DP_MODE(0, tc_port));
+ ln1 = I915_READ(MG_DP_MODE(1, tc_port));
}
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
@@ -3280,8 +3278,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
I915_WRITE(DKL_DP_MODE(tc_port), ln1);
} else {
- I915_WRITE(MG_DP_MODE(0, port), ln0);
- I915_WRITE(MG_DP_MODE(1, port), ln1);
+ I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
+ I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..eefd789b9a28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1956,8 +1956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
-#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
- _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
@@ -1967,10 +1967,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define MG_TX1_LINK_PARAMS(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
@@ -1980,10 +1980,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define MG_TX2_LINK_PARAMS(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
#define CRI_USE_FS32 (1 << 5)
#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
@@ -1994,10 +1994,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define MG_TX1_PISO_READLOAD(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
@@ -2007,10 +2007,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define MG_TX2_PISO_READLOAD(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
#define CRI_CALCINIT (1 << 1)
#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
@@ -2021,10 +2021,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define MG_TX1_SWINGCTRL(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- MG_TX_SWINGCTRL_TX1LN1_PORT1)
+#define MG_TX1_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
@@ -2034,10 +2034,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define MG_TX2_SWINGCTRL(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define MG_TX2_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
@@ -2049,10 +2049,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
-#define MG_TX1_DRVCTRL(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
- MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
- MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+#define MG_TX1_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
@@ -2062,10 +2062,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define MG_TX2_DRVCTRL(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
- MG_TX_DRVCTRL_TX2LN0_PORT2, \
- MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define MG_TX2_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
@@ -2082,10 +2082,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_CLKHUB_LN1_PORT3 0x16A79C
#define MG_CLKHUB_LN0_PORT4 0x16B39C
#define MG_CLKHUB_LN1_PORT4 0x16B79C
-#define MG_CLKHUB(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
- MG_CLKHUB_LN0_PORT2, \
- MG_CLKHUB_LN1_PORT1)
+#define MG_CLKHUB(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
#define CFG_LOW_RATE_LKREN_EN (1 << 11)
#define MG_TX_DCC_TX1LN0_PORT1 0x168110
@@ -2096,10 +2096,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
-#define MG_TX1_DCC(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
- MG_TX_DCC_TX1LN0_PORT2, \
- MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX1_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LN0_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
#define MG_TX_DCC_TX2LN0_PORT1 0x168090
#define MG_TX_DCC_TX2LN1_PORT1 0x168490
#define MG_TX_DCC_TX2LN0_PORT2 0x169090
@@ -2108,10 +2108,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
-#define MG_TX2_DCC(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
- MG_TX_DCC_TX2LN0_PORT2, \
- MG_TX_DCC_TX2LN1_PORT1)
+#define MG_TX2_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LN0_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
@@ -2124,10 +2124,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
-#define MG_DP_MODE(ln, port) \
- MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
- MG_DP_MODE_LN0_ACU_PORT2, \
- MG_DP_MODE_LN1_ACU_PORT1)
+#define MG_DP_MODE(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
+ MG_DP_MODE_LN0_ACU_PORT2, \
+ MG_DP_MODE_LN1_ACU_PORT1)
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
--
2.23.0
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* Re: [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers
2019-10-01 19:37 [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers José Roberto de Souza
@ 2019-10-01 21:36 ` Lucas De Marchi
2019-10-01 22:49 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Lucas De Marchi @ 2019-10-01 21:36 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Oct 01, 2019 at 12:37:29PM -0700, Jose Souza wrote:
>All the MG registers is based on the tc_port not port, so
>MG_PHY_PORT_LN() was subtracting port and PORT_C what is very
>fragile.
>So replacing port to tc_port in all MG register macros and users
>like we have for DKL.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 100 +++++++++++------------
> 2 files changed, 81 insertions(+), 83 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index b463e51f8b45..3c1e885e0187 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -2681,7 +2681,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> u32 level)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- enum port port = encoder->port;
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
> u32 n_entries, val;
> int ln;
>@@ -2697,33 +2697,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>
> /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
>+ val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
> val &= ~CRI_USE_FS32;
>- I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
>+ I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
>
>- val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
>+ val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
> val &= ~CRI_USE_FS32;
>- I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
>+ I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
> }
>
> /* Program MG_TX_SWINGCTRL with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
>+ val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
> val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> ddi_translations[level].cri_txdeemph_override_17_12);
>- I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
>+ I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
>
>- val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
>+ val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
> val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> ddi_translations[level].cri_txdeemph_override_17_12);
>- I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
>+ I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
> }
>
> /* Program MG_TX_DRVCTRL with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_TX1_DRVCTRL(ln, port));
>+ val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
> val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> val |= CRI_TXDEEMPH_OVERRIDE_5_0(
>@@ -2731,9 +2731,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> CRI_TXDEEMPH_OVERRIDE_11_6(
> ddi_translations[level].cri_txdeemph_override_11_6) |
> CRI_TXDEEMPH_OVERRIDE_EN;
>- I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
>+ I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
>
>- val = I915_READ(MG_TX2_DRVCTRL(ln, port));
>+ val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
> val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> val |= CRI_TXDEEMPH_OVERRIDE_5_0(
>@@ -2741,7 +2741,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> CRI_TXDEEMPH_OVERRIDE_11_6(
> ddi_translations[level].cri_txdeemph_override_11_6) |
> CRI_TXDEEMPH_OVERRIDE_EN;
>- I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
>+ I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
>
> /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
> }
>@@ -2752,17 +2752,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> * values from table for which TX1 and TX2 enabled.
> */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_CLKHUB(ln, port));
>+ val = I915_READ(MG_CLKHUB(ln, tc_port));
> if (link_clock < 300000)
> val |= CFG_LOW_RATE_LKREN_EN;
> else
> val &= ~CFG_LOW_RATE_LKREN_EN;
>- I915_WRITE(MG_CLKHUB(ln, port), val);
>+ I915_WRITE(MG_CLKHUB(ln, tc_port), val);
> }
>
> /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_TX1_DCC(ln, port));
>+ val = I915_READ(MG_TX1_DCC(ln, tc_port));
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> if (link_clock <= 500000) {
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
>@@ -2770,9 +2770,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> }
>- I915_WRITE(MG_TX1_DCC(ln, port), val);
>+ I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
>
>- val = I915_READ(MG_TX2_DCC(ln, port));
>+ val = I915_READ(MG_TX2_DCC(ln, tc_port));
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> if (link_clock <= 500000) {
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
>@@ -2780,18 +2780,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> }
>- I915_WRITE(MG_TX2_DCC(ln, port), val);
>+ I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
> }
>
> /* Program MG_TX_PISO_READLOAD with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
>- val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
>+ val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
> val |= CRI_CALCINIT;
>- I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
>+ I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
>
>- val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
>+ val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
> val |= CRI_CALCINIT;
>- I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
>+ I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
> }
> }
>
>@@ -3150,8 +3150,7 @@ static void
> icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
> {
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>- enum port port = dig_port->base.port;
>- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> u32 val, bits;
> int ln;
>
>@@ -3167,7 +3166,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
> I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
> val = I915_READ(DKL_DP_MODE(tc_port));
> } else {
>- val = I915_READ(MG_DP_MODE(ln, port));
>+ val = I915_READ(MG_DP_MODE(ln, tc_port));
> }
>
> if (enable)
>@@ -3178,7 +3177,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
> if (INTEL_GEN(dev_priv) >= 12)
> I915_WRITE(DKL_DP_MODE(tc_port), val);
> else
>- I915_WRITE(MG_DP_MODE(ln, port), val);
>+ I915_WRITE(MG_DP_MODE(ln, tc_port), val);
> }
>
> if (INTEL_GEN(dev_priv) == 11) {
>@@ -3203,8 +3202,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
>- enum port port = intel_dig_port->base.port;
>- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
> u32 ln0, ln1, pin_assignment;
> u8 width;
>
>@@ -3217,8 +3215,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
> I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
> ln1 = I915_READ(DKL_DP_MODE(tc_port));
> } else {
>- ln0 = I915_READ(MG_DP_MODE(0, port));
>- ln1 = I915_READ(MG_DP_MODE(1, port));
>+ ln0 = I915_READ(MG_DP_MODE(0, tc_port));
>+ ln1 = I915_READ(MG_DP_MODE(1, tc_port));
> }
>
> ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
>@@ -3280,8 +3278,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
> I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
> I915_WRITE(DKL_DP_MODE(tc_port), ln1);
> } else {
>- I915_WRITE(MG_DP_MODE(0, port), ln0);
>- I915_WRITE(MG_DP_MODE(1, port), ln1);
>+ I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
>+ I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
> }
> }
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 058aa5ca8b73..eefd789b9a28 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -1956,8 +1956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
>
>-#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
>- _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
>+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
> #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
>@@ -1967,10 +1967,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>-#define MG_TX1_LINK_PARAMS(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>- MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>- MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>
> #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
>@@ -1980,10 +1980,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
>-#define MG_TX2_LINK_PARAMS(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>- MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>- MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> #define CRI_USE_FS32 (1 << 5)
>
> #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
>@@ -1994,10 +1994,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
>-#define MG_TX1_PISO_READLOAD(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>- MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>- MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>
> #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
>@@ -2007,10 +2007,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
>-#define MG_TX2_PISO_READLOAD(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>- MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>- MG_TX_PISO_READLOAD_TX2LN1_PORT1)
>+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> #define CRI_CALCINIT (1 << 1)
>
> #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
>@@ -2021,10 +2021,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
>-#define MG_TX1_SWINGCTRL(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>- MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>- MG_TX_SWINGCTRL_TX1LN1_PORT1)
>+#define MG_TX1_SWINGCTRL(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
>
> #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
>@@ -2034,10 +2034,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
>-#define MG_TX2_SWINGCTRL(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>- MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>- MG_TX_SWINGCTRL_TX2LN1_PORT1)
>+#define MG_TX2_SWINGCTRL(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
>
>@@ -2049,10 +2049,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
>-#define MG_TX1_DRVCTRL(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
>- MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
>- MG_TX_DRVCTRL_TX1LN1_TXPORT1)
>+#define MG_TX1_DRVCTRL(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
>+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
>+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
>
> #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
>@@ -2062,10 +2062,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
>-#define MG_TX2_DRVCTRL(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
>- MG_TX_DRVCTRL_TX2LN0_PORT2, \
>- MG_TX_DRVCTRL_TX2LN1_PORT1)
>+#define MG_TX2_DRVCTRL(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
>+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
>+ MG_TX_DRVCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
> #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
> #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
>@@ -2082,10 +2082,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_CLKHUB_LN1_PORT3 0x16A79C
> #define MG_CLKHUB_LN0_PORT4 0x16B39C
> #define MG_CLKHUB_LN1_PORT4 0x16B79C
>-#define MG_CLKHUB(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
>- MG_CLKHUB_LN0_PORT2, \
>- MG_CLKHUB_LN1_PORT1)
>+#define MG_CLKHUB(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
>+ MG_CLKHUB_LN0_PORT2, \
>+ MG_CLKHUB_LN1_PORT1)
> #define CFG_LOW_RATE_LKREN_EN (1 << 11)
>
> #define MG_TX_DCC_TX1LN0_PORT1 0x168110
>@@ -2096,10 +2096,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
>-#define MG_TX1_DCC(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
>- MG_TX_DCC_TX1LN0_PORT2, \
>- MG_TX_DCC_TX1LN1_PORT1)
>+#define MG_TX1_DCC(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
>+ MG_TX_DCC_TX1LN0_PORT2, \
>+ MG_TX_DCC_TX1LN1_PORT1)
> #define MG_TX_DCC_TX2LN0_PORT1 0x168090
> #define MG_TX_DCC_TX2LN1_PORT1 0x168490
> #define MG_TX_DCC_TX2LN0_PORT2 0x169090
>@@ -2108,10 +2108,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
>-#define MG_TX2_DCC(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
>- MG_TX_DCC_TX2LN0_PORT2, \
>- MG_TX_DCC_TX2LN1_PORT1)
>+#define MG_TX2_DCC(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
>+ MG_TX_DCC_TX2LN0_PORT2, \
>+ MG_TX_DCC_TX2LN1_PORT1)
> #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
> #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
>@@ -2124,10 +2124,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
>-#define MG_DP_MODE(ln, port) \
>- MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
>- MG_DP_MODE_LN0_ACU_PORT2, \
>- MG_DP_MODE_LN1_ACU_PORT1)
>+#define MG_DP_MODE(ln, tc_port) \
>+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
>+ MG_DP_MODE_LN0_ACU_PORT2, \
>+ MG_DP_MODE_LN1_ACU_PORT1)
> #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
> #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
>--
>2.23.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mg: Use tc_port instead of port parameter to MG registers
2019-10-01 19:37 [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers José Roberto de Souza
2019-10-01 21:36 ` Lucas De Marchi
@ 2019-10-01 22:49 ` Patchwork
2019-10-01 23:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-02 10:23 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-01 22:49 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mg: Use tc_port instead of port parameter to MG registers
URL : https://patchwork.freedesktop.org/series/67467/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
70d2eaa029e3 drm/i915/mg: Use tc_port instead of port parameter to MG registers
-:224: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects?
#224: FILE: drivers/gpu/drm/i915/i915_reg.h:1959:
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
total: 0 errors, 0 warnings, 1 checks, 355 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/mg: Use tc_port instead of port parameter to MG registers
2019-10-01 19:37 [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers José Roberto de Souza
2019-10-01 21:36 ` Lucas De Marchi
2019-10-01 22:49 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-10-01 23:33 ` Patchwork
2019-10-02 10:23 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-01 23:33 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mg: Use tc_port instead of port parameter to MG registers
URL : https://patchwork.freedesktop.org/series/67467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14620
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/index.html
Known issues
------------
Here are the changes found in Patchwork_14620 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bxt-dsi/igt@gem_ctx_exec@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-bxt-dsi/igt@gem_ctx_exec@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_blits@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-icl-u3/igt@gem_linear_blits@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-icl-u3/igt@i915_module_load@reload.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [FAIL][10] ([fdo#111045] / [fdo#111096])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14620
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14620: 70d2eaa029e30d92f61ce87205e70e77f0df15ca @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
70d2eaa029e3 drm/i915/mg: Use tc_port instead of port parameter to MG registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/mg: Use tc_port instead of port parameter to MG registers
2019-10-01 19:37 [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers José Roberto de Souza
` (2 preceding siblings ...)
2019-10-01 23:33 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-02 10:23 ` Patchwork
2019-10-02 19:11 ` Souza, Jose
3 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2019-10-02 10:23 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mg: Use tc_port instead of port parameter to MG registers
URL : https://patchwork.freedesktop.org/series/67467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986_full -> Patchwork_14620_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14620_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl1/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl10/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_exec_balancer@smoke.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +11 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb6/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#109385] / [fdo#111870]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@gem_workarounds@suspend-resume.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([fdo#105763] / [fdo#106538])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk5/igt@i915_pm_rpm@modeset-stress-extra-wait.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#105363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108] / [fdo#106978])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103166])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
#### Possible fixes ####
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_request_retire@retire-vma-not-inactive:
- shard-hsw: [INCOMPLETE][29] ([fdo#103540]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw4/igt@gem_request_retire@retire-vma-not-inactive.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw8/igt@gem_request_retire@retire-vma-not-inactive.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][31] ([fdo#104108] / [fdo#107773]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl6/igt@gem_softpin@noreloc-s3.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl8/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: [DMESG-WARN][33] ([fdo#111870]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
- shard-apl: [DMESG-WARN][35] ([fdo#109385] / [fdo#111870]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [DMESG-WARN][37] ([fdo#111870]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [INCOMPLETE][41] ([fdo#103665] / [fdo#108767]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@i915_suspend@sysfs-reader.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: [FAIL][43] ([fdo#103184] / [fdo#103232]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-hsw: [DMESG-FAIL][45] ([fdo#102614]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][47] ([fdo#105363]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][49] ([fdo#109507]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][51] ([fdo#100368]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl8/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][53] ([fdo#103167]) -> [PASS][54] +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][55] ([fdo#108145] / [fdo#110403]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][57] ([fdo#109642] / [fdo#111068]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@kms_psr2_su@page_flip.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][61] ([fdo#99912]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw6/igt@kms_setmode@basic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw5/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][63] ([fdo#99912]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@kms_setmode@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][65] ([fdo#103665]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][67] ([fdo#109276]) -> [PASS][68] +18 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb3/igt@prime_busy@hang-bsd2.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][69] ([fdo#111330]) -> [SKIP][70] ([fdo#109276]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (16 -> 10)
------------------------------
Missing (6): shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14620
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14620: 70d2eaa029e30d92f61ce87205e70e77f0df15ca @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915/mg: Use tc_port instead of port parameter to MG registers
2019-10-02 10:23 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-10-02 19:11 ` Souza, Jose
0 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2019-10-02 19:11 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org
On Wed, 2019-10-02 at 10:23 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mg: Use tc_port instead of port parameter to MG
> registers
> URL : https://patchwork.freedesktop.org/series/67467/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6986_full -> Patchwork_14620_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed to dinq, thanks for the review Lucas.
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_14620_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@bcs0-s3:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl1/igt@gem_ctx_isolation@bcs0-s3.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl10/igt@gem_ctx_isolation@bcs0-s3.html
>
> * igt@gem_exec_async@concurrent-writes-bsd:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4
> similar issues
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +11
> similar issues
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb6/igt@gem_exec_schedule@promotion-bsd1.html
>
> * igt@gem_userptr_blits@sync-unmap-after-close:
> - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#109385]
> / [fdo#111870]) +1 similar issue
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html
>
> * igt@gem_workarounds@suspend-resume:
> - shard-apl: [PASS][11] -> [DMESG-WARN][12]
> ([fdo#108566]) +1 similar issue
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@gem_workarounds@suspend-resume.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl8/igt@gem_workarounds@suspend-resume.html
>
> * igt@i915_pm_rpm@modeset-stress-extra-wait:
> - shard-glk: [PASS][13] -> [DMESG-WARN][14]
> ([fdo#105763] / [fdo#106538])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk5/igt@i915_pm_rpm@modeset-stress-extra-wait.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#105363])
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-kbl: [PASS][17] -> [INCOMPLETE][18]
> ([fdo#103665]) +1 similar issue
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
> - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
>
> * igt@kms_frontbuffer_tracking@psr-suspend:
> - shard-skl: [PASS][21] -> [INCOMPLETE][22]
> ([fdo#104108] / [fdo#106978])
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_frontbuffer_tracking@psr-suspend.html
>
> * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
> - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103166])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
>
> * igt@kms_psr@psr2_sprite_mmap_gtt:
> - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2
> similar issues
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +3
> similar issues
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_request_retire@retire-vma-not-inactive:
> - shard-hsw: [INCOMPLETE][29] ([fdo#103540]) ->
> [PASS][30]
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw4/igt@gem_request_retire@retire-vma-not-inactive.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw8/igt@gem_request_retire@retire-vma-not-inactive.html
>
> * igt@gem_softpin@noreloc-s3:
> - shard-skl: [INCOMPLETE][31] ([fdo#104108] /
> [fdo#107773]) -> [PASS][32]
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl6/igt@gem_softpin@noreloc-s3.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl8/igt@gem_softpin@noreloc-s3.html
>
> * igt@gem_userptr_blits@dmabuf-sync:
> - shard-kbl: [DMESG-WARN][33] ([fdo#111870]) ->
> [PASS][34]
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
> - shard-apl: [DMESG-WARN][35] ([fdo#109385] /
> [fdo#111870]) -> [PASS][36]
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
>
> * igt@gem_userptr_blits@sync-unmap:
> - shard-hsw: [DMESG-WARN][37] ([fdo#111870]) ->
> [PASS][38]
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html
>
> * igt@i915_suspend@fence-restore-tiled2untiled:
> - shard-apl: [DMESG-WARN][39] ([fdo#108566]) ->
> [PASS][40] +4 similar issues
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
>
> * igt@i915_suspend@sysfs-reader:
> - shard-kbl: [INCOMPLETE][41] ([fdo#103665] /
> [fdo#108767]) -> [PASS][42]
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@i915_suspend@sysfs-reader.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl3/igt@i915_suspend@sysfs-reader.html
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
> - shard-skl: [FAIL][43] ([fdo#103184] / [fdo#103232]) ->
> [PASS][44]
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
>
> * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
> - shard-hsw: [DMESG-FAIL][45] ([fdo#102614]) ->
> [PASS][46]
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][47] ([fdo#105363]) -> [PASS][48]
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-skl: [INCOMPLETE][49] ([fdo#109507]) ->
> [PASS][50]
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip@plain-flip-fb-recreate:
> - shard-skl: [FAIL][51] ([fdo#100368]) -> [PASS][52]
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl8/igt@kms_flip@plain-flip-fb-recreate.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
> - shard-iclb: [FAIL][53] ([fdo#103167]) -> [PASS][54] +5
> similar issues
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
> [54]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [FAIL][55] ([fdo#108145] / [fdo#110403]) ->
> [PASS][56] +1 similar issue
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [56]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_psr2_su@page_flip:
> - shard-iclb: [SKIP][57] ([fdo#109642] / [fdo#111068]) ->
> [PASS][58]
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@kms_psr2_su@page_flip.html
> [58]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_psr2_su@page_flip.html
>
> * igt@kms_psr@psr2_sprite_blt:
> - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60]
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
> [60]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
>
> * igt@kms_setmode@basic:
> - shard-hsw: [FAIL][61] ([fdo#99912]) -> [PASS][62]
> [61]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw6/igt@kms_setmode@basic.html
> [62]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-hsw5/igt@kms_setmode@basic.html
> - shard-kbl: [FAIL][63] ([fdo#99912]) -> [PASS][64]
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@kms_setmode@basic.html
> [64]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl1/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-kbl: [INCOMPLETE][65] ([fdo#103665]) ->
> [PASS][66]
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [66]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
> * igt@prime_busy@hang-bsd2:
> - shard-iclb: [SKIP][67] ([fdo#109276]) -> [PASS][68] +18
> similar issues
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb3/igt@prime_busy@hang-bsd2.html
> [68]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb1/igt@prime_busy@hang-bsd2.html
>
>
> #### Warnings ####
>
> * igt@gem_mocs_settings@mocs-reset-bsd2:
> - shard-iclb: [FAIL][69] ([fdo#111330]) -> [SKIP][70]
> ([fdo#109276]) +1 similar issue
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
> [70]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or
> FAILURE).
>
> [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
> [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
> [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
> [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
> [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
> [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
> [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
> [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
> [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> Participating hosts (16 -> 10)
> ------------------------------
>
> Missing (6): shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4
> shard-tglb5 shard-tglb6
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6986 -> Patchwork_14620
>
> CI-20190529: 20190529
> CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14620: 70d2eaa029e30d92f61ce87205e70e77f0df15ca @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-02 19:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-01 19:37 [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers José Roberto de Souza
2019-10-01 21:36 ` Lucas De Marchi
2019-10-01 22:49 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-10-01 23:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-02 10:23 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-02 19:11 ` Souza, Jose
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