* [PATCH 2/6] drm/i915: setup io-mapping for LMEM
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
@ 2019-10-18 16:55 ` Matthew Auld
2019-10-18 22:50 ` Chris Wilson
2019-10-18 16:55 ` [PATCH 3/6] drm/i915/lmem: support kernel mapping Matthew Auld
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2019-10-18 16:55 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 7a3f96e1f766..051069664074 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -36,8 +36,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(&mem->iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(&mem->iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/6] drm/i915/lmem: support kernel mapping
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
2019-10-18 16:55 ` [PATCH 2/6] drm/i915: setup io-mapping for LMEM Matthew Auld
@ 2019-10-18 16:55 ` Matthew Auld
2019-10-18 22:48 ` Chris Wilson
2019-10-18 16:55 ` [PATCH 4/6] drm/i915/selftests: add write-dword test for LMEM Matthew Auld
` (7 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2019-10-18 16:55 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 ++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 22 +++-
.../drm/i915/selftests/intel_memory_region.c | 113 ++++++++++++++++++
5 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index a53e4463570d..dd69c00434f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_HAS_IOMEM,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
return obj->ops == &i915_gem_lmem_obj_ops;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a387e3ee728b..96008374a412 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -31,10 +31,11 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
-#define I915_GEM_OBJECT_IS_PROXY BIT(2)
-#define I915_GEM_OBJECT_NO_GGTT BIT(3)
-#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(4)
+#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
+#define I915_GEM_OBJECT_IS_PROXY BIT(3)
+#define I915_GEM_OBJECT_NO_GGTT BIT(4)
+#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(5)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index b0ec0959c13f..cf7f5a3cb210 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
+#include "i915_gem_lmem.h"
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -172,7 +173,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
void *ptr;
ptr = page_mask_bits(obj->mm.mapping);
- if (is_vmalloc_addr(ptr))
+ if (i915_gem_object_is_lmem(obj))
+ io_mapping_unmap(ptr);
+ else if (is_vmalloc_addr(ptr))
vunmap(ptr);
else
kunmap(kmap_to_page(ptr));
@@ -231,7 +234,7 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
}
/* The 'mapping' part of i915_gem_object_pin_map() below */
-static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
+static void *i915_gem_object_map(struct drm_i915_gem_object *obj,
enum i915_map_type type)
{
unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
@@ -244,6 +247,13 @@ static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
pgprot_t pgprot;
void *addr;
+ if (i915_gem_object_is_lmem(obj)) {
+ if (type != I915_MAP_WC)
+ return NULL;
+
+ return i915_gem_object_lmem_io_map(obj, 0, obj->base.size);
+ }
+
/* A single page can always be kmapped */
if (n_pages == 1 && type == I915_MAP_WB)
return kmap(sg_page(sgt->sgl));
@@ -285,11 +295,13 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
enum i915_map_type type)
{
enum i915_map_type has_type;
+ unsigned int flags;
bool pinned;
void *ptr;
int err;
- if (unlikely(!i915_gem_object_has_struct_page(obj)))
+ flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | I915_GEM_OBJECT_HAS_IOMEM;
+ if (!i915_gem_object_type_has(obj, flags))
return ERR_PTR(-ENXIO);
err = mutex_lock_interruptible(&obj->mm.lock);
@@ -321,7 +333,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
goto err_unpin;
}
- if (is_vmalloc_addr(ptr))
+ if (i915_gem_object_is_lmem(obj))
+ io_mapping_unmap(ptr);
+ else if (is_vmalloc_addr(ptr))
vunmap(ptr);
else
kunmap(kmap_to_page(ptr));
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 617a35cfac2f..292489371842 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -13,8 +13,10 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_object_blt.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
+#include "selftests/igt_flush_test.h"
#include "selftests/i915_random.h"
static void close_objects(struct intel_memory_region *mem,
@@ -275,6 +277,116 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_cpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ u32 bytes[] = {
+ 0, /* rng placeholder */
+ sizeof(u32),
+ sizeof(u64),
+ 64, /* cl */
+ PAGE_SIZE,
+ PAGE_SIZE - sizeof(u32),
+ PAGE_SIZE - sizeof(u64),
+ PAGE_SIZE - 64,
+ };
+ u32 *vaddr;
+ u32 sz;
+ u32 i;
+ int *order;
+ int count;
+ int err;
+
+ if (!HAS_ENGINE(i915, BCS0))
+ return 0;
+
+ sz = round_up(prandom_u32_state(&prng) % SZ_32M, PAGE_SIZE);
+ sz = max_t(u32, 2 * PAGE_SIZE, sz);
+
+ obj = i915_gem_object_create_lmem(i915, sz, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto out_put;
+ }
+
+ /* Put the pages into a known state -- do so from the gpu for added fun */
+ err = i915_gem_object_fill_blt(obj, i915->engine[BCS0]->kernel_context,
+ 0xdeadbeaf);
+ if (err)
+ goto out_unpin;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ i915_gem_object_unlock(obj);
+ if (err)
+ goto out_unpin;
+
+ count = ARRAY_SIZE(bytes);
+ order = i915_random_order(count * count, &prng);
+ if (!order) {
+ err = -ENOMEM;
+ goto out_unpin;
+ }
+
+ /* We want to throw in a random width/align */
+ bytes[0] = igt_random_offset(&prng, 0, PAGE_SIZE, sizeof(u32),
+ sizeof(u32));
+
+ i = 0;
+ do {
+ u32 offset;
+ u32 align;
+ u32 dword;
+ u32 size;
+ u32 val;
+
+ size = bytes[order[i] % count];
+ i = (i + 1) % (count * count);
+
+ align = bytes[order[i] % count];
+ i = (i + 1) % (count * count);
+
+ align = max_t(u32, sizeof(u32), rounddown_pow_of_two(align));
+
+ offset = igt_random_offset(&prng, 0, obj->base.size,
+ size, align);
+
+ val = prandom_u32_state(&prng);
+ memset32(vaddr + offset / sizeof(u32), val ^ 0xdeadbeaf,
+ size / sizeof(u32));
+
+ /*
+ * Sample random dw -- don't waste precious time reading every
+ * single dw.
+ */
+ dword = igt_random_offset(&prng, offset,
+ offset + size,
+ sizeof(u32), sizeof(u32));
+ dword /= sizeof(u32);
+ if (vaddr[dword] != (val ^ 0xdeadbeaf)) {
+ pr_err("%s vaddr[%u]=%u, val=%u, size=%u, align=%u, offset=%u\n",
+ __func__, dword, vaddr[dword], val ^ 0xdeadbeaf,
+ size, align, offset);
+ err = -EINVAL;
+ break;
+ }
+ } while (!__igt_timeout(end_time, NULL));
+
+out_unpin:
+ i915_gem_object_unpin_map(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
int intel_memory_region_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
@@ -308,6 +420,7 @@ int intel_memory_region_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_lmem_create),
+ SUBTEST(igt_lmem_write_cpu),
};
if (!HAS_LMEM(i915)) {
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/6] drm/i915/selftests: add write-dword test for LMEM
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
2019-10-18 16:55 ` [PATCH 2/6] drm/i915: setup io-mapping for LMEM Matthew Auld
2019-10-18 16:55 ` [PATCH 3/6] drm/i915/lmem: support kernel mapping Matthew Auld
@ 2019-10-18 16:55 ` Matthew Auld
2019-10-18 22:46 ` Chris Wilson
2019-10-18 16:55 ` [PATCH 5/6] drm/i915/selftests: extend coverage to include LMEM huge-pages Matthew Auld
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2019-10-18 16:55 UTC (permalink / raw)
To: intel-gfx
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
.../drm/i915/selftests/intel_memory_region.c | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 292489371842..8a2d1bded47b 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,13 +7,16 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -256,6 +259,125 @@ static int igt_mock_contiguous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, &prng);
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state(&prng);
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -277,6 +399,50 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ I915_RND_STATE(prng);
+ u32 sz;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_file;
+ }
+
+ sz = round_up(prandom_u32_state(&prng) % SZ_32M, PAGE_SIZE);
+
+ obj = i915_gem_object_create_lmem(i915, sz, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_file;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ err = igt_gpu_write(ctx, obj);
+ if (err)
+ pr_err("igt_gpu_write failed(%d)\n", err);
+
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+out_file:
+ mock_file_free(i915, file);
+ return err;
+}
+
static int igt_lmem_write_cpu(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -421,6 +587,7 @@ int intel_memory_region_live_selftests(struct drm_i915_private *i915)
static const struct i915_subtest tests[] = {
SUBTEST(igt_lmem_create),
SUBTEST(igt_lmem_write_cpu),
+ SUBTEST(igt_lmem_write_gpu),
};
if (!HAS_LMEM(i915)) {
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/6] drm/i915/selftests: extend coverage to include LMEM huge-pages
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (2 preceding siblings ...)
2019-10-18 16:55 ` [PATCH 4/6] drm/i915/selftests: add write-dword test for LMEM Matthew Auld
@ 2019-10-18 16:55 ` Matthew Auld
2019-10-18 22:44 ` Chris Wilson
2019-10-18 16:55 ` [PATCH 6/6] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests Matthew Auld
` (5 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2019-10-18 16:55 UTC (permalink / raw)
To: intel-gfx
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +++++++++++++++++-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f27772f6779a..d4892769b739 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -981,7 +982,7 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1013,6 +1014,51 @@ static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1397,6 +1443,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+ * Sanity check that the HW uses huge pages correctly through LMEM
+ * -- ensure that our writes land in the right place.
+ */
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1758,6 +1876,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ppgtt_exhaust_huge),
SUBTEST(igt_ppgtt_gemfs_huge),
SUBTEST(igt_ppgtt_internal_huge),
+ SUBTEST(igt_ppgtt_lmem_huge),
};
struct drm_file *file;
struct i915_gem_context *ctx;
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/6] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (3 preceding siblings ...)
2019-10-18 16:55 ` [PATCH 5/6] drm/i915/selftests: extend coverage to include LMEM huge-pages Matthew Auld
@ 2019-10-18 16:55 ` Matthew Auld
2019-10-18 22:43 ` Chris Wilson
2019-10-18 17:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: support creating LMEM objects Patchwork
` (4 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2019-10-18 16:55 UTC (permalink / raw)
To: intel-gfx
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 198 +++++++++---------
1 file changed, 94 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index d4892769b739..3f7ac4473f33 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1314,20 +1314,33 @@ static int igt_ppgtt_exhaust_huge(void *arg)
return err;
}
+static u32 igt_random_size(struct rnd_state *prng,
+ u32 min_page_size,
+ u32 max_page_size)
+{
+ u32 size;
+ u32 mask;
+
+ GEM_BUG_ON(!is_power_of_2(min_page_size));
+ GEM_BUG_ON(!is_power_of_2(max_page_size));
+ GEM_BUG_ON(min_page_size < PAGE_SIZE);
+ GEM_BUG_ON(min_page_size > max_page_size);
+
+ mask = GENMASK_ULL(ilog2(max_page_size), PAGE_SHIFT);
+ size = prandom_u32_state(prng) & mask;
+ if (size < min_page_size)
+ size |= min_page_size;
+
+ return size;
+}
+
static int igt_ppgtt_internal_huge(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_64K,
- SZ_128K,
- SZ_256K,
- SZ_512K,
- SZ_1M,
- SZ_2M,
- };
- int i;
+ I915_RND_STATE(prng);
+ u32 size;
int err;
/*
@@ -1335,42 +1348,36 @@ static int igt_ppgtt_internal_huge(void *arg)
* -- ensure that our writes land in the right place.
*/
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ size = igt_random_size(&prng, SZ_64K, SZ_2M);
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
-
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
- pr_info("internal unable to allocate huge-page(s) with size=%u\n",
- size);
- goto out_unpin;
- }
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("internal write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
- i915_gem_object_unpin_pages(obj);
- __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
- i915_gem_object_put(obj);
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("%s unable to allocate huge-page(s) with size=%u\n",
+ __func__, size);
+ err = -ENOMEM;
+ goto out_unpin;
}
- return 0;
+ err = igt_write_huge(ctx, obj);
+ if (err)
+ pr_err("%s write-huge failed with size=%u\n", __func__, size);
out_unpin:
i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
out_put:
i915_gem_object_put(obj);
+ if (err == -ENOMEM)
+ err = 0;
+
return err;
}
@@ -1384,14 +1391,8 @@ static int igt_ppgtt_gemfs_huge(void *arg)
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_2M,
- SZ_4M,
- SZ_8M,
- SZ_16M,
- SZ_32M,
- };
- int i;
+ I915_RND_STATE(prng);
+ u32 size;
int err;
/*
@@ -1400,46 +1401,40 @@ static int igt_ppgtt_gemfs_huge(void *arg)
*/
if (!igt_can_allocate_thp(i915)) {
- pr_info("missing THP support, skipping\n");
+ pr_info("%s missing THP support, skipping\n", __func__);
return 0;
}
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_shmem(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
+ size = igt_random_size(&prng, SZ_2M, SZ_32M);
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_2M) {
- pr_info("finishing test early, gemfs unable to allocate huge-page(s) with size=%u\n",
- size);
- goto out_unpin;
- }
+ obj = i915_gem_object_create_shmem(i915, size);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("gemfs write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
- i915_gem_object_unpin_pages(obj);
- __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
- i915_gem_object_put(obj);
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_2M) {
+ pr_info("%s finishing test early, gemfs unable to allocate huge-page(s) with size=%u\n",
+ __func__, size);
+ err = -ENOMEM;
+ goto out_unpin;
}
- return 0;
+ err = igt_write_huge(ctx, obj);
+ if (err)
+ pr_err("%s write-huge failed with size=%u\n", __func__, size);
out_unpin:
i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
out_put:
i915_gem_object_put(obj);
+ if (err == -ENOMEM)
+ err = 0;
+
return err;
}
@@ -1448,13 +1443,8 @@ static int igt_ppgtt_lmem_huge(void *arg)
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_64K,
- SZ_512K,
- SZ_1M,
- SZ_2M,
- };
- int i;
+ I915_RND_STATE(prng);
+ u32 size;
int err;
if (!HAS_LMEM(i915)) {
@@ -1467,49 +1457,49 @@ static int igt_ppgtt_lmem_huge(void *arg)
* -- ensure that our writes land in the right place.
*/
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);
- if (IS_ERR(obj)) {
- err = PTR_ERR(obj);
- if (err == -E2BIG) {
- pr_info("object too big for region!\n");
- return 0;
- }
+ size = SZ_1G;
+try_again:
+ size = igt_random_size(&prng, SZ_64K, rounddown_pow_of_two(size));
- return err;
+ obj = i915_gem_object_create_lmem(i915, size, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ size >>= 1;
+ goto try_again;
}
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
-
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
- pr_info("LMEM unable to allocate huge-page(s) with size=%u\n",
- size);
- goto out_unpin;
- }
+ return err;
+ }
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("LMEM write-huge failed with size=%u\n", size);
- goto out_unpin;
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ if (err == -ENXIO) {
+ i915_gem_object_put(obj);
+ size >>= 1;
+ goto try_again;
}
+ goto out_put;
+ }
- i915_gem_object_unpin_pages(obj);
- __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
- i915_gem_object_put(obj);
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("%s unable to allocate huge-page(s) with size=%u\n",
+ __func__, size);
+ err = -ENOMEM;
+ goto out_unpin;
}
- return 0;
+ err = igt_write_huge(ctx, obj);
+ if (err)
+ pr_err("%s write-huge failed with size=%u\n", __func__, size);
out_unpin:
i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
out_put:
i915_gem_object_put(obj);
- if (err == -ENOMEM)
+ if (err == -ENOMEM || err == -ENXIO)
err = 0;
return err;
--
2.20.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 6/6] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
2019-10-18 16:55 ` [PATCH 6/6] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests Matthew Auld
@ 2019-10-18 22:43 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2019-10-18 22:43 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Quoting Matthew Auld (2019-10-18 17:55:58)
> Ditch the dubious static list of sizes to enumerate, in favour of
> choosing a random size within the limits of each backing store. With
> repeated CI runs this should give us a wider range of object sizes, and
> in turn more page-size combinations, while using less machine time.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 198 +++++++++---------
> 1 file changed, 94 insertions(+), 104 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index d4892769b739..3f7ac4473f33 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1314,20 +1314,33 @@ static int igt_ppgtt_exhaust_huge(void *arg)
> return err;
> }
>
> +static u32 igt_random_size(struct rnd_state *prng,
> + u32 min_page_size,
> + u32 max_page_size)
> +{
> + u32 size;
> + u32 mask;
> +
> + GEM_BUG_ON(!is_power_of_2(min_page_size));
> + GEM_BUG_ON(!is_power_of_2(max_page_size));
> + GEM_BUG_ON(min_page_size < PAGE_SIZE);
> + GEM_BUG_ON(min_page_size > max_page_size);
> +
> + mask = GENMASK_ULL(ilog2(max_page_size), PAGE_SHIFT);
mask = (max_page_size - 1) & PAGE_MASK;
Easier to understand?
> + size = prandom_u32_state(prng) & mask;
> + if (size < min_page_size)
> + size |= min_page_size;
> +
> + return size;
> +}
> +
> static int igt_ppgtt_internal_huge(void *arg)
> {
> struct i915_gem_context *ctx = arg;
> struct drm_i915_private *i915 = ctx->i915;
> struct drm_i915_gem_object *obj;
> - static const unsigned int sizes[] = {
> - SZ_64K,
> - SZ_128K,
> - SZ_256K,
> - SZ_512K,
> - SZ_1M,
> - SZ_2M,
> - };
> - int i;
> + I915_RND_STATE(prng);
> + u32 size;
> int err;
I skipped to the final patch. Did you also leave in checking of the usual
suspects?
The randomised smoketesting looks good,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
The only question being whether we can do some limited smart testing to
catch the most likely bugs.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: support creating LMEM objects
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (4 preceding siblings ...)
2019-10-18 16:55 ` [PATCH 6/6] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests Matthew Auld
@ 2019-10-18 17:54 ` Patchwork
2019-10-18 17:57 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-10-18 17:54 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
69e50fdbd4bb drm/i915: support creating LMEM objects
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 199 lines checked
f60fc450c7d8 drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
8549943366a2 drm/i915/lmem: support kernel mapping
-:200: WARNING:LINE_SPACING: Missing a blank line after declarations
#200: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:284:
+ struct drm_i915_gem_object *obj;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 271 lines checked
ab40af9f7e31 drm/i915/selftests: add write-dword test for LMEM
-:19: CHECK:LINE_SPACING: Please don't use multiple blank lines
#19: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:10:
+
-:88: WARNING:LINE_SPACING: Missing a blank line after declarations
#88: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:314:
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
-:168: WARNING:LINE_SPACING: Missing a blank line after declarations
#168: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:408:
+ struct drm_file *file;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 1 checks, 198 lines checked
22d8dc1c7148 drm/i915/selftests: extend coverage to include LMEM huge-pages
959ff70be991 drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
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^ permalink raw reply [flat|nested] 16+ messages in thread* ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: support creating LMEM objects
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (5 preceding siblings ...)
2019-10-18 17:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: support creating LMEM objects Patchwork
@ 2019-10-18 17:57 ` Patchwork
2019-10-18 18:27 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-10-18 17:57 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: support creating LMEM objects
Okay!
Commit: drm/i915: setup io-mapping for LMEM
Okay!
Commit: drm/i915/lmem: support kernel mapping
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: expected void [noderef] <asn:2> *vaddr
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: got void *[assigned] ptr
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: expected void *
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: got void [noderef] <asn:2> *
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: warning: incorrect type in return expression (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: expected void [noderef] <asn:2> *vaddr
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: got void *[assigned] ptr
+drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: warning: incorrect type in argument 1 (different address spaces)
Commit: drm/i915/selftests: add write-dword test for LMEM
-
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:310:49: error: incompatible types in conditional expression (different address spaces)
Commit: drm/i915/selftests: extend coverage to include LMEM huge-pages
Okay!
Commit: drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: support creating LMEM objects
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (6 preceding siblings ...)
2019-10-18 17:57 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-10-18 18:27 ` Patchwork
2019-10-18 20:43 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-18 21:48 ` [PATCH 1/6] " Chris Wilson
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-10-18 18:27 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130 -> Patchwork_14887
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/index.html
New tests
---------
New tests have been introduced between CI_DRM_7130 and Patchwork_14887:
### New IGT tests (1) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 40 pass(s)
- Exec time: [0.39, 2.24] s
Known issues
------------
Here are the changes found in Patchwork_14887 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_busy@basic-wait-before-default:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-icl-u3/igt@prime_busy@basic-wait-before-default.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-icl-u3/igt@prime_busy@basic-wait-before-default.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}: [INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][9] ([fdo#111880]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-tgl-u/igt@gem_sync@basic-many-each.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-tgl-u/igt@gem_sync@basic-many-each.html
* igt@i915_selftest@live_execlists:
- fi-kbl-soraka: [INCOMPLETE][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [INCOMPLETE][13] ([fdo#111934]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-cfl-guc: [INCOMPLETE][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#111934]: https://bugs.freedesktop.org/show_bug.cgi?id=111934
Participating hosts (50 -> 44)
------------------------------
Additional (1): fi-bwr-2160
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7130 -> Patchwork_14887
CI-20190529: 20190529
CI_DRM_7130: 7d1700ba6820a82809a8dfc8d9cd9f82dbf421c7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5233: 19d40524c102aa086ae536dfb3e81f9b8456099f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14887: 959ff70be9913c9cd7e32bae07587e53006b3578 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
959ff70be991 drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
22d8dc1c7148 drm/i915/selftests: extend coverage to include LMEM huge-pages
ab40af9f7e31 drm/i915/selftests: add write-dword test for LMEM
8549943366a2 drm/i915/lmem: support kernel mapping
f60fc450c7d8 drm/i915: setup io-mapping for LMEM
69e50fdbd4bb drm/i915: support creating LMEM objects
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: support creating LMEM objects
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (7 preceding siblings ...)
2019-10-18 18:27 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-18 20:43 ` Patchwork
2019-10-18 21:48 ` [PATCH 1/6] " Chris Wilson
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-10-18 20:43 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130_full -> Patchwork_14887_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14887_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_flink_race@flink_name:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb7/igt@gem_flink_race@flink_name.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- {shard-tglb}: [SKIP][2] ([fdo#109506]) -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb7/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
New tests
---------
New tests have been introduced between CI_DRM_7130_full and Patchwork_14887_full:
### New IGT tests (1) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 8 pass(s)
- Exec time: [0.26, 2.24] s
Known issues
------------
Here are the changes found in Patchwork_14887_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#110841])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +22 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +5 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_selftest@live_execlists:
- shard-glk: [PASS][14] -> [INCOMPLETE][15] ([fdo#103359] / [k.org#198133])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-glk3/igt@i915_selftest@live_execlists.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-glk3/igt@i915_selftest@live_execlists.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
- shard-apl: [PASS][16] -> [FAIL][17] ([fdo#103232])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][18] -> [FAIL][19] ([fdo#105767])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#100368])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#107931] / [fdo#108303])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl5/igt@kms_flip_tiling@flip-changes-tiling-y.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][24] -> [FAIL][25] ([fdo#103167]) +6 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [PASS][26] -> [FAIL][27] ([fdo#103167] / [fdo#110378])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([fdo#108566]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [PASS][30] -> [INCOMPLETE][31] ([fdo#104108])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][32] -> [FAIL][33] ([fdo#103166])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][34] -> [FAIL][35] ([fdo#108341])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb6/igt@kms_psr@no_drrs.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][36] -> [SKIP][37] ([fdo#109441]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-s3:
- {shard-tglb}: [INCOMPLETE][38] ([fdo#111832]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb4/igt@gem_ctx_isolation@vcs1-s3.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb1/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_eio@wait-10ms:
- {shard-tglb}: [INCOMPLETE][40] ([fdo#111998]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb6/igt@gem_eio@wait-10ms.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb7/igt@gem_eio@wait-10ms.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][42] ([fdo#111325]) -> [PASS][43] +6 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_linear_blits@normal:
- shard-apl: [INCOMPLETE][44] ([fdo#103927]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-apl2/igt@gem_linear_blits@normal.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-apl8/igt@gem_linear_blits@normal.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-hsw: [FAIL][46] ([fdo#112037]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-hsw4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [DMESG-WARN][48] ([fdo#111870]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][50] ([fdo#111870]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
- shard-kbl: [FAIL][52] ([fdo#103232]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [INCOMPLETE][54] ([fdo#103540]) -> [PASS][55] +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][56] ([fdo#109507]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl7/igt@kms_flip@flip-vs-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
- {shard-tglb}: [INCOMPLETE][58] ([fdo#111884]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][60] ([fdo#103167]) -> [PASS][61] +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- {shard-tglb}: [FAIL][62] ([fdo#103167]) -> [PASS][63] +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][64] ([fdo#104108] / [fdo#106978]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl2/igt@kms_frontbuffer_tracking@psr-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][66] ([fdo#108566]) -> [PASS][67] +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][68] ([fdo#108145]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][70] ([fdo#109441]) -> [PASS][71] +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- {shard-tglb}: [INCOMPLETE][72] ([fdo#111832] / [fdo#111850]) -> [PASS][73] +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-tglb4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][74] ([fdo#109276]) -> [PASS][75] +20 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb5/igt@prime_busy@hang-bsd2.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb4/igt@prime_busy@hang-bsd2.html
* igt@tools_test@tools_test:
- shard-glk: [SKIP][76] ([fdo#109271]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-glk2/igt@tools_test@tools_test.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-glk7/igt@tools_test@tools_test.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][78] ([fdo#109276]) -> [FAIL][79] ([fdo#111330])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][80] ([fdo#111330]) -> [SKIP][81] ([fdo#109276])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7130/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/shard-iclb5/igt@gem_mocs_settings@mocs-rc6-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
[fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
[fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
[fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7130 -> Patchwork_14887
CI-20190529: 20190529
CI_DRM_7130: 7d1700ba6820a82809a8dfc8d9cd9f82dbf421c7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5233: 19d40524c102aa086ae536dfb3e81f9b8456099f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14887: 959ff70be9913c9cd7e32bae07587e53006b3578 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14887/index.html
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] drm/i915: support creating LMEM objects
2019-10-18 16:55 [PATCH 1/6] drm/i915: support creating LMEM objects Matthew Auld
` (8 preceding siblings ...)
2019-10-18 20:43 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-10-18 21:48 ` Chris Wilson
9 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2019-10-18 21:48 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Quoting Matthew Auld (2019-10-18 17:55:53)
> diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
> new file mode 100644
> index 000000000000..7a3f96e1f766
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_region_lmem.c
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_memory_region.h"
> +#include "gem/i915_gem_lmem.h"
> +#include "gem/i915_gem_region.h"
> +#include "intel_region_lmem.h"
> +
> +static struct drm_i915_gem_object *
> +lmem_create_object(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj;
> +
> + if (size > BIT(mem->mm.max_order) * mem->mm.chunk_size)
> + return ERR_PTR(-E2BIG);
> +
> + obj = i915_gem_object_alloc();
> + if (!obj)
> + return ERR_PTR(-ENOMEM);
> +
> + drm_gem_private_object_init(&i915->drm, &obj->base, size);
> + i915_gem_object_init(obj, &i915_gem_lmem_obj_ops);
Ah no. Under the current partitioning, you are leaking the GEM object
class out of its hierarchy.
intel_region_*.c provide the abstractions to work with the HW, with
gem/i915_gem_lmem.c wrapping that into a GEM object.
What's the driving force to put the _GEM_ object interface here?
-Chris
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^ permalink raw reply [flat|nested] 16+ messages in thread