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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com
Subject: [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
Date: Mon, 28 Oct 2019 13:40:37 -0700	[thread overview]
Message-ID: <20191028204041.13507-7-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20191028204041.13507-1-radhakrishna.sripada@intel.com>

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..1aa6d468c048 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com
Subject: [Intel-gfx] [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
Date: Mon, 28 Oct 2019 13:40:37 -0700	[thread overview]
Message-ID: <20191028204041.13507-7-radhakrishna.sripada@intel.com> (raw)
Message-ID: <20191028204037.edopG_ydJheV571eDH3LEkExCM6J_JSibYu9Vl6XIZc@z> (raw)
In-Reply-To: <20191028204041.13507-1-radhakrishna.sripada@intel.com>

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..1aa6d468c048 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-28 20:38 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 20:40 [PATCH v6 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 02/10] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 04/10] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 05/10] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` Radhakrishna Sripada [this message]
2019-10-28 20:40   ` [Intel-gfx] [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 07/10] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 08/10] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-30  0:05   ` Chery, Nanley G
2019-10-30  0:05     ` [Intel-gfx] " Chery, Nanley G
2019-11-01  7:00     ` Sripada, Radhakrishna
2019-11-01  7:00       ` [Intel-gfx] " Sripada, Radhakrishna
2019-11-12 17:40       ` Chery, Nanley G
2019-11-12 17:40         ` [Intel-gfx] " Chery, Nanley G
2019-11-13 22:33         ` Chery, Nanley G
2019-11-13 22:33           ` [Intel-gfx] " Chery, Nanley G
2019-10-28 20:40 ` [PATCH v6 10/10] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Radhakrishna Sripada
2019-10-28 20:40   ` [Intel-gfx] " Radhakrishna Sripada
2019-10-29  0:02 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev9) Patchwork
2019-10-29  0:02   ` [Intel-gfx] " Patchwork
2019-10-29  0:49 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-29  0:49   ` [Intel-gfx] " Patchwork

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