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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers
Date: Tue, 29 Oct 2019 11:24:28 -0700	[thread overview]
Message-ID: <20191029182428.GA15634@InViCtUs> (raw)
In-Reply-To: <20191026001323.216052-1-jose.souza@intel.com>

On Fri, Oct 25, 2019 at 05:13:19PM -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
> 
> Cc: Ramalingam C <ramalingam.c@intel.com>
LGTM,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 746326784a4d..09cb43f4e976 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,15 +7663,15 @@ enum {
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
>  #define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> +#define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
> +#define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
> +#define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
> +#define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers
Date: Tue, 29 Oct 2019 11:24:28 -0700	[thread overview]
Message-ID: <20191029182428.GA15634@InViCtUs> (raw)
Message-ID: <20191029182428.jklDmgmuZEjmLEwVl35Se8IQBhM-1qcXIg2cmMu3fyY@z> (raw)
In-Reply-To: <20191026001323.216052-1-jose.souza@intel.com>

On Fri, Oct 25, 2019 at 05:13:19PM -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
> 
> Cc: Ramalingam C <ramalingam.c@intel.com>
LGTM,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 746326784a4d..09cb43f4e976 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,15 +7663,15 @@ enum {
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
>  #define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> +#define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
> +#define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
> +#define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
> +#define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-29 18:22 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-26  0:13 [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers José Roberto de Souza
2019-10-26  0:13 ` [Intel-gfx] " José Roberto de Souza
2019-10-26  0:13 ` [PATCH 2/5] drm/i915/display: Handle fused off HDCP José Roberto de Souza
2019-10-26  0:13   ` [Intel-gfx] " José Roberto de Souza
2019-10-26  0:13 ` [PATCH 3/5] drm/i915/display: Check if FBC is fused off José Roberto de Souza
2019-10-26  0:13   ` [Intel-gfx] " José Roberto de Souza
2019-10-26  0:13 ` [PATCH 4/5] drm/i915/display/icl+: Check if DMC " José Roberto de Souza
2019-10-26  0:13   ` [Intel-gfx] " José Roberto de Souza
2019-10-26  0:13 ` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC José Roberto de Souza
2019-10-26  0:13   ` [Intel-gfx] " José Roberto de Souza
2019-10-26  2:04 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add two spaces before the SKL_DFSM registers Patchwork
2019-10-26  2:04   ` [Intel-gfx] " Patchwork
2019-10-27 20:42 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-27 20:42   ` [Intel-gfx] " Patchwork
2019-10-29 19:36   ` Souza, Jose
2019-10-29 19:36     ` [Intel-gfx] " Souza, Jose
2019-10-29 18:24 ` Radhakrishna Sripada [this message]
2019-10-29 18:24   ` [Intel-gfx] [PATCH 1/5] " Radhakrishna Sripada
2019-11-01  4:44 ` Ramalingam C
2019-11-01  4:44   ` [Intel-gfx] " Ramalingam C

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