From: Anshuamn Gupta <anshuman.gupta@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] i915: Expose panel power cycle delay to i915_panel_timings
Date: Tue, 3 Dec 2019 11:43:16 +0530 [thread overview]
Message-ID: <20191203061315.GA8432@intel.com> (raw)
In-Reply-To: <875zj4m700.fsf@intel.com>
On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote:
> On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Putting down the AUX power domain reference count in
> > edp vdd off async sequence takes too much of time
> > (relative to panel power cycle delay) therefore it make sense
> > to expose the panel power cycle delay to i915_panel_timings
> > along with other delays.
> > It can be use by DC state IGT to wait for strict power cycle delay
> > in order to check for various DC state counters.
>
> Catching up on review, are you suggesting to look at this kind of
> debugfs files for tests? Please find another way.
Actually on few panels power cycle delay is too much that it is required
to wait for 6 seconds in igt for an timeout, but this could really affect
CI execution time on panel with lesser power cycle delay.
(https://patchwork.freedesktop.org/series/68478/)
For this specific reason i thought it may be good to expose
panel power cycle delay with other panel delay and use that
in igt.
Thanks ,
Anshuman.
>
> I don't mind having the debugfs info per se.
>
> BR,
> Jani.
>
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index cab632791f73..c075cc2b7bb5 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data)
> > intel_dp->panel_power_up_delay);
> > seq_printf(m, "Panel power down delay: %d\n",
> > intel_dp->panel_power_down_delay);
> > + seq_printf(m, "Panel power cycle delay: %d\n",
> > + intel_dp->panel_power_cycle_delay);
> > seq_printf(m, "Backlight on delay: %d\n",
> > intel_dp->backlight_on_delay);
> > seq_printf(m, "Backlight off delay: %d\n",
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Anshuamn Gupta <anshuman.gupta@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] i915: Expose panel power cycle delay to i915_panel_timings
Date: Tue, 3 Dec 2019 11:43:16 +0530 [thread overview]
Message-ID: <20191203061315.GA8432@intel.com> (raw)
Message-ID: <20191203061316.APNEuZy_fRUMrcJEFv1L7eOxRrdh6fqEgxPjLfV0THU@z> (raw)
In-Reply-To: <875zj4m700.fsf@intel.com>
On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote:
> On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Putting down the AUX power domain reference count in
> > edp vdd off async sequence takes too much of time
> > (relative to panel power cycle delay) therefore it make sense
> > to expose the panel power cycle delay to i915_panel_timings
> > along with other delays.
> > It can be use by DC state IGT to wait for strict power cycle delay
> > in order to check for various DC state counters.
>
> Catching up on review, are you suggesting to look at this kind of
> debugfs files for tests? Please find another way.
Actually on few panels power cycle delay is too much that it is required
to wait for 6 seconds in igt for an timeout, but this could really affect
CI execution time on panel with lesser power cycle delay.
(https://patchwork.freedesktop.org/series/68478/)
For this specific reason i thought it may be good to expose
panel power cycle delay with other panel delay and use that
in igt.
Thanks ,
Anshuman.
>
> I don't mind having the debugfs info per se.
>
> BR,
> Jani.
>
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index cab632791f73..c075cc2b7bb5 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data)
> > intel_dp->panel_power_up_delay);
> > seq_printf(m, "Panel power down delay: %d\n",
> > intel_dp->panel_power_down_delay);
> > + seq_printf(m, "Panel power cycle delay: %d\n",
> > + intel_dp->panel_power_cycle_delay);
> > seq_printf(m, "Backlight on delay: %d\n",
> > intel_dp->backlight_on_delay);
> > seq_printf(m, "Backlight off delay: %d\n",
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-12-03 6:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 16:33 [PATCH] i915: Expose panel power cycle delay to i915_panel_timings Anshuman Gupta
2019-11-18 16:33 ` [Intel-gfx] " Anshuman Gupta
2019-11-18 19:08 ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-11-18 19:08 ` [Intel-gfx] " Patchwork
2019-11-28 14:05 ` [PATCH] " Jani Nikula
2019-11-28 14:05 ` [Intel-gfx] " Jani Nikula
2019-12-03 6:13 ` Anshuamn Gupta [this message]
2019-12-03 6:13 ` Anshuamn Gupta
2019-12-03 7:59 ` Jani Nikula
2019-12-03 7:59 ` [Intel-gfx] " Jani Nikula
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