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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
Date: Wed, 26 Feb 2020 22:34:49 +0200	[thread overview]
Message-ID: <20200226203455.23032-8-imre.deak@intel.com> (raw)
In-Reply-To: <20200226203455.23032-1-imre.deak@intel.com>

For clarity keep the SKL DPLL ref clock in a variable instead of
open-coding it. Store the value in kHZ units as done on other platforms.
This allows us in a later patch to keep track of the DPLL ref clock in a
more unified way across all platforms.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5057f7636534..a4d27dfaec9a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1369,6 +1369,7 @@ struct skl_wrpll_params {
 
 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
 				      u64 afe_clock,
+				      int ref_clock,
 				      u64 central_freq,
 				      u32 p0, u32 p1, u32 p2)
 {
@@ -1428,14 +1429,15 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
 	 * Intermediate values are in Hz.
 	 * Divide by MHz to match bsepc
 	 */
-	params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
+	params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
 	params->dco_fraction =
-		div_u64((div_u64(dco_freq, 24) -
+		div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
 			 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
 }
 
 static bool
 skl_ddi_calculate_wrpll(int clock /* in Hz */,
+			int ref_clock,
 			struct skl_wrpll_params *wrpll_params)
 {
 	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
@@ -1501,8 +1503,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 	 */
 	p0 = p1 = p2 = 0;
 	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
-	skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
-				  p0, p1, p2);
+	skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
+				  ctx.central_freq, p0, p1, p2);
 
 	return true;
 }
@@ -1520,7 +1522,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 
 	ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
 
-	if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
+	if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
 				     &wrpll_params))
 		return false;
 
@@ -1545,6 +1547,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 
 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
 {
+	int ref_clock = 24000;
 	u32 p0, p1, p2, dco_freq;
 
 	p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1586,11 +1589,11 @@ static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
 		break;
 	}
 
-	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
-		* 24 * 1000;
+	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
+		   ref_clock;
 
-	dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
-		     * 24 * 1000) / 0x8000;
+	dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
+		    ref_clock / 0x8000;
 
 	if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
-- 
2.23.1

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  parent reply	other threads:[~2020-02-26 20:35 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` Imre Deak [this message]
2020-02-26 20:34 ` [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
2020-02-27 17:57   ` Ville Syrjälä
2020-02-27 18:34     ` Imre Deak
2020-02-27 18:49       ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
2020-02-27 17:58   ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
2020-02-27 18:13   ` Ville Syrjälä
2020-02-27 19:01     ` Imre Deak
2020-02-28 15:33   ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-02-27  4:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking Patchwork
2020-02-27  4:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-27  4:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28  0:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-02-28 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2) Patchwork
2020-02-28 17:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-28 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 13:31   ` Imre Deak
2020-03-02 14:30     ` Vudum, Lakshminarayana
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-03-02 17:39   ` Imre Deak

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