From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
Date: Thu, 27 Feb 2020 19:58:07 +0200 [thread overview]
Message-ID: <20200227175807.GX13686@intel.com> (raw)
In-Reply-To: <20200226203455.23032-13-imre.deak@intel.com>
On Wed, Feb 26, 2020 at 10:34:54PM +0200, Imre Deak wrote:
> Instead of reading out the WRPLL/SPLL control values from HW, we can use
> the DPLL state that was already read out, or swapped-to.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b87b4ff5de52..7e6da58a47c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> const struct intel_shared_dpll *pll)
> {
> - i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
> - WRPLL_CTL(0) : WRPLL_CTL(1);
> int refclk;
> int n, p, r;
> - u32 wrpll;
> + u32 wrpll = pll->state.hw_state.wrpll;
>
> - wrpll = intel_de_read(dev_priv, reg);
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> /*
> @@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
> {
> int link_clock = 0;
>
> - switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
> + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
> case SPLL_FREQ_810MHz:
> link_clock = 81000;
> break;
> --
> 2.23.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-02-27 17:58 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
2020-02-27 17:57 ` Ville Syrjälä
2020-02-27 18:34 ` Imre Deak
2020-02-27 18:49 ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
2020-02-27 17:58 ` Ville Syrjälä [this message]
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
2020-02-27 18:13 ` Ville Syrjälä
2020-02-27 19:01 ` Imre Deak
2020-02-28 15:33 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-02-27 4:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking Patchwork
2020-02-27 4:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-27 4:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28 0:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-02-28 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2) Patchwork
2020-02-28 17:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-28 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 13:31 ` Imre Deak
2020-03-02 14:30 ` Vudum, Lakshminarayana
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-03-02 17:39 ` Imre Deak
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