From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux
Date: Mon, 6 Apr 2020 18:11:56 -0700 [thread overview]
Message-ID: <20200407011157.362092-7-jose.souza@intel.com> (raw)
In-Reply-To: <20200407011157.362092-1-jose.souza@intel.com>
As described in "drm/i915/tc/icl: Implement TC cold sequences" users
of TC functions should held aux power well during access to avoid
read garbage due HW in TC cold state.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 83861653768d..e473bb4a9b0b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -95,6 +95,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
intel_display_power_put_async(i915, domain, wakeref);
}
+static void
+is_tc_cold_blocked(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ bool enabled;
+
+ if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
+ return;
+
+ enabled = intel_display_power_is_enabled(i915,
+ tc_cold_get_power_domain(dig_port));
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -104,7 +118,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
lane_mask = intel_uncore_read(uncore,
PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
- drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
+ is_tc_cold_blocked(dig_port);
lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -119,7 +133,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
pin_mask = intel_uncore_read(uncore,
PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
- drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
+ is_tc_cold_blocked(dig_port);
return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -134,6 +148,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
if (dig_port->tc_mode != TC_PORT_DP_ALT)
return 4;
+ is_tc_cold_blocked(dig_port);
+
lane_mask = 0;
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
@@ -166,6 +182,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
drm_WARN_ON(&i915->drm,
lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
+ is_tc_cold_blocked(dig_port);
+
val = intel_uncore_read(uncore,
PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
--
2.26.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-04-07 1:10 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-07 1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
2020-04-07 15:15 ` Imre Deak
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
2020-04-07 15:20 ` Imre Deak
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
2020-04-07 15:42 ` Imre Deak
2020-04-07 20:01 ` Souza, Jose
2020-04-07 21:52 ` Imre Deak
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
2020-04-07 15:42 ` Imre Deak
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
2020-04-07 16:02 ` Imre Deak
2020-04-07 21:20 ` Souza, Jose
2020-04-07 1:11 ` José Roberto de Souza [this message]
2020-04-07 16:04 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux Imre Deak
2020-04-07 18:20 ` Imre Deak
2020-04-07 1:11 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
2020-04-07 16:18 ` Imre Deak
2020-04-07 1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Patchwork
2020-04-07 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-07 7:35 ` [Intel-gfx] [v2, 1/8] " You-Sheng Yang
2020-04-07 10:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] " Patchwork
2020-04-07 21:56 ` Souza, Jose
2020-04-07 15:13 ` [Intel-gfx] [PATCH v2 1/8] " Imre Deak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200407011157.362092-7-jose.souza@intel.com \
--to=jose.souza@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox